skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:038378/0272   Pages: 8
Recorded: 04/07/2016
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 73
1
Patent #:
8067831
Issue Dt:
11/29/2011
Application #:
11162629
Filing Dt:
09/16/2005
Publication #:
US20070063331
Pub Dt:
03/22/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PLANAR INTERCONNECTS
2
Patent #:
8089143
Issue Dt:
01/03/2012
Application #:
11162635
Filing Dt:
09/16/2005
Publication #:
US20060175695
Pub Dt:
08/10/2006
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM USING INTERPOSER
3
Patent #:
8093694
Issue Dt:
01/10/2012
Application #:
11164088
Filing Dt:
11/10/2005
Publication #:
US20060180904
Pub Dt:
08/17/2006
Title:
METHOD OF MANUFACTURING NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING ETCHED DIFFERENTIAL HEIGHT LEAD STRUCTURES
4
Patent #:
8039365
Issue Dt:
10/18/2011
Application #:
11456845
Filing Dt:
07/11/2006
Publication #:
US20080012095
Pub Dt:
01/17/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING WAFER LEVEL SPACER
5
Patent #:
8067271
Issue Dt:
11/29/2011
Application #:
11532509
Filing Dt:
09/15/2006
Publication #:
US20080067640
Pub Dt:
03/20/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
6
Patent #:
8093693
Issue Dt:
01/10/2012
Application #:
11532510
Filing Dt:
09/15/2006
Publication #:
US20080067698
Pub Dt:
03/20/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
7
Patent #:
8089166
Issue Dt:
01/03/2012
Application #:
11618805
Filing Dt:
12/30/2006
Publication #:
US20080157401
Pub Dt:
07/03/2008
Title:
INTEGRATED CIRCUIT PACKAGE WITH TOP PAD
8
Patent #:
8035207
Issue Dt:
10/11/2011
Application #:
11618807
Filing Dt:
12/30/2006
Publication #:
US20080157321
Pub Dt:
07/03/2008
Title:
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH RECESS
9
Patent #:
8039947
Issue Dt:
10/18/2011
Application #:
11749693
Filing Dt:
05/16/2007
Publication #:
US20070267731
Pub Dt:
11/22/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIFFERENT MOLD LOCKING FEATURES
10
Patent #:
8062934
Issue Dt:
11/22/2011
Application #:
11766785
Filing Dt:
06/21/2007
Publication #:
US20080006929
Pub Dt:
01/10/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH GROUND BONDS
11
Patent #:
8039960
Issue Dt:
10/18/2011
Application #:
11859416
Filing Dt:
09/21/2007
Publication #:
US20090079094
Pub Dt:
03/26/2009
Title:
SOLDER BUMP WITH INNER CORE PILLAR IN SEMICONDUCTOR PACKAGE
12
Patent #:
8067825
Issue Dt:
11/29/2011
Application #:
11863700
Filing Dt:
09/28/2007
Publication #:
US20090085181
Pub Dt:
04/02/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DIE
13
Patent #:
8039302
Issue Dt:
10/18/2011
Application #:
11952502
Filing Dt:
12/07/2007
Publication #:
US20090146282
Pub Dt:
06/11/2009
Title:
SEMICONDUCTOR PACKAGE AND METHOD OF FORMING SIMILAR STRUCTURE FOR TOP AND BOTTOM BONDING PADS
14
Patent #:
8084849
Issue Dt:
12/27/2011
Application #:
11954603
Filing Dt:
12/12/2007
Publication #:
US20090152692
Pub Dt:
06/18/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKING
15
Patent #:
8067275
Issue Dt:
11/29/2011
Application #:
11957845
Filing Dt:
12/17/2007
Publication #:
US20090155961
Pub Dt:
06/18/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE INTEGRATION
16
Patent #:
8035210
Issue Dt:
10/11/2011
Application #:
11966219
Filing Dt:
12/28/2007
Publication #:
US20090166835
Pub Dt:
07/02/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERPOSER
17
Patent #:
8048776
Issue Dt:
11/01/2011
Application #:
12036000
Filing Dt:
02/22/2008
Publication #:
US20090212429
Pub Dt:
08/27/2009
Title:
SEMICONDUCTOR DEVICE AND METHOD OF SUPPORTING A WAFER DURING BACKGRINDING AND REFLOW OF SOLDER BUMPS
18
Patent #:
8067307
Issue Dt:
11/29/2011
Application #:
12037291
Filing Dt:
02/26/2008
Publication #:
US20090212408
Pub Dt:
08/27/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES
19
Patent #:
8084302
Issue Dt:
12/27/2011
Application #:
12044803
Filing Dt:
03/07/2008
Publication #:
US20090224402
Pub Dt:
09/10/2009
Title:
SEMICONDUCTOR PACKAGE HAVING SEMICONDUCTOR DIE WITH INTERNAL VERTICAL INTERCONNECT STRUCTURE AND METHOD THEREFOR
20
Patent #:
8067828
Issue Dt:
11/29/2011
Application #:
12046369
Filing Dt:
03/11/2008
Publication #:
US20090230532
Pub Dt:
09/17/2009
Title:
SYSTEM FOR SOLDER BALL INNER STACKING MODULE CONNECTION
21
Patent #:
8035211
Issue Dt:
10/11/2011
Application #:
12055634
Filing Dt:
03/26/2008
Publication #:
US20090243070
Pub Dt:
10/01/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORT STRUCTURE UNDER WIRE-IN-FILM ADHESIVE
22
Patent #:
8072079
Issue Dt:
12/06/2011
Application #:
12057199
Filing Dt:
03/27/2008
Publication #:
US20090243045
Pub Dt:
10/01/2009
Title:
THROUGH HOLE VIAS AT SAW STREETS INCLUDING PROTRUSIONS OR RECESSES FOR INTERCONNECTION
23
Patent #:
8072047
Issue Dt:
12/06/2011
Application #:
12124793
Filing Dt:
05/21/2008
Publication #:
US20090289335
Pub Dt:
11/26/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SHIELD AND TIE BAR
24
Patent #:
8049314
Issue Dt:
11/01/2011
Application #:
12126684
Filing Dt:
05/23/2008
Publication #:
US20090127683
Pub Dt:
05/21/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INSULATOR OVER CIRCUITRY
25
Patent #:
8101460
Issue Dt:
01/24/2012
Application #:
12133216
Filing Dt:
06/04/2008
Publication #:
US20090302435
Pub Dt:
12/10/2009
Title:
SEMICONDUCTOR DEVICE AND METHOD OF SHIELDING SEMICONDUCTOR DIE FROM INTER-DEVICE INTERFERENCE
26
Patent #:
8050047
Issue Dt:
11/01/2011
Application #:
12136002
Filing Dt:
06/09/2008
Publication #:
US20090016032
Pub Dt:
01/15/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLEXIBLE SUBSTRATE AND RECESSED PACKAGE
27
Patent #:
8039942
Issue Dt:
10/18/2011
Application #:
12141059
Filing Dt:
06/17/2008
Publication #:
US20090309204
Pub Dt:
12/17/2009
Title:
BALL GRID ARRAY PACKAGE STACKING SYSTEM
28
Patent #:
8102666
Issue Dt:
01/24/2012
Application #:
12194506
Filing Dt:
08/19/2008
Publication #:
US20100046183
Pub Dt:
02/25/2010
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
29
Patent #:
8043894
Issue Dt:
10/25/2011
Application #:
12198491
Filing Dt:
08/26/2008
Publication #:
US20100052131
Pub Dt:
03/04/2010
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER
30
Patent #:
8039311
Issue Dt:
10/18/2011
Application #:
12205841
Filing Dt:
09/05/2008
Publication #:
US20100059884
Pub Dt:
03/11/2010
Title:
LEADLESS SEMICONDUCTOR CHIP CARRIER SYSTEM
31
Patent #:
8063475
Issue Dt:
11/22/2011
Application #:
12239715
Filing Dt:
09/26/2008
Publication #:
US20100078789
Pub Dt:
04/01/2010
Title:
SEMICONDUCTOR PACKAGE SYSTEM WITH THROUGH SILICON VIA INTERPOSER
32
Patent #:
8106502
Issue Dt:
01/31/2012
Application #:
12272751
Filing Dt:
11/17/2008
Publication #:
US20100123229
Pub Dt:
05/20/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLATED PAD AND METHOD OF MANUFACTURE THEREOF
33
Patent #:
8080885
Issue Dt:
12/20/2011
Application #:
12273547
Filing Dt:
11/19/2008
Publication #:
US20100123251
Pub Dt:
05/20/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI LEVEL CONTACT AND METHOD OF MANUFACTURE THEREOF
34
Patent #:
8063477
Issue Dt:
11/22/2011
Application #:
12328762
Filing Dt:
12/04/2008
Publication #:
US20100140770
Pub Dt:
06/10/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING ASYMMETRIC ENCAPSULATION STRUCTURES AND METHOD OF MANUFACTURE THEREOF
35
Patent #:
8035237
Issue Dt:
10/11/2011
Application #:
12398163
Filing Dt:
03/04/2009
Publication #:
US20090174064
Pub Dt:
07/09/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SLUG
36
Patent #:
8106498
Issue Dt:
01/31/2012
Application #:
12398466
Filing Dt:
03/05/2009
Publication #:
US20100224975
Pub Dt:
09/09/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A DUAL BOARD-ON-CHIP STRUCTURE AND METHOD OF MANUFACTURE THEREOF
37
Patent #:
8035458
Issue Dt:
10/11/2011
Application #:
12403234
Filing Dt:
03/12/2009
Publication #:
US20100231317
Pub Dt:
09/16/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF INTEGRATING BALUN AND RF COUPLER ON A COMMON SUBSTRATE
38
Patent #:
8093151
Issue Dt:
01/10/2012
Application #:
12404069
Filing Dt:
03/13/2009
Publication #:
US20100230822
Pub Dt:
09/16/2010
Title:
SEMICONDUCTOR DIE AND METHOD OF FORMING NOISE ABSORBING REGIONS BETWEEN THVS IN PERIPHERAL REGION OF THE DIE
39
Patent #:
8097489
Issue Dt:
01/17/2012
Application #:
12409142
Filing Dt:
03/23/2009
Publication #:
US20100237477
Pub Dt:
09/23/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING PRE-FABRICATED SHIELDING FRAME OVER SEMICONDUCTOR DIE
40
Patent #:
8039316
Issue Dt:
10/18/2011
Application #:
12423099
Filing Dt:
04/14/2009
Publication #:
US20100258928
Pub Dt:
10/14/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND HEAT SPREADER WITH OPENINGS AND METHOD OF MANUFACTURE THEREOF
41
Patent #:
8080446
Issue Dt:
12/20/2011
Application #:
12473253
Filing Dt:
05/27/2009
Publication #:
US20100301469
Pub Dt:
12/02/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER INTERCONNECTIONS AND METHOD OF MANUFACTURE THEREOF
42
Patent #:
8072059
Issue Dt:
12/06/2011
Application #:
12476447
Filing Dt:
06/02/2009
Publication #:
US20090236686
Pub Dt:
09/24/2009
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING UBM FIXED RELATIVE TO INTERCONNECT STRUCTURE FOR ALIGNMENT OF SEMICONDUCTOR DIE
43
Patent #:
8067308
Issue Dt:
11/29/2011
Application #:
12480317
Filing Dt:
06/08/2009
Publication #:
US20100308443
Pub Dt:
12/09/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INTERCONNECT STRUCTURE WITH TSV USING ENCAPSULANT FOR STRUCTURAL SUPPORT
44
Patent #:
8039303
Issue Dt:
10/18/2011
Application #:
12481404
Filing Dt:
06/09/2009
Publication #:
US20090309212
Pub Dt:
12/17/2009
Title:
METHOD OF FORMING STRESS RELIEF LAYER BETWEEN DIE AND INTERCONNECT STRUCTURE
45
Patent #:
8105915
Issue Dt:
01/31/2012
Application #:
12484146
Filing Dt:
06/12/2009
Publication #:
US20100314780
Pub Dt:
12/16/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT STRUCTURE BETWEEN NON-LINEAR PORTIONS OF CONDUCTIVE LAYERS
46
Patent #:
8106499
Issue Dt:
01/31/2012
Application #:
12488555
Filing Dt:
06/20/2009
Publication #:
US20100320583
Pub Dt:
12/23/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A DUAL SUBSTRATE PACKAGE AND METHOD OF MANUFACTURE THEREOF
47
Patent #:
8039304
Issue Dt:
10/18/2011
Application #:
12540174
Filing Dt:
08/12/2009
Publication #:
US20110037169
Pub Dt:
02/17/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF DUAL-MOLDING DIE FORMED ON OPPOSITE SIDES OF BUILD-UP INTERCONNECT STRUCTURES
48
Patent #:
8102040
Issue Dt:
01/24/2012
Application #:
12544555
Filing Dt:
08/20/2009
Publication #:
US20090309207
Pub Dt:
12/17/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIE AND PACKAGE COMBINATION
49
Patent #:
8035235
Issue Dt:
10/11/2011
Application #:
12560312
Filing Dt:
09/15/2009
Publication #:
US20110062574
Pub Dt:
03/17/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
50
Patent #:
8076232
Issue Dt:
12/13/2011
Application #:
12562414
Filing Dt:
09/18/2009
Publication #:
US20100007019
Pub Dt:
01/14/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPOSITE BUMP-ON-LEAD INTERCONNECTION
51
Patent #:
8067272
Issue Dt:
11/29/2011
Application #:
12578797
Filing Dt:
10/14/2009
Publication #:
US20100038768
Pub Dt:
02/18/2010
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND MANUFACTURING METHOD THEREOF
52
Patent #:
8080867
Issue Dt:
12/20/2011
Application #:
12608587
Filing Dt:
10/29/2009
Publication #:
US20110101542
Pub Dt:
05/05/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE THEREOF
53
Patent #:
8080882
Issue Dt:
12/20/2011
Application #:
12641958
Filing Dt:
12/18/2009
Publication #:
US20100096731
Pub Dt:
04/22/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED-DOWN RDL AND RECESSED THV IN PERIPHERAL REGION OF THE DEVICE
54
Patent #:
8097496
Issue Dt:
01/17/2012
Application #:
12703450
Filing Dt:
02/10/2010
Publication #:
US20100144100
Pub Dt:
06/10/2010
Title:
METHOD OF FORMING QUAD FLAT PACKAGE
55
Patent #:
8097935
Issue Dt:
01/17/2012
Application #:
12703461
Filing Dt:
02/10/2010
Publication #:
US20100140761
Pub Dt:
06/10/2010
Title:
QUAD FLAT PACKAGE
56
Patent #:
8067306
Issue Dt:
11/29/2011
Application #:
12714320
Filing Dt:
02/26/2010
Publication #:
US20110210437
Pub Dt:
09/01/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXPOSED CONDUCTOR AND METHOD OF MANUFACTURE THEREOF
57
Patent #:
8039384
Issue Dt:
10/18/2011
Application #:
12720029
Filing Dt:
03/09/2010
Publication #:
US20110221058
Pub Dt:
09/15/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON DIFFERENT HEIGHT TRACES
58
Patent #:
8049322
Issue Dt:
11/01/2011
Application #:
12772128
Filing Dt:
04/30/2010
Publication #:
US20100230796
Pub Dt:
09/16/2010
Title:
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM AND METHOD FOR MAKING THEREOF
59
Patent #:
8049328
Issue Dt:
11/01/2011
Application #:
12775188
Filing Dt:
05/06/2010
Publication #:
US20100213610
Pub Dt:
08/26/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR 3-D DEVICES USING ENCAPSULANT FOR STRUCTURAL SUPPORT
60
Patent #:
8106500
Issue Dt:
01/31/2012
Application #:
12777023
Filing Dt:
05/10/2010
Publication #:
US20100219523
Pub Dt:
09/02/2010
Title:
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM
61
Patent #:
8067268
Issue Dt:
11/29/2011
Application #:
12782992
Filing Dt:
05/19/2010
Publication #:
US20100224979
Pub Dt:
09/09/2010
Title:
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
62
Patent #:
8062929
Issue Dt:
11/22/2011
Application #:
12788785
Filing Dt:
05/27/2010
Publication #:
US20100233852
Pub Dt:
09/16/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF STACKING SAME SIZE SEMICONDUCTOR DIE ELECTRICALLY CONNECTED THROUGH CONDUCTIVE VIA FORMED AROUND PERIPHERY OF THE DIE
63
Patent #:
8105872
Issue Dt:
01/31/2012
Application #:
12792066
Filing Dt:
06/02/2010
Publication #:
US20110298109
Pub Dt:
12/08/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED EMI SHIELDING FRAME WITH CAVITIES CONTAINING PENETRABLE MATERIAL OVER SEMICONDUCTOR DIE
64
Patent #:
8039275
Issue Dt:
10/18/2011
Application #:
12792629
Filing Dt:
06/02/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUNDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
65
Patent #:
8076757
Issue Dt:
12/13/2011
Application #:
12830390
Filing Dt:
07/05/2010
Publication #:
US20100270661
Pub Dt:
10/28/2010
Title:
SEMICONDUCTOR DEVICE HAVING ELECTRICAL DEVICES MOUNTED TO IPD STRUCTURE AND METHOD OF SHIELDING ELECTROMAGNETIC INTERFERENCE
66
Patent #:
8076184
Issue Dt:
12/13/2011
Application #:
12857395
Filing Dt:
08/16/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER-LEVEL MULTI-ROW ETCHED LEADFRAME WITH BASE LEADS AND EMBEDDED SEMICONDUCTOR DIE
67
Patent #:
8097490
Issue Dt:
01/17/2012
Application #:
12870696
Filing Dt:
08/27/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED INTERCONNECT LAYER FOR STACKED SEMICONDUCTOR DIE
68
Patent #:
8093727
Issue Dt:
01/10/2012
Application #:
12871031
Filing Dt:
08/30/2010
Publication #:
US20100320621
Pub Dt:
12/23/2010
Title:
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH SIDE-BY-SIDE AND OFFSET STACKING AND METHOD FOR MANUFACTURING THEREOF
69
Patent #:
8080445
Issue Dt:
12/20/2011
Application #:
12876425
Filing Dt:
09/07/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WLP WITH SEMICONDUCTOR DIE EMBEDDED WITHIN PENETRABLE ENCAPSULANT BETWEEN TSV INTERPOSERS
70
Patent #:
8097943
Issue Dt:
01/17/2012
Application #:
12905797
Filing Dt:
10/15/2010
Publication #:
US20110024903
Pub Dt:
02/03/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER LEVEL GROUND PLANE AND POWER RING
71
Patent #:
8093100
Issue Dt:
01/10/2012
Application #:
12949835
Filing Dt:
11/19/2010
Publication #:
US20110062591
Pub Dt:
03/17/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING THROUGH SILICON VIA WITH DIRECT INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
72
Patent #:
8067832
Issue Dt:
11/29/2011
Application #:
12964638
Filing Dt:
12/09/2010
Publication #:
US20110079899
Pub Dt:
04/07/2011
Title:
EMBEDDED INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF MANUFACTURE THEREOF
73
Patent #:
8102043
Issue Dt:
01/24/2012
Application #:
13006278
Filing Dt:
01/13/2011
Publication #:
US20110108976
Pub Dt:
05/12/2011
Title:
STACKED INTEGRATED CIRCUIT AND PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
Assignor
1
STATS CHIPPAC LTD.
Exec Dt:
03/29/2016
Assignee
1
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 53
SINGAPORE, SINGAPORE
Correspondence name and address
EDWARD J. MAYLE
1850 K STREET, N.W.
SUITE 1100
WASHINGTON, DC 20006

Search Results as of: 05/24/2024 12:06 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT