Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 032667/0279 | |
| Pages: | 6 |
| | Recorded: | 04/14/2014 | | |
Attorney Dkt #: | RA452.D1C1C1C1C1.US |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
5
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Patent #:
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Issue Dt:
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07/07/2009
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Application #:
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11768107
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Filing Dt:
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06/25/2007
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Publication #:
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Pub Dt:
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10/25/2007
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Title:
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MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
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Patent #:
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Issue Dt:
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01/03/2012
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Application #:
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12477703
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Filing Dt:
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06/03/2009
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Publication #:
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Pub Dt:
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09/24/2009
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Title:
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MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
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Patent #:
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Issue Dt:
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12/25/2012
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Application #:
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13336851
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Filing Dt:
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12/23/2011
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Publication #:
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Pub Dt:
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07/26/2012
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Title:
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INTEGRATED CIRCUIT WITH STAGGERED SIGNAL OUTPUT
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Patent #:
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Issue Dt:
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01/28/2014
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Application #:
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13720720
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Filing Dt:
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12/19/2012
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Publication #:
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Pub Dt:
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05/02/2013
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Title:
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MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
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Patent #:
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Issue Dt:
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10/20/2015
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Application #:
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14153822
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Filing Dt:
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01/13/2014
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Publication #:
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Pub Dt:
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06/19/2014
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Title:
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MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
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Assignee
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1050 ENTERPRISE WAY, SUITE 700 |
SUNNYVALE, CALIFORNIA 94089 |
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Correspondence name and address
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TARISA WAIN
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1050 ENTERPRISE WAY #700
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SUNNYVALE, CA 94089
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