Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 026001/0285 | |
| Pages: | 2 |
| | Recorded: | 03/22/2011 | | |
| Conveyance: | CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). |
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Total properties:
6
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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10481570
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Filing Dt:
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12/19/2003
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Publication #:
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Pub Dt:
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08/05/2004
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Title:
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METHOD AND CIRCUIT ARRANGEMENT FOR MEMORY ERROR PROCESSING
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Patent #:
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Issue Dt:
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06/19/2007
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Application #:
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10536302
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Filing Dt:
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05/19/2005
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Publication #:
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Pub Dt:
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01/19/2006
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Title:
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CIRCUIT ARRANGEMENT WITH NON-VOLATILE MEMORY MODULE AND METHOD FOR REGISTETING LIGHT- ATTACKS ON THE NON-VOLATILE MEMORY MODULE
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Patent #:
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Issue Dt:
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02/19/2008
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Application #:
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10538288
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Filing Dt:
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06/10/2005
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Publication #:
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Pub Dt:
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03/16/2006
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Title:
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ONE-TIME PROGRAMMABLE MEMORY DEVICES
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Patent #:
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Issue Dt:
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06/05/2007
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Application #:
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10538574
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Filing Dt:
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06/15/2005
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Publication #:
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Pub Dt:
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06/01/2006
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Title:
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TEMPERATURE COMPENSATED R-C OSCILLATOR
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Patent #:
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Issue Dt:
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04/03/2007
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Application #:
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10548340
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Filing Dt:
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09/07/2005
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Publication #:
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Pub Dt:
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08/24/2006
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Title:
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TEST FOR WEAK SRAM CELLS
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Patent #:
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Issue Dt:
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03/03/2009
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Application #:
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10559208
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Filing Dt:
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12/06/2005
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Publication #:
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Pub Dt:
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06/08/2006
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Title:
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REAL-TIME ADAPTIVE CONTROL FOR BEST IC PERFORMANCE
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Assignee
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| HIGH TECH CAMPUS 60 |
| EINDHOVEN, NETHERLANDS 5656AG |
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Correspondence name and address
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DAVID L SCHAEFFER
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1109 MCKAY DRIVE, M/S 41 SJ
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NXP SEMICONDUCTORS, IP&L DEPARTMENT
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SAN JOSE, CA 95131
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