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Patent Assignment Details

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Reel/Frame:	028176/0290			Pages:	5
		Recorded:	05/08/2012
Attorney Dkt #:	MSFT-00000US0-IBM TRANSF
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 19

Patent #:	6477654	Issue Dt:	11/05/2002	Application #:	09287159	Filing Dt:	04/06/1999
Title:	MANAGING VT FOR REDUCED POWER USING POWER SETTING COMMANDS IN THE INSTRUCTION STREAM

Patent #:	6667929	Issue Dt:	12/23/2003	Application #:	10171863	Filing Dt:	06/14/2002
Publication #:	US20030231542	Pub Dt:	12/18/2003
Title:	POWER GOVERNOR FOR DYNAMIC RAM

Patent #:	6798688	Issue Dt:	09/28/2004	Application #:	10306938	Filing Dt:	11/29/2002
Publication #:	US20040105299	Pub Dt:	06/03/2004
Title:	STORAGE ARRAY SUCH AS A SRAM WITH REDUCED POWER REQUIREMENTS

Patent #:	6798682	Issue Dt:	09/28/2004	Application #:	10307168	Filing Dt:	11/29/2002
Publication #:	US20040105300	Pub Dt:	06/03/2004
Title:	REDUCED INTEGRATED CIRCUIT CHIP LEAKAGE AND METHOD OF REDUCING LEAKAGE

Patent #:	6905560	Issue Dt:	06/14/2005	Application #:	10334464	Filing Dt:	12/31/2002
Publication #:	US20040123922	Pub Dt:	07/01/2004
Title:	RETARDING AGGLOMERATION OF NI MONOSILICIDE USING NI ALLOYS

Patent #:	7657772	Issue Dt:	02/02/2010	Application #:	10366437	Filing Dt:	02/13/2003
Publication #:	US20040159904	Pub Dt:	08/19/2004
Title:	THERMALLY AWARE INTEGRATED CIRCUIT

Patent #:	7587615	Issue Dt:	09/08/2009	Application #:	10661017	Filing Dt:	09/12/2003
Publication #:	US20050060559	Pub Dt:	03/17/2005
Title:	UTILIZING HARDWARE TRANSACTIONAL APPROACH TO EXECUTE CODE AFTER INITIALLY UTILIZING SOFTWARE LOCKING BY EMPLOYING PSEUDO-TRANSACTIONS

Patent #:	7401240	Issue Dt:	07/15/2008	Application #:	10860407	Filing Dt:	06/03/2004
Publication #:	US20050283679	Pub Dt:	12/22/2005
Title:	METHOD FOR DYNAMICALLY MANAGING POWER IN MICROPROCESSOR CHIPS ACCORDING TO PRESENT PROCESSING DEMANDS

Patent #:	7173875	Issue Dt:	02/06/2007	Application #:	10950928	Filing Dt:	09/27/2004
Publication #:	US20050078508	Pub Dt:	04/14/2005
Title:	SRAM ARRAY WITH IMPROVED CELL STABILITY

Patent #:	7295457	Issue Dt:	11/13/2007	Application #:	10950940	Filing Dt:	09/27/2004
Publication #:	US20050063232	Pub Dt:	03/24/2005
Title:	INTEGRATED CIRCUIT CHIP WITH IMPROVED ARRAY STABILITY

Patent #:	7271486	Issue Dt:	09/18/2007	Application #:	11075289	Filing Dt:	03/08/2005
Publication #:	US20050176247	Pub Dt:	08/11/2005
Title:	RETARDING AGGLOMERATION OF NI MONOSILICIDE USING NI ALLOYS

Patent #:	8028290	Issue Dt:	09/27/2011	Application #:	11468547	Filing Dt:	08/30/2006
Publication #:	US20080059769	Pub Dt:	03/06/2008
Title:	MULTIPLE-CORE PROCESSOR SUPPORTING MULTIPLE INSTRUCTION SET ARCHITECTURES

Patent #:	7945741	Issue Dt:	05/17/2011	Application #:	11775096	Filing Dt:	07/09/2007
Publication #:	US20090019209	Pub Dt:	01/15/2009
Title:	RESERVATION REQUIRED TRANSACTIONS

Patent #:	7403412	Issue Dt:	07/22/2008	Application #:	11782282	Filing Dt:	07/24/2007
Publication #:	US20080019200	Pub Dt:	01/24/2008
Title:	INTEGRATED CIRCUIT CHIP WITH IMPROVED ARRAY STABILITY

Patent #:	7647519	Issue Dt:	01/12/2010	Application #:	12131507	Filing Dt:	06/02/2008
Publication #:	US20080229128	Pub Dt:	09/18/2008
Title:	SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DYNAMICALLY MANAGING POWER IN MICROPROCESSOR CHIPS ACCORDING TO PRESENT PROCESSING DEMANDS

Patent #:	7787284	Issue Dt:	08/31/2010	Application #:	12133450	Filing Dt:	06/05/2008
Publication #:	US20080232149	Pub Dt:	09/25/2008
Title:	INTEGRATED CIRCUIT CHIP WITH IMPROVED ARRAY STABILITY

Patent #:	8102236	Issue Dt:	01/24/2012	Application #:	12968118	Filing Dt:	12/14/2010
Title:	THIN FILM INDUCTOR WITH INTEGRATED GAPS

Patent #:	8166255	Issue Dt:	04/24/2012	Application #:	13009582	Filing Dt:	01/19/2011
Publication #:	US20110113203	Pub Dt:	05/12/2011
Title:	RESERVATION REQUIRED TRANSACTIONS

Patent #:	8806182	Issue Dt:	08/12/2014	Application #:	13182181	Filing Dt:	07/13/2011
Publication #:	US20110271079	Pub Dt:	11/03/2011
Title:	MULTIPLE-CORE PROCESSOR SUPPORTING MULTIPLE INSTRUCTION SET ARCHITECTURES

Assignor

Exec Dt:

03/30/2012

Assignee

ONE MICROSOFT WAY

REDMOND, WASHINGTON 98052

Correspondence name and address
	TYLER THORP
	575 MARKET STREET, SUITE 2500
	SAN FRANCISCO, CA 94105

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