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Reel/Frame:	019111/0295			Pages:	12
		Recorded:	04/04/2007
Attorney Dkt #:	380889
Conveyance:	FIRST AMENDMENT TO PATENT SECURITY AGREEMENT

Total properties: 58

Patent #:	4396479	Issue Dt:	08/02/1983	Application #:	06355445	Filing Dt:	04/30/1982
Title:	ION ETCHING PROCESS WITH MINIMIZED REDEPOSITION

Patent #:	4477962	Issue Dt:	10/23/1984	Application #:	06397050	Filing Dt:	07/12/1982
Title:	PROCESS FOR AND STRUCTURE OF HIGH DENSITY VLSI CIRCUITS, HAVING SELF- ALIGNED GATES AND CONTACTS FOR FET DEVICES AND CONDUCTING LINES

Patent #:	4506437	Issue Dt:	03/26/1985	Application #:	06397052	Filing Dt:	07/12/1982
Title:	PROCESS FOR AND STRUCTURE OF HIGH DENSITY VLSI CIRCUITS, HAVING SELF- ALIGNED GATES AND CONTACTS FOR PET DEVICES AND CONDUCTING LINES

Patent #:	4459937	Issue Dt:	07/17/1984	Application #:	06397646	Filing Dt:	07/12/1982
Title:	HIGH RATE RESIST POLYMERIZATION APPARATUS

Patent #:	4444617	Issue Dt:	04/24/1984	Application #:	06456183	Filing Dt:	01/06/1983
Title:	REACTIVE ION ETCHING OF MOLTYBDENUM SILICIDE AND N POLYSILICON

Patent #:	4639142	Issue Dt:	01/27/1987	Application #:	06484666	Filing Dt:	04/13/1983
Title:	DIMENSION MONITORING TECHNIQUE FOR SEMICONDUCTOR FABRICATION

Patent #:	4507852	Issue Dt:	04/02/1985	Application #:	06531529	Filing Dt:	09/12/1983
Title:	METHOD FOR MAKING A RELIABLE OHMIC CONTACT BETWEEN TWO LAYERS OF INTEGRATED CIRCUIT METALLIZATIONS

Patent #:	4497685	Issue Dt:	02/05/1985	Application #:	06544914	Filing Dt:	10/24/1983
Title:	SMALL AREA HIGH VALUE RESISTOR WITH GREATLY REDUCED PARASITIC CAPACITANCE

Patent #:	4593453	Issue Dt:	06/10/1986	Application #:	06621773	Filing Dt:	06/18/1984
Title:	TWO-LEVEL TRANSISTOR STRUCTURES AND METHOD UTILIZING MINIMAL AREA THEREFOR

Patent #:	5031014	Issue Dt:	07/09/1991	Application #:	07062007	Filing Dt:	06/12/1987
Title:	LATERAL TRANSISTOR SEPARATED FROM SUBSTRATE BY INTERSECTING SLOTS FILLED WITH SUBSTRATE OXIDE FOR MINIMAL INTERFERENCE THEREFROM

Patent #:	5097316	Issue Dt:	03/17/1992	Application #:	07068383	Filing Dt:	06/11/1987
Title:	COMPLEMENTARY NPN AND PNP LATERAL TRANSISTORS SEPARATED FROM SUBSTRATE BY INTERSECTING SLOTS FILLED WITH SUBSTRATE OXIDE FOR MINIMAL INTERFERENCE THEREFROM

Patent #:	7049246	Issue Dt:	05/23/2006	Application #:	09575055	Filing Dt:	05/19/2000
Title:	METHOD FOR SELECTIVE FABRICATION OF HIGH CAPACITANCE DENSITY AREAS IN A LOW DIELECTRIC CONSTANT MATERIAL

Patent #:	6995068	Issue Dt:	02/07/2006	Application #:	09590462	Filing Dt:	06/09/2000
Title:	DOUBLE-IMPLANT HIGH PERFORMANCE VARACTOR AND METHOD FOR MANUFACTURING SAME

Patent #:	6984577	Issue Dt:	01/10/2006	Application #:	09665422	Filing Dt:	09/20/2000
Title:	DAMASCENE INTERCONNECT STRUCTURE AND FABRICATION METHOD HAVING AIR GAPS BETWEEN METAL LINES AND METAL LAYERS

Patent #:	7056822	Issue Dt:	06/06/2006	Application #:	09686323	Filing Dt:	10/09/2000
Title:	METHOD OF FABRICATING AN INTERCONNECT STRUCTURE EMPLOYING AIR GAPS BETWEEN METAL LINES AND BETWEEN METAL LAYERS

Patent #:	7173318	Issue Dt:	02/06/2007	Application #:	09754806	Filing Dt:	01/02/2001
Publication #:	US20020011646	Pub Dt:	01/31/2002
Title:	ON-CHIP INDUCTORS

Patent #:	7217613	Issue Dt:	05/15/2007	Application #:	09833953	Filing Dt:	04/11/2001
Publication #:	US20020151148	Pub Dt:	10/17/2002
Title:	LOW COST FABRICATION OF HIGH RESISTIVITY RESISTORS

Patent #:	7183627	Issue Dt:	02/27/2007	Application #:	10054438	Filing Dt:	01/22/2002
Publication #:	US20020090788	Pub Dt:	07/11/2002
Title:	INDEPENDENT CONTROL OF POLYCRYSTALLINE SILICON-GERMANIUM IN AN HBT AND RELATED STRUCTURE

Patent #:	6586307	Issue Dt:	07/01/2003	Application #:	10075701	Filing Dt:	02/14/2002
Title:	METHOD FOR CONTROLLING AN EMITTER WINDOW OPENING IN AN HBT AND RELATED STRUCTURE

Patent #:	7060557	Issue Dt:	06/13/2006	Application #:	10190297	Filing Dt:	07/05/2002
Title:	FABRICATION OF HIGH-DENSITY CAPACITORS FOR MIXED SIGNAL/RF CIRCUITS

Patent #:	6838352	Issue Dt:	01/04/2005	Application #:	10190459	Filing Dt:	07/05/2002
Title:	DAMASCENE TRENCH CAPACITOR FOR MIXED-SIGNAL/RF IC APPLICATIONS

Patent #:	6972442	Issue Dt:	12/06/2005	Application #:	10313583	Filing Dt:	12/07/2002
Title:	Efficiently fabricated bipolar transistor

Patent #:	6965132	Issue Dt:	11/15/2005	Application #:	10321877	Filing Dt:	12/17/2002
Title:	POLYCRYSTALLINE SILICON EMITTER HAVING AN ACCURATELY CONTROLLED CRITICAL DIMENSION

Patent #:	7015115	Issue Dt:	03/21/2006	Application #:	10371307	Filing Dt:	02/20/2003
Title:	METHOD FOR FORMING DEEP TRENCH ISOLATION AND RELATED STRUCTURE

Patent #:	7064073	Issue Dt:	06/20/2006	Application #:	10434961	Filing Dt:	05/09/2003
Title:	TECHNIQUE FOR REDUCING CONTAMINANTS IN FABRICATION OF SEMICONDUCTOR WAFERS

Patent #:	6979626	Issue Dt:	12/27/2005	Application #:	10442449	Filing Dt:	05/21/2003
Publication #:	US20040135179	Pub Dt:	07/15/2004
Title:	METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR HAVING INCREASED MANUFACTURABILITY AND RELATED STRUCTURE

Patent #:	7041569	Issue Dt:	05/09/2006	Application #:	10712067	Filing Dt:	11/13/2003
Title:	METHOD FOR FABRICATING A HIGH DENSITY COMPOSITE MIM CAPACITOR WITH REDUCED VOLTAGE DEPENDENCE IN SEMICONDUCTOR DIES

Patent #:	7063988	Issue Dt:	06/20/2006	Application #:	10758494	Filing Dt:	01/15/2004
Title:	CIRCUIT FOR DETECTING ARCING IN AN ETCH TOOL DURING WAFER PROCESSING

Patent #:	7154161	Issue Dt:	12/26/2006	Application #:	10826507	Filing Dt:	04/16/2004
Title:	COMPOSITE GROUND SHIELD FOR PASSIVE COMPONENTS IN A SEMICONDUCTOR DIE

Patent #:	6995449	Issue Dt:	02/07/2006	Application #:	10842943	Filing Dt:	05/10/2004
Title:	DEEP TRENCH ISOLATION REGION WITH REDUCED-SIZE CAVITIES IN OVERLYING FIELD OXIDE

Patent #:	7078786	Issue Dt:	07/18/2006	Application #:	10843190	Filing Dt:	05/10/2004
Title:	COMPOSITE SERIES RESISTOR HAVING REDUCED TEMPERATURE SENSITIVITY IN AN IC CHIP

Patent #:	7078310	Issue Dt:	07/18/2006	Application #:	10850187	Filing Dt:	05/19/2004
Title:	METHOD FOR FABRICATING A HIGH DENSITY COMPOSITE MIM CAPACITOR WITH FLEXIBLE ROUTING IN SEMICONDUCTOR DIES

Patent #:	7033898	Issue Dt:	04/25/2006	Application #:	10865153	Filing Dt:	06/09/2004
Title:	METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR HAVING RECESSED SPACERS

Patent #:	7064361	Issue Dt:	06/20/2006	Application #:	10865634	Filing Dt:	06/10/2004
Title:	NPN TRANSISTOR HAVING REDUCED EXTRINISIC BASE RESISTANCE AND IMPROVED MANUFACTURABILITY

Patent #:	7041564	Issue Dt:	05/09/2006	Application #:	10870900	Filing Dt:	06/17/2004
Title:	METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR

Patent #:	7078744	Issue Dt:	07/18/2006	Application #:	10888406	Filing Dt:	07/10/2004
Title:	TRANSISTOR EMITTER HAVING ALTERNATING UNDOPED AND DOPED LAYERS

Patent #:	7994611	Issue Dt:	08/09/2011	Application #:	10892015	Filing Dt:	07/14/2004
Title:	BIPOLAR TRANSISTOR FABRICATED IN A BICMOS PROCESS

Patent #:	7132700	Issue Dt:	11/07/2006	Application #:	10915797	Filing Dt:	08/11/2004
Title:	SIGE LAYER HAVING SMALL POLY GRAINS

Patent #:	6992338	Issue Dt:	01/31/2006	Application #:	10936927	Filing Dt:	09/09/2004
Title:	CMOS TRANSISTOR SPACERS FORMED IN A BICMOS PROCESS

Patent #:	7282418	Issue Dt:	10/16/2007	Application #:	10952256	Filing Dt:	09/28/2004
Title:	METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR WITHOUT SPACERS

Patent #:	7338848	Issue Dt:	03/04/2008	Application #:	10970645	Filing Dt:	10/20/2004
Title:	METHOD FOR OPTO-ELECTRONIC INTEGRATION ON A SOI SUBSTRATE AND RELATED STRUCTURE

Patent #:	7109125	Issue Dt:	09/19/2006	Application #:	10995762	Filing Dt:	11/22/2004
Title:	SELECTIVE FABRICATION OF HIGH CAPACITANCE DENSITY AREAS IN A LOW DIELECTRIC CONSTANT MATERIAL

Patent #:	7064415	Issue Dt:	06/20/2006	Application #:	10995769	Filing Dt:	11/22/2004
Title:	SELF-ALIGNED BIPOLAR TRANSISTOR HAVING INCREASED MANUFACTURABILITY

Patent #:	7297992	Issue Dt:	11/20/2007	Application #:	10997534	Filing Dt:	11/23/2004
Title:	METHOD AND STRUCTURE FOR INTEGRATION OF PHOSPHORUS EMITTER IN AN NPN DEVICE IN A BICMOS PROCESS

Patent #:	7268038	Issue Dt:	09/11/2007	Application #:	10997638	Filing Dt:	11/23/2004
Publication #:	US20060110889	Pub Dt:	05/25/2006
Title:	METHOD FOR FABRICATING A MIM CAPACITOR HAVING INCREASED CAPACITANCE DENSITY AND RELATED STRUCTURE

Patent #:	7235861	Issue Dt:	06/26/2007	Application #:	11003572	Filing Dt:	12/02/2004
Title:	NPN TRANSISTOR HAVING REDUCED EXTRINSIC BASE RESISTANCE AND IMPROVED MANUFACTURABILITY

Patent #:	7339254	Issue Dt:	03/04/2008	Application #:	11018164	Filing Dt:	12/20/2004
Title:	SOI SUBSTRATE FOR INTEGRATION OF OPTO-ELECTRONICS WITH SIGE BICMOS

Patent #:	7541231	Issue Dt:	06/02/2009	Application #:	11084391	Filing Dt:	03/17/2005
Title:	INTEGRATION OF SIGE NPN AND VERTICAL PNP DEVICES ON A SUBSTRATE

Patent #:	7335547	Issue Dt:	02/26/2008	Application #:	11086168	Filing Dt:	03/21/2005
Title:	METHOD FOR EFFECTIVE BICMOS PROCESS INTEGRATION

Patent #:	7709949	Issue Dt:	05/04/2010	Application #:	11112194	Filing Dt:	04/22/2005
Publication #:	US20090243114	Pub Dt:	10/01/2009
Title:	DENSELY PACKED METAL SEGMENTS PATTERNED IN A SEMICONDUCTOR DIE

Patent #:	7220639	Issue Dt:	05/22/2007	Application #:	11121360	Filing Dt:	05/03/2005
Publication #:	US20060252218	Pub Dt:	11/09/2006
Title:	METHOD FOR FABRICATING A MIM CAPACITOR HIGH-K DIELECTRIC FOR INCREASED CAPACITANCE DENSITY AND RELATED STRUCTURE

Patent #:	7291898	Issue Dt:	11/06/2007	Application #:	11146537	Filing Dt:	06/06/2005
Title:	SELECTIVE AND NON-SELECTIVE EPITAXY FOR BASE INTEGRATION IN A BICMOS PROCESS AND RELATED STRUCTURE

Patent #:	7291536	Issue Dt:	11/06/2007	Application #:	11175720	Filing Dt:	07/06/2005
Title:	FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR HAVING INCREASED MANUFACTURABILITY

Patent #:	9136157	Issue Dt:	09/15/2015	Application #:	11198425	Filing Dt:	08/05/2005
Title:	Deep N wells in triple well structures

Patent #:	7498620	Issue Dt:	03/03/2009	Application #:	11525457	Filing Dt:	09/21/2006
Title:	INTEGRATION OF PHOSPHORUS EMITTER IN AN NPN DEVICE IN A BICMOS PROCESS

Patent #:	8212351	Issue Dt:	07/03/2012	Application #:	11542088	Filing Dt:	10/02/2006
Title:	STRUCTURE FOR ENCAPSULATING MICROELECTRONIC DEVICES

Patent #:	7704874	Issue Dt:	04/27/2010	Application #:	11641500	Filing Dt:	12/18/2006
Title:	METHOD FOR FABRICATING A FRONTSIDE THROUGH-WAFER VIA IN A PROCESSED WAFER AND RELATED STRUCTURE

Patent #:	7589009	Issue Dt:	09/15/2009	Application #:	11641925	Filing Dt:	12/18/2006
Title:	METHOD FOR FABRICATING A TOP CONDUCTIVE LAYER IN A SEMICONDUCTOR DIE AND RELATED STRUCTURE

Assignor

NEWPORT FAB, LLC

Exec Dt:

02/28/2007

Assignee

WACHOVIA CAPITAL FINANCE CORPORATION (WESTERN)

251 S. LAKE AVE.

SUITE 900

PASADENA, CALIFORNIA 91101

Correspondence name and address
	Y
	1023 FIFTEENTH STREET, NW, STE 401
	ATTN: OLEH HERELIUK
	WASHINGTON, DC 20005

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