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Patent Assignment Details
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Reel/Frame:033004/0302   Pages: 3
Recorded: 05/22/2014
Attorney Dkt #:RA463.C1C1C1.US +2
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 3
1
Patent #:
Issue Dt:
08/02/2011
Application #:
12361513
Filing Dt:
01/28/2009
Publication #:
Pub Dt:
05/21/2009
Title:
PROCESS FOR MAKING A SEMICONDUCTOR SYSTEM HAVING DEVICES THAT HAVE CONTACTS ON TOP AND BOTTOM SURFACES OF EACH DEVICE
2
Patent #:
Issue Dt:
06/10/2014
Application #:
13166996
Filing Dt:
06/23/2011
Publication #:
Pub Dt:
10/13/2011
Title:
PROCESS FOR MAKING A SEMICONDUCTOR SYSTEM
3
Patent #:
Issue Dt:
12/19/2017
Application #:
14272295
Filing Dt:
05/07/2014
Publication #:
Pub Dt:
11/06/2014
Title:
METHOD OF MAKING A STACKED DEVICE ASSEMBLY
Assignors
1
Exec Dt:
06/01/2006
2
Exec Dt:
06/01/2006
3
Exec Dt:
06/01/2006
Assignee
1
1050 ENTERPRISE WAY, SUITE 700
SUNNYVALE, CALIFORNIA 94089
Correspondence name and address
TARISA WAIN
1050 ENTERPRISE WAY #700
SUNNYVALE, CA 94089

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