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Total properties:
44
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Patent #:
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Issue Dt:
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06/16/1998
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Application #:
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08153560
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Filing Dt:
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11/17/1993
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Title:
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INTELLIGENT HARDWARE FOR AUTOMATICALLY READING AND WRITING MULTIPLE SECTORS OF DATA BETWEEN A COMPUTER BUS AND A DISK DRIVE
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Patent #:
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Issue Dt:
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10/20/1998
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Application #:
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08363448
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Filing Dt:
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12/22/1994
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Title:
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DUAL FUNCTION DISK DRIVE INTEGRATED CIRCUIT FOR MASTER MODE AND SLAVE MODE OPERATIONS
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Patent #:
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Issue Dt:
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09/22/1998
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Application #:
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08417754
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Filing Dt:
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04/06/1995
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Title:
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PROCESS FOR BALANCING THE LOUDNESS OF DIGITALLY SAMPLED AUDIO WAVEFORMS
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Patent #:
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Issue Dt:
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06/09/1998
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Application #:
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08450456
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Filing Dt:
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05/25/1995
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Title:
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A DIAGNOSTIC SYSTEM INCLUDING A LSI OR VLSI INTEGRATED CIRCUIT WITH A DIAGNOSTIC DATA PORT
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Patent #:
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Issue Dt:
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12/01/1998
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Application #:
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08463333
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Filing Dt:
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06/05/1995
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Title:
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SYSTEM FOR SUPPLYING INITIATOR IDENTIFICATION INFORMATION TO SCSI BUS IN A RESELECTION PHASE OF AN INITIATOR BEFORE COMPLETION OF AN AUTOTRANSFER COMMAND
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Patent #:
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Issue Dt:
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07/14/1998
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Application #:
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08465075
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Filing Dt:
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06/05/1995
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Title:
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SYSTEM FOR STORING INITIATOR, QUEUE TAG AND LOGICAL BLOCK INFORMATION, DISCONNECTING FROM TARGET IF COMMAND IS NOT AUTO TRANSFER, RECONNECTING AND PERFORMING DATA TRANSFER
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Patent #:
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Issue Dt:
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10/20/1998
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Application #:
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08482529
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Filing Dt:
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06/07/1995
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Title:
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INTEGRATED CIRCUIT WITH A SERIAL PORT HAVING ONLY ONE PIN
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Patent #:
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Issue Dt:
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11/17/1998
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Application #:
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08486096
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Filing Dt:
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06/07/1995
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Title:
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A METHOD OF OPERATION OF A HOST ADAPTER INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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09/22/1998
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Application #:
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08522037
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Filing Dt:
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09/01/1995
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Title:
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PROGRAMMABLE DATA TRANSFER WITHOUT SECTOR PULSES IN A HEADERLESS DISK DRIVE ARCHITECTURE
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Patent #:
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Issue Dt:
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09/01/1998
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Application #:
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08522639
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Filing Dt:
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09/01/1995
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Title:
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HARDWARE ALIGNMENT IN A HEADERLESS DISK DRIVE ARCHITECTURE
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Patent #:
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Issue Dt:
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09/22/1998
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Application #:
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08522687
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Filing Dt:
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09/01/1995
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Title:
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LOGICAL AND PHYSICAL ZONES FOR MANAGEMENT OF DEFECTS IN A HEADERLESS DISK DRIVE ARCHITECTURE
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Patent #:
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Issue Dt:
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06/23/1998
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Application #:
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08542198
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Filing Dt:
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10/12/1995
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Title:
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SYSTEM AND METHOD FOR SOLVING QUADRATIC EQUATION IN GALOIS FIELDS
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Patent #:
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Issue Dt:
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09/22/1998
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Application #:
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08542262
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Filing Dt:
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10/12/1995
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Title:
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ARITHMETIC LOGIC UNIT AND METHOD FOR NUMERICAL COMPUTATIONS IN GALOIS FIELDS
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Patent #:
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Issue Dt:
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07/28/1998
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Application #:
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08542277
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Filing Dt:
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10/12/1995
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Title:
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SYSTEM AND METHOD FOR ENCODING AND DECODING DATA USING NUMERICAL COMPUTATIONS IN GALOIS FIELDS
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Patent #:
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Issue Dt:
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07/21/1998
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Application #:
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08571534
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Filing Dt:
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12/13/1995
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Title:
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APPARATUS FOR A VARIABLE AREA NOZZLE
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Patent #:
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Issue Dt:
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07/06/1999
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Application #:
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08592800
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Filing Dt:
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01/26/1996
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Title:
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A SERIAL PORT HAVING ONLY A SINGLE TERMINAL FOR INFORMATION TRANSFER TO AND FROM AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/20/1999
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Application #:
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08603531
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Filing Dt:
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02/21/1996
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Title:
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REMOTE PROCEDURAL CALL COMPONENT MANAGEMENT METHOD FOR A HETEROGENEOUS COMPUTER NETWORK
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Patent #:
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Issue Dt:
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12/15/1998
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Application #:
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08615476
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Filing Dt:
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03/15/1996
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Title:
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METHOD FOR SPECIFYING CONCURRENT EXECUTION OF A STRING OF I/O COMMAND BLOCKS IN A CHAIN STRUCTURE
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Patent #:
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Issue Dt:
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03/09/1999
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Application #:
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08615477
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Filing Dt:
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03/15/1996
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Title:
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HOST ADAPTER SYSTEM INCLUDING AN INTEGRATED PCI BUFFER CONTROLLER AND XOR FUNCTION CIRCUIT
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Patent #:
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Issue Dt:
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02/02/1999
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Application #:
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08615478
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Filing Dt:
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03/15/1996
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Title:
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HARDWARE METHOD FOR VERIFYING THAT AN AREA OF MEMORY HAS ONLY ZERO VALUES
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|
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Patent #:
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|
Issue Dt:
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04/06/1999
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Application #:
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08615479
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Filing Dt:
|
03/15/1996
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Title:
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METHOD FOR CONCURRENTLY EXECUTING A CONFIGURED STRING OF CONCURRENT I/O COMMAND BLOCKS WITHIN A CHAIN CONCURRENTLY TO PERFORM A RAID 5 I/O OPERATION
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Patent #:
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Issue Dt:
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06/16/1998
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Application #:
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08616817
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Filing Dt:
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03/15/1996
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Title:
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CHAIN MANAGER FOR USE IN EXECUTING A CHAIN OF I/O COMMAND BLOCKS
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|
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Patent #:
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Issue Dt:
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08/18/1998
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Application #:
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08616836
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Filing Dt:
|
03/15/1996
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Title:
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METHOD FOR SPECIFYING EXECUTION OF ONLY ONE OF A PAIR OF I/O COMMAND BLOCKS IN A CHAIN STRUCTURE
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Patent #:
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Issue Dt:
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05/26/1998
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Application #:
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08616838
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Filing Dt:
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03/15/1996
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Title:
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METHOD FOR ENHANCING PERFORMANCE OF A RAID 1 READ OPERATION USING A PAIR OF I/O COMMAND BLOCKS IN A CHAIN STRUCTURE
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|
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Patent #:
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Issue Dt:
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09/22/1998
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Application #:
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08616846
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Filing Dt:
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03/15/1996
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Title:
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I/O COMMAND BLOCK CHAIN STRUCTURE IN A MEMORY
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Patent #:
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Issue Dt:
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07/13/1999
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Application #:
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08617990
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Filing Dt:
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03/15/1996
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|
Title:
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METHOD FOR SEQUENCING EXECUTION OF I/O COMMAND BLOCKS IN A CHAIN STRUCTURE BY SETTING HOLD-OFF FLAGS AND CONFIGURING A COUNTER IN EACH I/O COMMAND BLOCK
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Patent #:
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Issue Dt:
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11/23/1999
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Application #:
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08617991
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Filing Dt:
|
03/15/1996
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Title:
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A METHOD OF ENABLING AND DISABLING A DATA FUNCTION IN AN INTEGRATED CIRCUIT
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|
|
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Patent #:
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|
Issue Dt:
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08/04/1998
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Application #:
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08617994
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Filing Dt:
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03/15/1996
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Title:
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DIGITAL DELAY CIRCUIT AND METHOD
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|
|
|
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Patent #:
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|
Issue Dt:
|
02/16/1999
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Application #:
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08687009
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Filing Dt:
|
07/16/1996
|
|
Title:
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GLOBAL PARITY SYMBOL FOR INTERLEAVED REED-SOLOMON CODED DATA
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|
|
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Patent #:
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|
Issue Dt:
|
10/13/1998
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Application #:
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08709501
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Filing Dt:
|
09/06/1996
|
|
Title:
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METHOD FOR DETERMINING WHETHER BI-DIRECTIONAL OR UNIDIRECTIONAL DATA LINE CIRCUITS ARE USED
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|
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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08797802
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Filing Dt:
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02/07/1997
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|
Title:
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ERROR GENERATION CIRCUIT FOR TESTING A DIGITAL BUS
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|
|
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Patent #:
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|
Issue Dt:
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09/28/1999
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Application #:
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08808099
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Filing Dt:
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02/28/1997
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Title:
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FORMAT CALCULATOR FOR HEADERLESS HARD DISK WITH EMBEDDED SERVO WEDGES
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Patent #:
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Issue Dt:
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08/31/1999
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Application #:
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08808526
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Filing Dt:
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02/28/1997
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Title:
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INTERLEAVED BURST XOR USING A SINGLE MEMORY POINTER
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|
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Patent #:
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Issue Dt:
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12/21/1999
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Application #:
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08815645
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Filing Dt:
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03/13/1997
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Title:
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METHOD OF MANAGING HARDWARE CONTROL BLOCKS UTILIZING ENDLESS QUEUE MAINTAINED TO NEVER BE EMPTY AND CONTAINING TAIL POINTER ONLY ACCESSIBLE BY PROCESS EXECUTING ON SYSTEM PROCESSOR
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Patent #:
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Issue Dt:
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08/17/1999
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Application #:
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08816980
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Filing Dt:
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03/13/1997
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Title:
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IMPROVED HARDWARE COMMAND BLOCK DELIVERY QUEUE FOR HOST ADAPTERS AND OTHER DEVICES WITH ONBOARD PROCESSORS
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|
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Patent #:
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Issue Dt:
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08/17/1999
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Application #:
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08823779
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Filing Dt:
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03/24/1997
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Title:
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DATA SECTOR MARK GENERATION FOR A HEADERLESS DISK DRIVE ARCHITECTURE
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|
|
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Patent #:
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Issue Dt:
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01/04/2000
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Application #:
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08862143
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Filing Dt:
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05/22/1997
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Title:
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IMPROVED HARDWARE CONTROL BLOCK DELIVERY QUEUES FOR HOST ADAPTERS AND OTHER DEVICES WITH ONBOARD PROCESSORS
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|
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Patent #:
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Issue Dt:
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09/28/1999
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Application #:
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08869665
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Filing Dt:
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06/05/1997
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Title:
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HOST ADAPTER INTEGRATED CIRCUIT HAVING AUTOACCESS PAUSE
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|
|
|
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Patent #:
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|
Issue Dt:
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11/02/1999
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Application #:
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08876539
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Filing Dt:
|
06/09/1997
|
|
Title:
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STATUS INDICATOR FOR A HOST ADAPTER
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|
|
|
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Patent #:
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|
Issue Dt:
|
12/07/1999
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Application #:
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08877115
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Filing Dt:
|
06/17/1997
|
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Title:
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SYSTEM FOR ALIGNING CONTROL WORDS FOR IDENTIFYING BOUNDARIES OF HEADERLESS DATA SECTORS USING AUTOMATIC INCREMENTING AND DISCARDING OF DATA FRAME NUMBERS
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|
|
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Patent #:
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|
Issue Dt:
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05/21/2002
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Application #:
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08938828
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Filing Dt:
|
09/29/1997
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Title:
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APPARATUS AND METHOD FOR COMMUNICATION BETWEEN INTEGRATED CIRCUITS CONNECTED TO EACH OTHER BY A SINGLE LINE
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|
|
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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08942373
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Filing Dt:
|
10/02/1997
|
|
Title:
|
INTEGRATED PCI BUFFER CONTROLLER AND XOR FUNCTION CIRCUIT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/1999
|
Application #:
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08956224
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Filing Dt:
|
10/21/1997
|
|
Title:
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METHOD AND APPARATUS FOR AUTOMATICALLY LOADING CONFIGURATION DATA ON RESET INTO A HOST ADAPTER INTEGRATED CIRCUIT
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|
|
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Patent #:
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|
Issue Dt:
|
08/08/2000
|
Application #:
|
09063635
|
Filing Dt:
|
04/20/1998
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|
Title:
|
ARITHMETIC LOGIC UNIT AND METHOD FOR NUMERICAL COMPUTATIONS IN GALOIS FIELDS
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