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Reel/Frame:037096/0315   Pages: 15
Recorded: 11/20/2015
Attorney Dkt #:70341.00400
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 42
1
Patent #:
7575956
Issue Dt:
08/18/2009
Application #:
10721916
Filing Dt:
11/24/2003
Publication #:
US20050112796
Pub Dt:
05/26/2005
Title:
FABRICATION METHOD FOR SEMICONDUCTOR PACKAGE HEAT SPREADERS
2
Patent #:
7358115
Issue Dt:
04/15/2008
Application #:
11626232
Filing Dt:
01/23/2007
Publication #:
US20070114648
Pub Dt:
05/24/2007
Title:
METHOD OF FABRICATING A SEMICONDUCTOR ASSEMBLY INCLUDING CHIP SCALE PACKAGE AND SECOND SUBSTRATE WITH EXPOSED SUBSTRATE SURFACES ON UPPER AND LOWER SIDES
3
Patent #:
7358115
Issue Dt:
04/15/2008
Application #:
11626232
Filing Dt:
01/23/2007
Publication #:
US20070114648
Pub Dt:
05/24/2007
Title:
METHOD OF FABRICATING A SEMICONDUCTOR ASSEMBLY INCLUDING CHIP SCALE PACKAGE AND SECOND SUBSTRATE WITH EXPOSED SUBSTRATE SURFACES ON UPPER AND LOWER SIDES
4
Patent #:
9084377
Issue Dt:
07/14/2015
Application #:
11694913
Filing Dt:
03/30/2007
Publication #:
US20080235941
Pub Dt:
10/02/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING FEATURES FOR CLEARANCE
5
Patent #:
9202776
Issue Dt:
12/01/2015
Application #:
11754603
Filing Dt:
05/29/2007
Publication #:
US20070278643
Pub Dt:
12/06/2007
Title:
STACKABLE MULTI-CHIP PACKAGE SYSTEM
6
Patent #:
9059074
Issue Dt:
06/16/2015
Application #:
12055526
Filing Dt:
03/26/2008
Publication #:
US20090243082
Pub Dt:
10/01/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PLANAR INTERCONNECT
7
Patent #:
9202777
Issue Dt:
12/01/2015
Application #:
12131037
Filing Dt:
05/30/2008
Publication #:
US20090294935
Pub Dt:
12/03/2009
Title:
SEMICONDUCTOR PACKAGE SYSTEM WITH CUT MULTIPLE LEAD PADS
8
Patent #:
9177898
Issue Dt:
11/03/2015
Application #:
12146192
Filing Dt:
06/25/2008
Publication #:
US20090321913
Pub Dt:
12/31/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LOCKING TERMINAL
9
Patent #:
9076737
Issue Dt:
07/07/2015
Application #:
12487925
Filing Dt:
06/19/2009
Publication #:
US20100320589
Pub Dt:
12/23/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMPS AND METHOD OF MANUFACTURE THEREOF
10
Patent #:
9093391
Issue Dt:
07/28/2015
Application #:
12561897
Filing Dt:
09/17/2009
Publication #:
US20110062602
Pub Dt:
03/17/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FAN-IN PACKAGE AND METHOD OF MANUFACTURE THEREOF
11
Patent #:
7829382
Issue Dt:
11/09/2010
Application #:
12699787
Filing Dt:
02/03/2010
Publication #:
US20100136744
Pub Dt:
06/03/2010
Title:
METHOD FOR MAKING SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING DIE AND INVERTED LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
12
Patent #:
8035204
Issue Dt:
10/11/2011
Application #:
12709073
Filing Dt:
02/19/2010
Publication #:
US20100140766
Pub Dt:
06/10/2010
Title:
LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR
13
Patent #:
9048197
Issue Dt:
06/02/2015
Application #:
12709425
Filing Dt:
02/19/2010
Publication #:
US20100148355
Pub Dt:
06/17/2010
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING WAFER LEVEL CHIP SCALE PACKAGING
14
Patent #:
9093364
Issue Dt:
07/28/2015
Application #:
13166438
Filing Dt:
06/22/2011
Publication #:
US20120326281
Pub Dt:
12/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXPOSED VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
15
Patent #:
9059151
Issue Dt:
06/16/2015
Application #:
13187505
Filing Dt:
07/20/2011
Publication #:
US20120018865
Pub Dt:
01/26/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISLAND TERMINALS AND EMBEDDED PADDLE AND METHOD OF MANUFACTURE THEREOF
16
Patent #:
9054098
Issue Dt:
06/09/2015
Application #:
13221894
Filing Dt:
08/30/2011
Publication #:
US20130049208
Pub Dt:
02/28/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH REDISTRIBUTION LAYER AND METHOD OF MANUFACTURE THEREOF
17
Patent #:
9059108
Issue Dt:
06/16/2015
Application #:
13407554
Filing Dt:
02/28/2012
Publication #:
US20130221543
Pub Dt:
08/29/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS
18
Patent #:
9142481
Issue Dt:
09/22/2015
Application #:
13489282
Filing Dt:
06/05/2012
Publication #:
US20130322023
Pub Dt:
12/05/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEATSINK CAP AND METHOD OF MANUFACTURE THEREOF
19
Patent #:
9184122
Issue Dt:
11/10/2015
Application #:
13489850
Filing Dt:
06/06/2012
Publication #:
US20130328216
Pub Dt:
12/12/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND METHOD OF MANUFACTURE THEREOF
20
Patent #:
9059011
Issue Dt:
06/16/2015
Application #:
13589018
Filing Dt:
08/17/2012
Publication #:
US20120306078
Pub Dt:
12/06/2012
Title:
EXPOSED INTERCONNECT FOR A PACKAGE ON PACKAGE SYSTEM
21
Patent #:
9324584
Issue Dt:
04/26/2016
Application #:
13714865
Filing Dt:
12/14/2012
Publication #:
US20140167236
Pub Dt:
06/19/2014
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSFERABLE TRACE LEAD FRAME
22
Patent #:
9054084
Issue Dt:
06/09/2015
Application #:
13716479
Filing Dt:
12/17/2012
Publication #:
US20130127061
Pub Dt:
05/23/2013
Title:
INTEGRATED CIRCUIT HAVING STAGGERED BOND PADS AND I/O CELLS
23
Patent #:
9053953
Issue Dt:
06/09/2015
Application #:
13842305
Filing Dt:
03/15/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF
24
Patent #:
9059157
Issue Dt:
06/16/2015
Application #:
13842582
Filing Dt:
03/15/2013
Publication #:
US20130320525
Pub Dt:
12/05/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
25
Patent #:
9123733
Issue Dt:
09/01/2015
Application #:
13844160
Filing Dt:
03/15/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE UNDERFILL AND METHOD OF MANUFACTURE THEREOF
26
Patent #:
9123733
Issue Dt:
09/01/2015
Application #:
13844160
Filing Dt:
03/15/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE UNDERFILL AND METHOD OF MANUFACTURE THEREOF
27
Patent #:
9123712
Issue Dt:
09/01/2015
Application #:
13949432
Filing Dt:
07/24/2013
Title:
LEADFRAME SYSTEM WITH WARP CONTROL MECHANISM AND METHOD OF MANUFACTURE THEREOF
28
Patent #:
9123712
Issue Dt:
09/01/2015
Application #:
13949432
Filing Dt:
07/24/2013
Title:
LEADFRAME SYSTEM WITH WARP CONTROL MECHANISM AND METHOD OF MANUFACTURE THEREOF
29
Patent #:
9082887
Issue Dt:
07/14/2015
Application #:
13966259
Filing Dt:
08/13/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOF
30
Patent #:
9076802
Issue Dt:
07/07/2015
Application #:
14037320
Filing Dt:
09/25/2013
Title:
DUAL-SIDED FILM-ASSIST MOLDING PROCESS
31
Patent #:
9048228
Issue Dt:
06/02/2015
Application #:
14037838
Filing Dt:
09/26/2013
Publication #:
US20150084172
Pub Dt:
03/26/2015
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SIDE SOLDERABLE LEADS AND METHOD OF MANUFACTURE THEREOF
32
Patent #:
9076724
Issue Dt:
07/07/2015
Application #:
14038275
Filing Dt:
09/26/2013
Title:
INTEGRATED CIRCUIT SYSTEM WITH DEBONDING ADHESIVE AND METHOD OF MANUFACTURE THEREOF
33
Patent #:
9184139
Issue Dt:
11/10/2015
Application #:
14109313
Filing Dt:
12/17/2013
Publication #:
US20150171024
Pub Dt:
06/18/2015
Title:
Semiconductor Device and Method of Reducing Warpage Using a Silicon to Encapsulant Ratio
34
Patent #:
9728415
Issue Dt:
08/08/2017
Application #:
14134907
Filing Dt:
12/19/2013
Publication #:
US20150179544
Pub Dt:
06/25/2015
Title:
SEMICONDUCTOR DEVICE AND METHOD OF WAFER THINNING INVOLVING EDGE TRIMMING AND CMP
35
Patent #:
9768038
Issue Dt:
09/19/2017
Application #:
14139312
Filing Dt:
12/23/2013
Publication #:
US20150179481
Pub Dt:
06/25/2015
Title:
Semiconductor Device and Method of Making Embedded Wafer Level Chip Scale Packages
36
Patent #:
9721922
Issue Dt:
08/01/2017
Application #:
14139614
Filing Dt:
12/23/2013
Publication #:
US20150179570
Pub Dt:
06/25/2015
Title:
Semiconductor Device and Method of Forming Fine Pitch RDL Over Semiconductor Die in Fan-Out Package
37
Patent #:
9142530
Issue Dt:
09/22/2015
Application #:
14214765
Filing Dt:
03/15/2014
Publication #:
US20140284791
Pub Dt:
09/25/2014
Title:
CORELESS INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
38
Patent #:
9472533
Issue Dt:
10/18/2016
Application #:
14548064
Filing Dt:
11/19/2014
Publication #:
US20150140736
Pub Dt:
05/21/2015
Title:
Semiconductor Device and Method of Forming Wire Bondable Fan-Out EWLB Package
39
Patent #:
9171795
Issue Dt:
10/27/2015
Application #:
14556992
Filing Dt:
12/01/2014
Publication #:
US20150171002
Pub Dt:
06/18/2015
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED COMPONENT AND METHOD OF MANUFACTURE THEREOF
40
Patent #:
9508621
Issue Dt:
11/29/2016
Application #:
14564427
Filing Dt:
12/09/2014
Publication #:
US20150145126
Pub Dt:
05/28/2015
Title:
Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP
41
Patent #:
9548240
Issue Dt:
01/17/2017
Application #:
14616942
Filing Dt:
02/09/2015
Publication #:
US20150155248
Pub Dt:
06/04/2015
Title:
Semiconductor Device and Method of Forming Repassivation Layer for Robust Low Cost Fan-Out Semiconductor Package
42
Patent #:
9818734
Issue Dt:
11/14/2017
Application #:
14624136
Filing Dt:
02/17/2015
Publication #:
US20150179616
Pub Dt:
06/25/2015
Title:
Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate
Assignors
1
STATS CHIPPAC, INC.
Exec Dt:
10/01/2015
2
STATS CHIPPAC LTD.
Exec Dt:
10/01/2015
Assignee
1
CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
39TH FLOOR, CITIBANK TOWER, CITIBANK PLAZA, 3 GARDEN ROAD
CENTRAL, HONG KONG
Correspondence name and address
MILBANK, TWEED, HADLEY & MCCLOY, LLP
28 LIBERTY STREET
C/O LAWRENCE KASS
NEW YORK, NY 10005

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