skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:024380/0329   Pages: 14
Recorded: 05/13/2010
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 83
1
Patent #:
6069497
Issue Dt:
05/30/2000
Application #:
09019244
Filing Dt:
02/05/1998
Title:
METHOD AND APPARATUS FOR A N-NARY LOGIC CIRCUIT USING 1 OF N SIGNALS
2
Patent #:
6911846
Issue Dt:
06/28/2005
Application #:
09019278
Filing Dt:
02/05/1998
Title:
METHOD AND APPARATUS FOR A 1 OF N SIGNAL
3
Patent #:
6066965
Issue Dt:
05/23/2000
Application #:
09019355
Filing Dt:
02/05/1998
Title:
METHOD AND APPARATUS FOR AN N-NARY LOGIC CIRCUIT USING 1 OF 4 SIGNALS
4
Patent #:
6202194
Issue Dt:
03/13/2001
Application #:
09073478
Filing Dt:
05/06/1998
Title:
METHOD AND APPARATUS FOR ROUTING 1 OF N SIGNALS
5
Patent #:
6211456
Issue Dt:
04/03/2001
Application #:
09073479
Filing Dt:
05/06/1998
Title:
METHOD AND APPARATUS FOR ROUTING 1 OF 4 SIGNALS
6
Patent #:
6173299
Issue Dt:
01/09/2001
Application #:
09120771
Filing Dt:
07/22/1998
Title:
A METHOD AND APPARATUS FOR SELECTING AN INTERMEDIATE RESULT FOR PARALLEL NORMALIZATION AND ROUNDING TECHNIQUE FOR FLOATING POINT ARITHMETIC OPERATIONS
7
Patent #:
6185593
Issue Dt:
02/06/2001
Application #:
09120775
Filing Dt:
07/22/1998
Title:
METHOD AND APPARATUS FOR PARALLEL NORMALIZATION AND ROUNDING TECHNIQUE FOR FLOATING POINT ARITHMETIC OPERATIONS
8
Patent #:
6151615
Issue Dt:
11/21/2000
Application #:
09120776
Filing Dt:
07/22/1998
Title:
METHOD AND APPARATUS FOR FORMATTING AN INTERMEDIATE RESULT FOR PARALLEL NORMALIZATION AND ROUNDING TECHNIQUE FOR FLOATING POINT ARITHMETIC OPERATIONS
9
Patent #:
6175847
Issue Dt:
01/16/2001
Application #:
09120814
Filing Dt:
07/22/1998
Title:
SHIFTING FOR PARALLEL NORMALIZATION AND ROUNDING TECHNIQUE FOR FLOATING POINT ARITHMETIC OPERATIONS
10
Patent #:
6209076
Issue Dt:
03/27/2001
Application #:
09122504
Filing Dt:
07/24/1998
Title:
METHOD AND APPARATUS FOR TW0-STAGE ADDRESS GENERATION
11
Patent #:
6404233
Issue Dt:
06/11/2002
Application #:
09123742
Filing Dt:
07/28/1998
Title:
METHOD AND APPARATUS FOR LOGIC CIRCUIT TRANSITION DETECTION
12
Patent #:
6088830
Issue Dt:
07/11/2000
Application #:
09124207
Filing Dt:
07/28/1998
Title:
METHOD AND APPARATUS FOR LOGIC CIRCUIT SPEED DETECTION
13
Patent #:
6069836
Issue Dt:
05/30/2000
Application #:
09150162
Filing Dt:
09/09/1998
Title:
METHOD AND APPARATUS FOR A RAM CIRCUIT HAVING N-NARY WORD LINE GENERATION
14
Patent #:
6046931
Issue Dt:
04/04/2000
Application #:
09150258
Filing Dt:
09/09/1998
Title:
METHOD AND APPARATUS FOR A RAM CIRCUIT HAVING N-NARY OUTPUT INTERFACE
15
Patent #:
6118716
Issue Dt:
09/12/2000
Application #:
09150389
Filing Dt:
09/09/1998
Title:
METHOD AND APPARATUS FOR AN ADDRESS TRIGGERED RAM CIRCUIT
16
Patent #:
6223199
Issue Dt:
04/24/2001
Application #:
09150575
Filing Dt:
09/10/1998
Title:
METHOD AND APPARATUS FOR AN N-NARY HPG GATE
17
Patent #:
6219686
Issue Dt:
04/17/2001
Application #:
09150717
Filing Dt:
09/10/1998
Title:
METHOD AND APPARATUS FOR AN N-NARY SUM/HPG ADDER/SUBTRACTOR GATE
18
Patent #:
6219687
Issue Dt:
04/17/2001
Application #:
09150720
Filing Dt:
09/10/1998
Title:
METHOD AND APPARATUS FOR AN N-NARY SUM/HPG GATE
19
Patent #:
6216146
Issue Dt:
04/10/2001
Application #:
09150829
Filing Dt:
09/10/1998
Title:
METHOD AND APPARATUS FOR AN N-NARY ADDER GATE
20
Patent #:
6118304
Issue Dt:
09/12/2000
Application #:
09179330
Filing Dt:
10/27/1998
Title:
METHOD AND APPARATUS FOR LOGIC SYNCHRONIZATION
21
Patent #:
6233707
Issue Dt:
05/15/2001
Application #:
09179626
Filing Dt:
10/27/1998
Title:
METHOD AND APPARATUS THAT ALLOWS THE LOGIC STATE OF A LOGIC GATE TO BE TESTED WHEN STOPPING OR STARTING THE LOGIC GATE'S CLOCK
22
Patent #:
6288589
Issue Dt:
09/11/2001
Application #:
09179745
Filing Dt:
10/27/1998
Title:
METHOD AND APPARATUS FOR GENERATING CLOCK SIGNALS
23
Patent #:
6275838
Issue Dt:
08/14/2001
Application #:
09181405
Filing Dt:
10/28/1998
Title:
METHOD AND APPARATUS FOR AN ENHANCED FLOATING POINT UNIT WITH GRAPHICS AND INTEGER CAPABILITIES
24
Patent #:
6460134
Issue Dt:
10/01/2002
Application #:
09181406
Filing Dt:
10/28/1998
Title:
METHOD AND APPARATUS FOR A LATE PIPELINE ENHANCED FLOATING POINT UNIT
25
Patent #:
6275841
Issue Dt:
08/14/2001
Application #:
09186843
Filing Dt:
11/05/1998
Title:
1 OF 4 MULTIPLIER
26
Patent #:
6272653
Issue Dt:
08/07/2001
Application #:
09191813
Filing Dt:
11/13/1998
Title:
METHOD AND APPARATUS FOR BUILT-IN SELF-TEST OF LOGIC CIRCUITRY
27
Patent #:
6301597
Issue Dt:
10/09/2001
Application #:
09195024
Filing Dt:
11/18/1998
Title:
METHOD AND APPARATUS FOR SATURATION IN AN N-NARY ADDER/SUBTRACTOR
28
Patent #:
6272514
Issue Dt:
08/07/2001
Application #:
09195751
Filing Dt:
11/18/1998
Title:
METHOD AND APPARATUS FOR INTERRUPTION OF CARRY PROPAGATION ON PARTITION BOUNDARIES
29
Patent #:
6301600
Issue Dt:
10/09/2001
Application #:
09195752
Filing Dt:
11/18/1998
Title:
METHOD AND APPARATUS FOR DYNAMIC PARTITIONABLE SATURATING ADDER/SUBTRACTOR
30
Patent #:
6334183
Issue Dt:
12/25/2001
Application #:
09195757
Filing Dt:
11/18/1998
Title:
METHOD AND APPARATUS FOR HANDLING PARTIAL REGISTER ACCESSES
31
Patent #:
6370632
Issue Dt:
04/09/2002
Application #:
09195758
Filing Dt:
11/18/1998
Title:
METHOD AND APPARATUS THAT ENFORCES A REGIONAL MEMORY MODEL IN HIERARCHICAL MEMORY SYSTEMS
32
Patent #:
6260131
Issue Dt:
07/10/2001
Application #:
09195779
Filing Dt:
11/18/1998
Title:
METHOD AND APPARATUS FOR TLB MEMORY ORDERING
33
Patent #:
6269387
Issue Dt:
07/31/2001
Application #:
09206463
Filing Dt:
12/07/1998
Title:
METHOD AND APPARATUS FOR 3-STAGE 32-BIT ADDER/SUBSTRACTOR
34
Patent #:
6324239
Issue Dt:
11/27/2001
Application #:
09206539
Filing Dt:
12/07/1998
Title:
METHOD AND APPARATUS FOR A 1 OF 4 SHIFTER
35
Patent #:
6154120
Issue Dt:
11/28/2000
Application #:
09206631
Filing Dt:
12/07/1998
Title:
METHOD AND APPARATUS FOR AN N-NARY EQUALITY COMPARATOR
36
Patent #:
6347327
Issue Dt:
02/12/2002
Application #:
09206830
Filing Dt:
12/07/1998
Title:
METHOD AND APPARATUS FOR N-NARY INCREMENTOR
37
Patent #:
6295622
Issue Dt:
09/25/2001
Application #:
09206900
Filing Dt:
12/07/1998
Title:
METHOD AND APPARATUS FOR TRANSFORMING PSEUDORANDOM BINARY TEST PATTERNS INTO TEST STIMULUS PATTERNS APPROPRIATE FOR CIRCUITS HAVING 1 OF N ENCODED INPUTS
38
Patent #:
6429795
Issue Dt:
08/06/2002
Application #:
09206905
Filing Dt:
12/07/1998
Title:
METHOD AND APPARATUS FOR TRANSFORMING PSEUDORANDOM BINARY PATTERNS INTO TEST STIMULUS PATTERNS APPROPRIATE FOR CIRCUITS HAVING 1 OF N ENCODED INPUTS
39
Patent #:
6216147
Issue Dt:
04/10/2001
Application #:
09206906
Filing Dt:
12/07/1998
Title:
METHOD AND APPARATUS FOR AN N-NARY MAGNITUDE COMPARATOR
40
Patent #:
6104642
Issue Dt:
08/15/2000
Application #:
09207806
Filing Dt:
12/09/1998
Title:
METHOD AND APPARATUS FOR 1 OF 4 REGISTER FILE DESIGN
41
Patent #:
6107835
Issue Dt:
08/22/2000
Application #:
09209207
Filing Dt:
12/10/1998
Title:
A METHOD AND APPARATUS FOR A LOGIC CIRCUIT WITH CONSTANT POWER CONSUMPTION
42
Patent #:
6334136
Issue Dt:
12/25/2001
Application #:
09209935
Filing Dt:
12/11/1998
Title:
DYNAMIC 3-LEVEL PARTIAL RESULT MERGE ADDER
43
Patent #:
6124735
Issue Dt:
09/26/2000
Application #:
09209967
Filing Dt:
12/10/1998
Title:
METHOD AND APPARATUS FOR A N-NARY LOGIC CIRCUIT USING CAPACITANCE ISOLATION
44
Patent #:
6345381
Issue Dt:
02/05/2002
Application #:
09210024
Filing Dt:
12/11/1998
Title:
METHOD AND APPARATUS FOR A LOGIC CIRCUIT DESIGN TOOL
45
Patent #:
6289497
Issue Dt:
09/11/2001
Application #:
09210408
Filing Dt:
12/11/1998
Title:
METHOD AND APPARATUS FOR N-NARY HARDWARE DESCRIPTION LANGUAGE
46
Patent #:
6367065
Issue Dt:
04/02/2002
Application #:
09210410
Filing Dt:
12/11/1998
Title:
METHOD AND APPARATUS FOR N-NARY LOGIC CIRCUIT DESIGN TOOL WITH PRECHARGE CIRCUIT EVALUATION
47
Patent #:
6115294
Issue Dt:
09/05/2000
Application #:
09291659
Filing Dt:
04/14/1999
Title:
METHOD AND APPARATUS FOR MULTI-BIT REGISTER CELL
48
Patent #:
6360315
Issue Dt:
03/19/2002
Application #:
09373516
Filing Dt:
08/12/1999
Title:
METHOD AND APPARATUS THAT SUPPORTS MULTIPLE ASSIGNMENT CODE
49
Patent #:
6457170
Issue Dt:
09/24/2002
Application #:
09373840
Filing Dt:
08/13/1999
Title:
SOFTWARE SYSTEM BUILD METHOD AND APPARATUS THAT SUPPORTS MULTIPLE USERS IN A SOFTWARE DEVELOPMENT ENVIRONMENT
50
Patent #:
6438743
Issue Dt:
08/20/2002
Application #:
09374588
Filing Dt:
08/13/1999
Title:
METHOD AND APPARATUS FOR OBJECT CACHE REGISTRATION AND MAINTENANCE IN A NETWORKED SOFTWARE DEVELOPMENT ENVIRONMENT
51
Patent #:
6567835
Issue Dt:
05/20/2003
Application #:
09398618
Filing Dt:
09/17/1999
Title:
METHOD AND APPARATUS FOR A 5:2 CARRY-SAVE-ADDER (CSA)
52
Patent #:
6604065
Issue Dt:
08/05/2003
Application #:
09405474
Filing Dt:
09/24/1999
Title:
MULTIPLE-STATE SIMULATION FOR NON-BINARY LOGIC
53
Patent #:
7031897
Issue Dt:
04/18/2006
Application #:
09405618
Filing Dt:
09/24/1999
Title:
SOFTWARE MODELING OF LOGIC SIGNALS CAPABLE OF HOLDING MORE THAN TWO VALUES
54
Patent #:
6594803
Issue Dt:
07/15/2003
Application #:
09406016
Filing Dt:
09/24/1999
Title:
METHOD AND APPARATUS THAT REPORTS MULTIPLE STATUS EVENTS WITH A SINGLE MONITOR
55
Patent #:
6889180
Issue Dt:
05/03/2005
Application #:
09406017
Filing Dt:
09/24/1999
Title:
METHOD AND APPARATUS FOR A MONITOR THAT DETECTS AND REPORTS A STATUS EVENT TO A DATABASE
56
Patent #:
6252425
Issue Dt:
06/26/2001
Application #:
09458763
Filing Dt:
12/10/1999
Title:
METHOD AND APPARATUS FOR AN N-NARY LOGIC CIRCUIT
57
Patent #:
6181596
Issue Dt:
01/30/2001
Application #:
09458766
Filing Dt:
12/10/1999
Title:
METHOD AND APPARATUS FOR A RAM CIRCUIT HAVING N-NARY OUTPUT INTERFACE
58
Patent #:
6415405
Issue Dt:
07/02/2002
Application #:
09468759
Filing Dt:
12/21/1999
Title:
METHOD AND APPARATUS FOR SCAN OF SYNCHRONIZED DYNAMIC LOGIC USING EMBEDDED SCAN GATES
59
Patent #:
6412085
Issue Dt:
06/25/2002
Application #:
09468760
Filing Dt:
12/21/1999
Title:
METHOD AND APPARATUS FOR A SPECIAL STRESS MODE FOR N-NARY LOGIC THAT INITIALIZES THE LOGIC INTO A FUNCTIONALLY ILLEGAL STATE
60
Patent #:
6271683
Issue Dt:
08/07/2001
Application #:
09468972
Filing Dt:
12/21/1999
Title:
DYNAMIC LOGIC SCAN GATE METHOD AND APPARATUS
61
Patent #:
6622240
Issue Dt:
09/16/2003
Application #:
09496008
Filing Dt:
02/01/2000
Title:
METHOD AND APPARATUS FOR PRE-BRANCH INSTRUCTION
62
Patent #:
6349387
Issue Dt:
02/19/2002
Application #:
09503397
Filing Dt:
02/14/2000
Title:
Dynamic adjustment of the clock rate in logic circuits
63
Patent #:
6557021
Issue Dt:
04/29/2003
Application #:
09527653
Filing Dt:
03/17/2000
Title:
ROUNDING ANTICIPATOR FOR FLOATING POINT OPERATIONS
64
Patent #:
6499044
Issue Dt:
12/24/2002
Application #:
09546412
Filing Dt:
04/10/2000
Title:
LEADING ZERO/ONE ANTICIPATOR FOR FLOATING POINT OPERATIONS
65
Patent #:
6268746
Issue Dt:
07/31/2001
Application #:
09586638
Filing Dt:
06/05/2000
Title:
Method and apparatus for logic synchronization
66
Patent #:
6571378
Issue Dt:
05/27/2003
Application #:
09587729
Filing Dt:
06/05/2000
Title:
METHOD AND APPARATUS FOR A N-NARY LOGIC CIRCUIT USING CAPACITANCE ISOLATION
67
Patent #:
6445213
Issue Dt:
09/03/2002
Application #:
09844686
Filing Dt:
04/27/2001
Publication #:
US20020067187
Pub Dt:
06/06/2002
Title:
METHOD FOR CALCULATING DYNAMIC LOGIC BLOCK PROPAGATION DELAY TARGETS USING TIME BORROWING
68
Patent #:
6745357
Issue Dt:
06/01/2004
Application #:
09901411
Filing Dt:
07/09/2001
Publication #:
US20010039635
Pub Dt:
11/08/2001
Title:
DYNAMIC LOGIC SCAN GATE METHOD AND APPARATUS
69
Patent #:
6728654
Issue Dt:
04/27/2004
Application #:
09965945
Filing Dt:
09/28/2001
Publication #:
US20030023396
Pub Dt:
01/30/2003
Title:
RANDOM NUMBER INDEXING METHOD AND APPARATUS THAT ELIMINATES SOFTWARE CALL SEQUENCE DEPENDENCY
70
Patent #:
7099812
Issue Dt:
08/29/2006
Application #:
09966049
Filing Dt:
09/28/2001
Publication #:
US20020040285
Pub Dt:
04/04/2002
Title:
GRID THAT TRACKS THE OCCURRENCE OF A N-DIMENSIONAL MATRIX OF COMBINATORIAL EVENTS IN A SIMULATION USING A LINEAR INDEX
71
Patent #:
6732346
Issue Dt:
05/04/2004
Application #:
10155042
Filing Dt:
05/24/2002
Publication #:
US20020178428
Pub Dt:
11/28/2002
Title:
GENERATION OF ROUTE RULES
72
Patent #:
6898691
Issue Dt:
05/24/2005
Application #:
10164040
Filing Dt:
06/06/2002
Publication #:
US20020198911
Pub Dt:
12/26/2002
Title:
REARRANGING DATA BETWEEN VECTOR AND MATRIX FORMS IN A SIMD MATRIX PROCESSOR
73
Patent #:
7346484
Issue Dt:
03/18/2008
Application #:
10177527
Filing Dt:
06/21/2002
Publication #:
US20030046645
Pub Dt:
03/06/2003
Title:
MONITOR MANAGER THAT CREATES AND EXECUTES STATE MACHINE-BASED MONITOR INSTANCES IN A DIGITAL SIMULATION
74
Patent #:
6714045
Issue Dt:
03/30/2004
Application #:
10186770
Filing Dt:
07/01/2002
Publication #:
US20030042935
Pub Dt:
03/06/2003
Title:
STATIC TRANSMISSTION OF FAST14 LOGIC 1-OF-N SIGNALS
75
Patent #:
6956406
Issue Dt:
10/18/2005
Application #:
10187879
Filing Dt:
07/02/2002
Publication #:
US20030110404
Pub Dt:
06/12/2003
Title:
STATIC STORAGE ELEMENT FOR DYNAMIC LOGIC
76
Patent #:
7053664
Issue Dt:
05/30/2006
Application #:
10300289
Filing Dt:
11/20/2002
Publication #:
US20040006753
Pub Dt:
01/08/2004
Title:
NULL VALUE PROPAGATION FOR FAST14 LOGIC
77
Patent #:
7219326
Issue Dt:
05/15/2007
Application #:
10738278
Filing Dt:
12/16/2003
Publication #:
US20050060128
Pub Dt:
03/17/2005
Title:
PHYSICAL REALIZATION OF DYNAMIC LOGIC USING PARAMETERIZED TILE PARTITIONING
78
Patent #:
7299461
Issue Dt:
11/20/2007
Application #:
10738281
Filing Dt:
12/16/2003
Publication #:
US20040139423
Pub Dt:
07/15/2004
Title:
EXPANSION SYNTAX
79
Patent #:
7956636
Issue Dt:
06/07/2011
Application #:
12526691
Filing Dt:
08/11/2009
Publication #:
US20100045333
Pub Dt:
02/25/2010
Title:
GENERATING TEST BENCHES FOR PRE-SILICON VALIDATION OF RETIMED COMPLEX IC DESIGNS AGAINST A REFERENCE DESIGN
80
Patent #:
7956636
Issue Dt:
06/07/2011
Application #:
12526691
Filing Dt:
08/11/2009
Publication #:
US20100045333
Pub Dt:
02/25/2010
PCT #:
US0855587
Title:
GENERATING TEST BENCHES FOR PRE-SILICON VALIDATION OF RETIMED COMPLEX IC DESIGNS AGAINST A REFERENCE DESIGN
81
Patent #:
8450991
Issue Dt:
05/28/2013
Application #:
12743689
Filing Dt:
05/19/2010
Publication #:
US20100253311
Pub Dt:
10/07/2010
PCT #:
US0883962
Title:
CHARGE RECYCLING A 1 OF N NDL GATE WITH A TIME VARYING POWER SUPPLY
82
Patent #:
8448107
Issue Dt:
05/21/2013
Application #:
13127936
Filing Dt:
05/05/2011
PCT #:
US0949930
Title:
Method For Piecewise Hierarchical Sequential Verification
83
Patent #:
8443319
Issue Dt:
05/14/2013
Application #:
13128153
Filing Dt:
05/06/2011
PCT #:
US0962337
Title:
METHOD FOR PREPARING RE-ARCHITECTED DESIGNS FOR SEQUENTIAL EQUIVALENCE CHECKING
Assignor
1
INTRINSITY, INC.
Exec Dt:
04/01/2010
Assignee
1
APPLE INC.
1 INFINITE LOOP
CUPERTINO, CALIFORNIA 95014
Correspondence name and address
RICHARD J. LUTTON, JR.
1 INFINITE LOOP
CUPERTINO, CA 95014

Search Results as of: 05/26/2024 01:44 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT