Total properties:
419
Page
2
of
5
Pages:
1 2 3 4 5
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
|
08811548
|
Filing Dt:
|
03/04/1997
|
|
Title:
|
CIRCUIT FOR IMMUNIZING AN INTEGRATED CIRCUIT FROM NOISE AFFECTING ENABLE SIGNALS OF THE INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/1999
|
Application #:
|
08811577
|
Filing Dt:
|
03/05/1997
|
|
Title:
|
INTEGRATED DEVICE WITH PADS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/1998
|
Application #:
|
08811869
|
Filing Dt:
|
03/05/1997
|
|
Title:
|
ADDRESS TRANSITION DETECTION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/1998
|
Application #:
|
08812595
|
Filing Dt:
|
03/07/1997
|
|
Title:
|
NON-VOLATILE MEMORY DEVICE HAVING OPTIMIZED MANAGEMENT OF DATA TRANSMISSION LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
08813687
|
Filing Dt:
|
03/07/1997
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2001
| | | | |
|
Title:
|
TIMESHARING INTERNAL BUS, PARTICULARLY FOR NON-VOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2000
|
Application #:
|
08816766
|
Filing Dt:
|
03/18/1997
|
|
Title:
|
METHOD FOR RECOVERING FAILED MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
08819519
|
Filing Dt:
|
03/17/1997
|
|
Title:
|
CIRCUIT FOR DETECTING THE COINCIDENCE BETWEEN A BINARY INFORMATION UNIT STORED THEREIN AND AN EXTERNAL DATUM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/1998
|
Application #:
|
08821804
|
Filing Dt:
|
03/21/1997
|
|
Title:
|
SECTORIZED ELECTRICALLY ERASABLE AND PROGRAMMABLE NON-VOLATILE MEMORY DEVICE WITH REDUNDANCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/1998
|
Application #:
|
08824616
|
Filing Dt:
|
03/27/1997
|
|
Title:
|
ROW DECODING CIRCUIT FOR SEMICONDUCTOR NON-VOLATILE ELECTRICALLY PROGRAMMABLE MEMORY AND CORRESPONDING METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
08824888
|
Filing Dt:
|
03/18/1997
|
|
Title:
|
HIGH-VOLTAGE-RESISTANT MOS TRANSISTOR, AND CORRESPONDING MANUFACTURING PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/1998
|
Application #:
|
08824958
|
Filing Dt:
|
03/27/1997
|
|
Title:
|
VOLTAGE BOOSTER FOR MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/1999
|
Application #:
|
08825098
|
Filing Dt:
|
03/27/1997
|
|
Title:
|
DATA SENSING TIMING MODULATING CIRCUIT, PARTICULARLY FOR NON-VOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
08825138
|
Filing Dt:
|
03/28/1997
|
|
Title:
|
CIRCUIT AND METHOD TO ADJUST MEMORY TIMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1999
|
Application #:
|
08826008
|
Filing Dt:
|
03/27/1997
|
|
Title:
|
STANDBY VOLTAGE BOOSTING STAGE AND METHOD FOR A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/1999
|
Application #:
|
08826009
|
Filing Dt:
|
03/27/1997
|
|
Title:
|
PULSE GENERATION CIRCUIT AND METHOD FOR SYNCHRONIZED DATA LOADING IN AN OUTPUT PRE-BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/1998
|
Application #:
|
08826223
|
Filing Dt:
|
03/27/1997
|
|
Title:
|
DRIVER DEVICE FOR SELECTION LINES FOR A MULTIPLEXER, TO BE USED IN A WIDE RANGE OF SUPPLY VOLTAGES, PARTICULARLY FOR NON-VOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
08826489
|
Filing Dt:
|
03/27/1997
|
|
Title:
|
NONVOLATILE MEMORY DEVICE CAPABLE OF READING DATA WITH AN APPROPRIATE SELF-TIMING AND A REDUCED NUMBER OF REFERENCE LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/1999
|
Application #:
|
08827409
|
Filing Dt:
|
03/27/1997
|
|
Title:
|
SYSTEM FOR DETERMINING THE PROGRAMMED/NON PROGRAMMED STATUS OF A MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/1998
|
Application #:
|
08828039
|
Filing Dt:
|
03/27/1997
|
|
Title:
|
METHOD AND APPARATUS FOR REDUNDANCY MANAGEMENT OF NON-VOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/1999
|
Application #:
|
08828790
|
Filing Dt:
|
03/27/1997
|
|
Title:
|
GAIN MODULATED SENSE AMPLIFIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
08828791
|
Filing Dt:
|
03/27/1997
|
|
Title:
|
CIRCUIT AND METHOD FOR GENERATING A POWER-ON RESET SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
08833336
|
Filing Dt:
|
04/04/1997
|
|
Title:
|
VOLTAGE REGULATOR FOR PROGRAMMING ELECTRICALLY PROGRAMMABLE NON-VOLATILE MEMORY CELLS IN A CELL MATRIX
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/1998
|
Application #:
|
08833925
|
Filing Dt:
|
04/10/1997
|
|
Title:
|
FLASH-EPROM WITH EMBEDDED EEPROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2000
|
Application #:
|
08835030
|
Filing Dt:
|
03/28/1997
|
|
Title:
|
A MEMORY UNDER TEST PROGRAMMING AND READING DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/1998
|
Application #:
|
08835031
|
Filing Dt:
|
03/27/1997
|
|
Title:
|
CIRCUIT FOR THE GENERATION OF A VOLTAGE AS A FUNCTION OF THE CONDUCTIVITY OF AN ELEMENTARY CELL OF A NON-VOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/1998
|
Application #:
|
08835033
|
Filing Dt:
|
03/27/1997
|
|
Title:
|
REFERENCE WORD LINE AND DATA PROPAGATION REPRODUCTION CIRCUIT FOR MEMORIES PROVIDED WITH HIERARCHICAL DECODERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/1998
|
Application #:
|
08835294
|
Filing Dt:
|
04/07/1997
|
|
Title:
|
CIRCUIT FOR THE SWITCHING OF SUPPLY VOLTAGES IN ELECTRICALLY PROGRAMMABLE AND CANCELABLE NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/1999
|
Application #:
|
08835296
|
Filing Dt:
|
04/07/1997
|
|
Title:
|
AUTO-SAVING CIRCUIT FOR PROGRAMMING CONFIGURATION ELEMENTS IN NON-VOLATILE MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
08835347
|
Filing Dt:
|
04/07/1997
|
|
Title:
|
PRE-CHARGE STEP DETERMINING CIRCUIT OF A GENERIC BIT LINE PARTICULARLY FOR NON-VOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/1999
|
Application #:
|
08840056
|
Filing Dt:
|
04/24/1997
|
|
Title:
|
CIRCUITS AND METHODS FOR READ-ENABLING MEMORY DEVICES SYNCHRONOUSLY WITHTHE REACHING OF THE MINIMUM FUNCTIONALITY CONDITIONS OF THE MEMORY CELLS AND READING CIRCUITS, PARTICULARLY FOR NON-VOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/1998
|
Application #:
|
08841903
|
Filing Dt:
|
04/17/1997
|
|
Title:
|
REDUNDANCY MEMORY REGISTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/1998
|
Application #:
|
08841904
|
Filing Dt:
|
04/17/1997
|
|
Title:
|
METHOD FOR DETECTING REDUNDED DEFECTIVE ADDRESSES IN A MEMORY DEVICE WITH REDUNDANCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1999
|
Application #:
|
08842835
|
Filing Dt:
|
04/17/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH ROW REDUNDANCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/1999
|
Application #:
|
08845916
|
Filing Dt:
|
04/29/1997
|
|
Title:
|
SENSING CIRCUITRY FOR READING AND VERIFYING THE CONTENTS OF ELECTRICALLY PROGRAMMABLE/ERASABLE NON-VOLATILE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/1999
|
Application #:
|
08846753
|
Filing Dt:
|
04/30/1997
|
|
Title:
|
BIASING CIRCUIT FOR UPROM CELLS WITH LOW VOLTAGE SUPPLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/1998
|
Application #:
|
08846755
|
Filing Dt:
|
04/30/1997
|
|
Title:
|
UPROM CELL FOR LOW VOLTAGE SUPPLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08846757
|
Filing Dt:
|
04/30/1997
|
|
Title:
|
POWER ON RESET CIRCUIT WITH AUTO TURN OFF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/1999
|
Application #:
|
08847385
|
Filing Dt:
|
04/24/1997
|
|
Title:
|
MEMORY ARCHITECTURE FOR FLEXIBLE READING MANAGEMENT, PARTICULARLY FOR NON-VOLATILE MEMORIES, HAVING NOISE-IMMUNITY FEATURES, MATCHING DEVICE PERFORMANCE, AND HAVING OPTIMIZED THROUGHOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/1998
|
Application #:
|
08853732
|
Filing Dt:
|
05/09/1997
|
|
Title:
|
COLUMN MULTIPLEXER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
08853756
|
Filing Dt:
|
05/08/1997
|
|
Title:
|
ELECTRICALLY ERASABLE AND PROGRAMMABLE NON-VOLATILE MEMORY DEVICE WITH TESTABLE REDUNDANCY CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2000
|
Application #:
|
08862563
|
Filing Dt:
|
05/23/1997
|
|
Title:
|
LINE DECODER FOR MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
08865642
|
Filing Dt:
|
05/30/1997
|
|
Title:
|
METHOD AND CIRCUIT ARCHITECTURE FOR TESTING A NON-VOLATILE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
08865748
|
Filing Dt:
|
05/30/1997
|
|
Title:
|
SYNCHRONIZATION SIGNAL GENERATION CIRCUIT AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/1999
|
Application #:
|
08866283
|
Filing Dt:
|
05/30/1997
|
|
Title:
|
INTEGRATED CIRCUIT FOR GENERATING INITIALIZATION SIGNALS FOR MEMORY CELL SENSING CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/1999
|
Application #:
|
08866531
|
Filing Dt:
|
05/30/1997
|
|
Title:
|
METHOD FOR VERIFYING ELECTRICALLY PROGRAMMABLE NON-VOLATILE MEMORY CELLS OF AN ELECTRICALLY PROGRAMMABLE NON-VOLATILE MEMORY DEVICE AFTER PROGRAMMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/1998
|
Application #:
|
08868213
|
Filing Dt:
|
06/03/1997
|
|
Title:
|
MEMORY DEVICE WITH CLOCKED COLUMN REDUNDANCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08868214
|
Filing Dt:
|
06/03/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH CLOCKED COLUMN REDUNDANCY AND TIME-SHARED REDUNDANCY DATA TRANSFER APPROACH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/1998
|
Application #:
|
08869208
|
Filing Dt:
|
06/05/1997
|
|
Title:
|
PAGE-MODE MEMORY DEVICE WITH MULTIPLE-LEVEL MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/1999
|
Application #:
|
08869367
|
Filing Dt:
|
06/05/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH ROW AND COLUMN REDUNDANCY CIRCUITS AND A TIME-SHARED REDUNDANCY CIRCUIT TEST ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/1999
|
Application #:
|
08869859
|
Filing Dt:
|
06/05/1997
|
|
Title:
|
CIRCUIT FOR TRANSFERRING REDUNDANCY DATA OF A REDUNDANCY CIRCUIT INSIDE A MEMORY DEVICE BY MEANS OF A TIME-SHARED APPROACH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/1998
|
Application #:
|
08877921
|
Filing Dt:
|
06/18/1997
|
|
Title:
|
CIRCUIT AND METHOD FOR GENERATING A READ REFERENCE SIGNAL FOR NONVOLATILE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
08877922
|
Filing Dt:
|
06/18/1997
|
|
Title:
|
READ CIRCUIT AND METHOD FOR NONVOLATILE MEMORY CELLS WITH AN EQUALIZING STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
|
08877927
|
Filing Dt:
|
06/18/1997
|
|
Title:
|
LOW-SUPPLY-VOLTAGE NONVOLATILE MEMORY DEVICE WITH VOLTAGE BOOSTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
08879017
|
Filing Dt:
|
06/18/1997
|
|
Title:
|
METHOD AND CIRCUIT FOR READING LOW-SUPPLY-VOLTAGE NONVOLATILE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08883822
|
Filing Dt:
|
06/27/1997
|
|
Title:
|
CLOCK CIRCUIT FOR READING A MUTILEVEL NON VOLATILE MEMORY CELLS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
08889653
|
Filing Dt:
|
07/08/1997
|
|
Title:
|
LOW NOISE OUTPUT BUFFER FOR SEMICONDUCTOR ELECTRONIC CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
08897799
|
Filing Dt:
|
07/21/1997
|
|
Title:
|
PROCESS FOR MANUFACTURING AN INTEGRATED CIRCUIT COMPRISING AN ARRAY OF MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2000
|
Application #:
|
08898811
|
Filing Dt:
|
07/23/1997
|
|
Title:
|
HIGH VOLTAGE TOLERANCE OUTPUT STAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
08899228
|
Filing Dt:
|
07/23/1997
|
|
Title:
|
OUTPUT STAGE FOR A MEMORY DEVICE AND FOR LOW VOLTAGE APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2001
|
Application #:
|
08900165
|
Filing Dt:
|
07/28/1997
|
|
Title:
|
BIDIRECTIONAL CHARGE PUMP GENERATING EITHER A POSITIVE OR NEGATIVE VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2000
|
Application #:
|
08900424
|
Filing Dt:
|
07/25/1997
|
|
Title:
|
ASYMMETRICAL PULSIVE DELAY NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
08916874
|
Filing Dt:
|
08/22/1997
|
|
Title:
|
MULTILEVEL NON-VOLATILE MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
08921930
|
Filing Dt:
|
08/27/1997
|
|
Title:
|
CMOS TWIN-TUB NEGATIVE VOLTAGE SWITCHING ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/1999
|
Application #:
|
08927391
|
Filing Dt:
|
08/27/1997
|
|
Title:
|
STACKED CHARGE PUMP CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/1999
|
Application #:
|
08934499
|
Filing Dt:
|
09/19/1997
|
|
Title:
|
CONTROL CIRCUIT OF AN OUTPUT BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/1999
|
Application #:
|
08940115
|
Filing Dt:
|
09/29/1997
|
|
Title:
|
NEADING CIRCUIT FOR SEMICONDUCTOR MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
08940278
|
Filing Dt:
|
09/30/1997
|
|
Title:
|
FLOATING GATE MOS TRANSISTOR CHARGE INJECTION CIRCUIT AND COMPUTATION DEVICES INCORPORATING IT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/1999
|
Application #:
|
08941882
|
Filing Dt:
|
09/30/1997
|
|
Title:
|
METHOD AND CIRCUIT FOR CHECKING MULTILEVEL PROGRAMMING OF FLOATING-GATE NONVOLATILE MEMORY CELLS PARTICULARLY FLASH CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
08946727
|
Filing Dt:
|
10/08/1997
|
|
Title:
|
POSITIVE CHARGE PUMP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
08957685
|
Filing Dt:
|
10/24/1997
|
|
Title:
|
CIRCUIT FOR SELECTIVELY ENABLING ONE AMONG A PLURALITY OF CIRCUIT ALTERNATIVES OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08960926
|
Filing Dt:
|
10/30/1997
|
|
Title:
|
SELF-REGULATED EQUALIZER, PARTICULARLY FOR SENSE AMPLIFIERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/1998
|
Application #:
|
08961368
|
Filing Dt:
|
10/30/1997
|
|
Title:
|
PROTECTION CIRCUIT FOR REDUNDANCY REGISTER SET-UP CELLS OF ELECTRICALLY PROGRAMMABLE NON-VOLATILE MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2000
|
Application #:
|
08965068
|
Filing Dt:
|
11/05/1997
|
|
Title:
|
BICMOS NEGATIVE CHARGE PUMP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
08978665
|
Filing Dt:
|
11/26/1997
|
|
Title:
|
METHOD AND CIRCUIT FOR GENERATING A SYNCHRONIZING ATD SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
08987454
|
Filing Dt:
|
12/09/1997
|
|
Title:
|
PROCESS FOR REALIZING AN INTERMEDIATE DIELECTRIC LAYER FOR ENHANCING THE PLANARITY IN SEMICONDUCTOR ELECTRONIC DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1999
|
Application #:
|
08990328
|
Filing Dt:
|
12/15/1997
|
|
Title:
|
PROCESS FOR THE REPAIR OF FLOATING-GATE NON-VOLATILE MEMORIES DAMAGED BY PLASMA TREATMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
08996920
|
Filing Dt:
|
12/23/1997
|
|
Title:
|
PROCESS FOR DEPOSITING A STRATIFIED DIELECTRIC STRUCTURE FOR ENHANCING THE PLANARITY OF SEMICONDUCTOR ELECTRONIC DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2000
|
Application #:
|
08997499
|
Filing Dt:
|
12/23/1997
|
|
Title:
|
AUTOALIGNED ETCHING PROCESS FOR REALIZING WORD LINES IN MEMORY DEVICES INTEGRATED SEMICONDUCTOR SUBTRATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08998854
|
Filing Dt:
|
12/29/1997
|
|
Title:
|
ELECTRONIC MEMORY DEVICE HAVING BIT LINES WITH BLOCK SELECTOR SWITCHES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2000
|
Application #:
|
09002599
|
Filing Dt:
|
01/05/1998
|
|
Title:
|
FOLDING TOP FOR A MOTOR VEHICLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2000
|
Application #:
|
09003474
|
Filing Dt:
|
01/06/1998
|
|
Title:
|
POWER-ON RESET CIRCUIT FOR DUAL SUPPLY VOLTAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2000
|
Application #:
|
09012331
|
Filing Dt:
|
01/23/1998
|
|
Title:
|
NMOS NEGATIVE CHARGE PUMP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
09027343
|
Filing Dt:
|
02/20/1998
|
|
Title:
|
MEMORY DEVICE WITH A MEMORY CELL ARRAY IN TRIPLE WELL, AND RELATED MANUFACTURING PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
09030604
|
Filing Dt:
|
02/25/1998
|
|
Title:
|
VOLTAGE LEVEL SHIFTER DEVICE, PARTICULARY FOR A NONVOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
09032272
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
METHOD AND CIRCUIT FOR TRIMMING THE INTERNAL TIMING CONDITIONS OF A SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/1999
|
Application #:
|
09032282
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
STAIRCASE ADAPTIVE VOLTAGE GENERATOR CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
09039588
|
Filing Dt:
|
03/16/1998
|
|
Title:
|
METHOD AND DEVICE FOR READING A NON-ERASABLE MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
09049858
|
Filing Dt:
|
03/27/1998
|
|
Title:
|
DEVICE AND METHOD FOR INCREASING THE INTERNAL ADDRESS OF A
MEMORY DEVICE USING MULTIFUNCTIONAL TERMINALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
09053720
|
Filing Dt:
|
04/01/1998
|
|
Title:
|
MEMORY DEVICE WITH REDUCED POWER DISSIPATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
|
Application #:
|
09076013
|
Filing Dt:
|
05/11/1998
|
|
Title:
|
METHOD AND DEVICE FOR ANALOG PROGRAMMING OF NON-VOLATILE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09119115
|
Filing Dt:
|
07/20/1998
|
|
Title:
|
HIGH VOLTAGE CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
|
Application #:
|
09130720
|
Filing Dt:
|
08/06/1998
|
|
Title:
|
PROCESS FOR THE MANUFACTURING OF AN ELECTRICALLY PROGRAMMABLE NON-VOLATILE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2000
|
Application #:
|
09139909
|
Filing Dt:
|
08/26/1998
|
|
Title:
|
METHOD FOR MANUFACTURING A NATIVE MOS P-CHANNEL TRANSISTOR WITH A PROCESS FOR MANUFACTURING NON-VOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2000
|
Application #:
|
09141250
|
Filing Dt:
|
08/27/1998
|
|
Title:
|
METHOD AND CIRCUIT FOR GENERATING A GATE VOLTAGE IN NON-VOLATILE MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
09162639
|
Filing Dt:
|
09/28/1998
|
|
Title:
|
METHOD AND DEVICE FOR ANALOG PROGRAMMING OF FLASH EEPROM MEMORY CELLS WITH AUTOVERIFY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
09163755
|
Filing Dt:
|
09/30/1998
|
|
Title:
|
COMPENSATED VOLTAGE REGULATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
09169239
|
Filing Dt:
|
10/08/1998
|
|
Title:
|
CONTROLLED HOT-ELECTRON WRITING METHOD FOR NON-VOLATILE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09170788
|
Filing Dt:
|
10/13/1998
|
|
Title:
|
IMPROVED OUTPUT CIRCUIT FOR INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2003
|
Application #:
|
09175220
|
Filing Dt:
|
10/19/1998
|
|
Title:
|
MEMORY DEVICE GENERATOR FOR GENERATING MEMORY DEVICES WITH REDUNDANCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2000
|
Application #:
|
09181230
|
Filing Dt:
|
10/27/1998
|
|
Title:
|
METHOD FOR PARALLEL PROGRAMMING OF NONVOLATILE MEMORY DEVICES, IN PARTICULAR FLASH MEMORIES AND EEPROMS
|
|
