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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09871234
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Filing Dt:
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05/30/2001
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Publication #:
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Pub Dt:
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02/07/2002
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Title:
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CIRCUITAL STRUCTURE FOR READING DATA IN A NON-VOLATILE MEMORY DEVICE
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09881661
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Filing Dt:
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06/13/2001
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Publication #:
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Pub Dt:
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01/24/2002
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Title:
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CIRCUIT ARRANGEMENT FOR THE LOWERING OF THE THRESHOLD VOLTAGE OF A DIODE CONFIGURED TRANSISTOR
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09882535
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Filing Dt:
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06/14/2001
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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BIASING CIRCUIT FOR MULTI-LEVEL MEMORY CELLS
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09898744
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Filing Dt:
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07/03/2001
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Publication #:
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Pub Dt:
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02/21/2002
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Title:
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NON-VOLATILE MEMORY MATRIX ARCHITECTURE WITH VERTICAL INSULATION STRIPS BETWEEN ADJACENT MEMORY BLOCKS.
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09900501
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Filing Dt:
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07/06/2001
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Publication #:
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Pub Dt:
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02/28/2002
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Title:
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PROCESS FOR MANUFACTURING A NON-VOLATILE MEMORY CELL WITH A FLOATING GATE REGION AUTOALIGNED TO THE ISOLATION AND WITH A HIGH COUPLING COEFFICIENT
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09905163
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Filing Dt:
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07/12/2001
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Title:
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CIRCUIT DEVICE FOR PERFORMING HIERARCHIC ROW DECODING IN NON-VOLATILE MEMORY DEVICES
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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09917613
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Filing Dt:
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07/26/2001
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Publication #:
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Pub Dt:
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03/21/2002
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Title:
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CONDUCTION LINE DECOUPLING CIRCUIT
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Patent #:
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Issue Dt:
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12/03/2002
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Application #:
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09925842
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Filing Dt:
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08/08/2001
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Publication #:
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Pub Dt:
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08/08/2002
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Title:
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OUTPUT BUFFER AND METHOD OF DRIVING
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09952957
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Filing Dt:
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09/12/2001
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Publication #:
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Pub Dt:
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06/13/2002
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Title:
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METHOD AND CIRCUIT FOR PROGRAMMING A MULTILEVEL NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09953070
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Filing Dt:
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09/13/2001
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Publication #:
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Pub Dt:
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05/16/2002
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Title:
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READING CIRCUIT FOR SEMICONDUCTOR NON-VOLATILE MEMORIES
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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09960254
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Filing Dt:
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09/20/2001
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Publication #:
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Pub Dt:
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04/11/2002
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Title:
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LATERAL DMOS TRANSISTOR WITH FIRST AND SECOND DRAIN ELECTRODES IN RESPECTIVE CONTACT WITH HIGH-AND LOW-CONCENTRATION PORTIONS OF A DRAIN REGION
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09960851
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Filing Dt:
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09/21/2001
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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CONTROL CIRCUIT FOR A VARIABLE-VOLTAGE REGULATOR OF A NONVOLATILE MEMORY WITH HIERARCHICAL ROW DECODING
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09972726
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Filing Dt:
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10/04/2001
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Publication #:
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Pub Dt:
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04/25/2002
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Title:
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SMALL SIZE, LOW CONSUMPTION, MULTILEVEL NONVOLATILE MEMORY
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09972753
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Filing Dt:
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10/05/2001
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Publication #:
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Pub Dt:
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06/06/2002
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Title:
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CONTROL AND TIMING STRUCTURE FOR A MEMORY
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09977769
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Filing Dt:
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10/15/2001
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Publication #:
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Pub Dt:
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02/14/2002
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Title:
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FLANGED PIPE FITTING
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09991493
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Filing Dt:
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11/21/2001
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Publication #:
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Pub Dt:
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07/18/2002
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Title:
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CONTROL CIRCUIT FOR AN OUTPUT DRIVING STAGE OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09997227
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Filing Dt:
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11/29/2001
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Publication #:
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Pub Dt:
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05/29/2003
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Title:
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METHOD FOR AVOIDING THE EFFECTS OF LACK OF UNIFORMITY IN TRENCH ISOLATED INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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04/13/2004
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Application #:
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09998902
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Filing Dt:
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10/31/2001
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Publication #:
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Pub Dt:
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05/01/2003
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Title:
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NEGATIVE CHARGE PUMP ARCHITECTURE WITH SELF-GENERATED BOOSTED PHASES
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09998903
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Filing Dt:
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10/31/2001
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Title:
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CIRCUIT FOR GENERATING A PULSE SIGNAL INDEPENDENT OF VOLTAGE AND TEMPERATURE VARIATIONS
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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10017502
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Filing Dt:
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12/14/2001
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Publication #:
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Pub Dt:
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10/17/2002
| | | | |
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Title:
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PROGRAMMING METHOD FOR A MULTILEVEL MEMORY CELL
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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10033711
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Filing Dt:
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12/28/2001
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Publication #:
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Pub Dt:
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10/24/2002
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Title:
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GENERATOR CIRCUIT FOR VOLTAGE RAMPS AND CORRESPONDING VOLTAGE GENERATION METHOD
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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10035006
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Filing Dt:
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12/27/2001
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Publication #:
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Pub Dt:
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10/17/2002
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Title:
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MULTI-EMITTER BIPOLAR TRANSISTOR FOR BANDGAP REFERENCE CIRCUITS
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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10036337
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Filing Dt:
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12/19/2001
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Publication #:
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Pub Dt:
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08/08/2002
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Title:
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METHOD OF PROGRAMMING A PLURALITY OF MEMORY CELLS CONNECTED IN PARALLEL, AND A PROGRAMMING CIRCUIT THEREFOR
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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10041684
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Filing Dt:
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10/24/2001
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Title:
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MEMORY DEVICE
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10047918
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Filing Dt:
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01/14/2002
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Publication #:
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Pub Dt:
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10/17/2002
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Title:
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METHOD AND CIRCUIT FOR DYNAMIC READING OF A MEMORY CELL, IN PARTICULAR A MULTI-LEVEL NONVOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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10057768
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Filing Dt:
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01/24/2002
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Publication #:
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Pub Dt:
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08/22/2002
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Title:
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METHOD FOR REFRESHING STORED DATA IN AN ELECTRICALLY ERASABLE AND PROGRAMMABLE NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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10057769
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Filing Dt:
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01/24/2002
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Publication #:
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Pub Dt:
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10/24/2002
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Title:
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NON-VOLATILE, ELECTRICALLY ALTERABLE SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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10076023
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Filing Dt:
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02/13/2002
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Publication #:
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Pub Dt:
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10/17/2002
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Title:
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METHOD AND CIRCUIT FOR DYNAMIC READING OF A MEMORY CELL AT LOW SUPPLY VOLTAGE AND WITH LOW OUTPUT DYNAMICS
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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10076134
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Filing Dt:
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02/13/2002
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Publication #:
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Pub Dt:
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11/14/2002
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Title:
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BOOST DEVICE FOR NONVOLATILE MEMORIES WITH AN INTEGRATED STAND-BY CHARGE PUMP
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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10077687
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Filing Dt:
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02/15/2002
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Publication #:
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Pub Dt:
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10/10/2002
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Title:
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DEVICE AND METHOD FOR TIMING THE READING OF A NONVOLATILE MEMORY WITH REDUCED SWITCHING NOISE
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Patent #:
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Issue Dt:
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07/12/2005
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Application #:
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10115888
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Filing Dt:
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04/03/2002
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Publication #:
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Pub Dt:
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12/05/2002
| | | | |
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Title:
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DEVICE AND METHOD FOR AUTOMATICALLY GENERATING AN APPROPRIATE NUMBER OF WAIT CYCLES WHILE READING A NONVOLATILE MEMORY
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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10123874
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Filing Dt:
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04/16/2002
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Publication #:
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Pub Dt:
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12/05/2002
| | | | |
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Title:
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METHOD AND CIRCUIT FOR TIMING DYNAMIC READING OF A MEMORY CELL WITH CONTROL OF THE INTEGRATION TIME
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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10158553
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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COLUMN MULTIPLEXER FOR SEMICONDUCTOR MEMORIES
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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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10159782
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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01/23/2003
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Title:
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METHOD FOR ERROR CONTROL IN MULTILEVEL CELLS WITH CONFIGURABLE NUMBER OF STORED BITS
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10161053
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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03/13/2003
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Title:
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OUTPUT BUFFER FOR A NONVOLATILE MEMORY WITH OUTPUT SIGNAL SWITCHING NOISE REDUCTION, AND NONVOLATILE MEMORY COMPRISING THE SAME
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10161055
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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03/27/2003
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Title:
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OUTPUT BUFFER FOR A NONVOLATILE MEMORY WITH OPTIMIZED SLEW-RATE CONTROL
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Patent #:
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Issue Dt:
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08/12/2003
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Application #:
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10162135
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Filing Dt:
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06/03/2002
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Publication #:
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Pub Dt:
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02/20/2003
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Title:
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HIGH-EFFICIENCY POWER CHARGE PUMP SUPPLYING HIGH DC OUTPUT CURRENTS
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10171078
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Filing Dt:
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06/12/2002
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Publication #:
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Pub Dt:
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12/12/2002
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Title:
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METHOD OF RE-PROGRAMMING AN ARRAY OF NON-VOLATILE MEMORY CELLS, IN PARTICULAR OF THE NOR ARCHITECTURE FLASH TYPE, AFTER AN ERASE OPERATION, AND A CORRESPONDING MEMORY DEVICE
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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10176954
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Filing Dt:
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06/20/2002
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Publication #:
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Pub Dt:
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01/23/2003
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Title:
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MEMORY WITH IMPROVED DIFFERENTIAL READING SYSTEM
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Patent #:
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Issue Dt:
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04/13/2004
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Application #:
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10189152
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Filing Dt:
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07/02/2002
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Publication #:
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Pub Dt:
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02/06/2003
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Title:
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PROCESS FOR REMOVING POLYMERS DURING THE FABRICATION OF SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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10225513
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Filing Dt:
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08/20/2002
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Publication #:
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Pub Dt:
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04/10/2003
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Title:
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EEPROM FLASH MEMORY ERASABLE LINE BY LINE
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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10271352
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Filing Dt:
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10/15/2002
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Publication #:
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Pub Dt:
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05/08/2003
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Title:
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NONVOLATILE MEMORY DEVICE WITH DOUBLE SERIAL/PARALLEL COMMUNICATION INTERFACE
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Patent #:
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Issue Dt:
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12/27/2005
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Application #:
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10281078
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Filing Dt:
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10/24/2002
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Publication #:
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Pub Dt:
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06/05/2003
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Title:
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FAST PROGRAMMING METHOD FOR NONVOLATILE MEMORIES, IN PARTICULAR FLASH MEMORIES, AND RELATIVE MEMORY ARCHITECTURE
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Patent #:
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Issue Dt:
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10/16/2007
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Application #:
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10309759
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Filing Dt:
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12/04/2002
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Publication #:
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Pub Dt:
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07/03/2003
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Title:
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FINITE STATE MACHINE INTERFACE HAS ARBITRATION STRUCTURE TO STORE COMMAND GENERATED BY INTERNAL CIRCUITS DURING EVALUATION PHASE OF STATE MACHINE FOR FLASH EEPROM DEVICE
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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10319439
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Filing Dt:
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12/12/2002
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Publication #:
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Pub Dt:
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10/02/2003
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Title:
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ARCHITECTURE OF A PHASE-CHANGE NONVOLATILE MEMORY ARRAY
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Patent #:
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Issue Dt:
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08/28/2007
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Application #:
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10323615
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Filing Dt:
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12/18/2002
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Publication #:
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Pub Dt:
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12/04/2003
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Title:
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MANUFACTURING PROCESS OF A SEMICONDUCTOR NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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10325707
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Filing Dt:
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12/20/2002
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Publication #:
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Pub Dt:
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07/03/2003
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Title:
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BINARY ENCODING CIRCUIT
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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10331106
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Filing Dt:
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12/27/2002
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Publication #:
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Pub Dt:
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07/31/2003
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Title:
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REGULATION METHOD FOR THE SOURCE TERMINAL VOLTAGE IN A NON-VOLATILE MEMORY CELL DURING A PROGRAM PHASE AND CORRESPONDING PROGRAM CIRCUIT
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Patent #:
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Issue Dt:
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10/05/2004
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Application #:
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10331147
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Filing Dt:
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12/27/2002
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Publication #:
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Pub Dt:
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07/31/2003
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Title:
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CIRCUIT FOR CONTROLLING A REFERENCE NODE IN A SENSE AMPLIFIER
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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10331158
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Filing Dt:
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12/26/2002
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Publication #:
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Pub Dt:
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08/21/2003
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Title:
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SENSE AMPLIFIER STRUCTURE FOR MULTILEVEL NON-VOLATILE MEMORY DEVICES AND CORRESPONDING READING METHOD
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Patent #:
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Issue Dt:
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10/25/2005
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Application #:
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10331177
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Filing Dt:
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12/27/2002
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Publication #:
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Pub Dt:
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08/07/2003
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Title:
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DECODING STRUCTURE FOR A MEMORY DEVICE WITH A CONTROL CODE
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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10340207
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Filing Dt:
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01/10/2003
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Publication #:
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Pub Dt:
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07/17/2003
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Title:
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ARCHITECTURE FOR A FLASH-EEPROM SIMULTANEOUSLY READABLE IN OTHER SECTORS WHILE ERASING AND/OR PROGRAMMING ONE OR MORE SECTORS
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Patent #:
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Issue Dt:
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09/20/2005
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Application #:
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10345129
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Filing Dt:
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01/14/2003
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Publication #:
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08/28/2003
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05/23/2006
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10360840
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09/18/2003
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12/06/2005
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10371154
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02/20/2003
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01/22/2004
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02/07/2006
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10371221
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02/21/2003
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09/25/2003
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03/08/2005
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10372626
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02/20/2003
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10/23/2003
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08/16/2005
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10372639
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02/20/2003
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11/20/2003
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05/08/2007
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10387141
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03/11/2003
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12/11/2003
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12/12/2006
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10390556
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03/14/2003
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11/13/2003
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NON-VOLATILE MEMORY DEVICE
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04/19/2005
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10406628
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04/02/2003
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01/15/2004
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07/26/2005
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10423845
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04/24/2003
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12/25/2003
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11/30/2004
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10426924
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04/29/2003
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12/25/2003
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04/05/2005
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10606164
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06/25/2003
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04/01/2004
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06/21/2005
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10608998
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06/26/2003
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04/22/2004
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12/28/2004
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10614693
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07/07/2003
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07/15/2004
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08/16/2005
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10616414
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07/08/2003
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04/01/2004
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06/12/2007
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10623474
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07/18/2003
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04/29/2004
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11/22/2005
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10651019
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08/28/2003
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03/31/2005
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08/09/2005
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09/02/2003
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05/12/2005
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02/15/2005
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10664606
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09/16/2003
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07/01/2004
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09/20/2005
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10675805
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09/30/2003
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11/11/2004
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01/24/2006
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10/07/2003
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07/08/2004
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11/14/2006
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10/07/2003
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08/05/2004
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07/26/2005
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10/15/2003
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07/22/2004
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04/11/2006
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11/20/2003
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07/15/2004
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09/27/2005
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12/03/2003
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07/15/2004
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06/27/2006
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12/05/2003
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09/02/2004
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05/22/2007
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12/12/2003
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09/16/2004
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01/13/2009
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12/18/2003
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09/09/2004
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10/24/2006
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10/14/2004
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04/26/2005
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12/30/2003
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02/24/2005
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04/25/2006
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12/30/2003
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09/02/2004
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05/24/2005
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12/30/2003
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10/14/2004
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10/24/2006
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12/29/2003
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10/21/2004
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07/11/2006
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01/20/2004
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11/18/2004
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10/10/2006
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02/17/2004
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11/11/2004
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02/26/2004
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11/25/2004
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05/30/2006
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04/08/2004
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12/23/2004
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02/28/2006
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06/04/2004
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02/24/2005
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12/26/2006
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07/16/2004
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03/03/2005
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09/18/2007
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08/06/2004
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02/10/2005
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11/14/2006
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08/06/2004
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08/14/2007
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10/22/2004
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02/13/2007
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11/25/2008
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