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Total properties:
77
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Patent #:
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11/15/2011
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11958578
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Filing Dt:
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12/18/2007
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Publication #:
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Pub Dt:
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06/19/2008
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Title:
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CAMERA HAVING A FOCUS ADJUSTING SYSTEM AND A FACE RECOGNITION FUNCTION
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Patent #:
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Issue Dt:
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02/01/2011
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Application #:
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12572568
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Filing Dt:
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10/02/2009
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Publication #:
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Pub Dt:
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01/28/2010
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING ALONG A PROFILE DISPOSED IN PERIPHERAL REGION AROUND THE DEVICE
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Patent #:
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Issue Dt:
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08/05/2014
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Application #:
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12572590
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Filing Dt:
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10/02/2009
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Publication #:
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Pub Dt:
|
06/17/2010
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Title:
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SEMICONDUCTOR DEVICE WITH A VERTICAL INTERCONNECT STRUCTURE FOR 3-D FO-WLCSP
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Patent #:
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Issue Dt:
|
04/12/2011
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Application #:
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12615428
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Filing Dt:
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11/10/2009
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|
Publication #:
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Pub Dt:
|
03/04/2010
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE DEVICE USING SACRIFICIAL CARRIER
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Patent #:
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Issue Dt:
|
12/28/2010
|
Application #:
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12627884
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Filing Dt:
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11/30/2009
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Publication #:
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Pub Dt:
|
03/25/2010
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING EMBEDDED PASSIVE CIRCUIT ELEMENTS INTERCONNECTED TO THROUGH HOLE VIAS
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Patent #:
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Issue Dt:
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12/20/2011
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Application #:
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12641958
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Filing Dt:
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12/18/2009
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|
Publication #:
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|
Pub Dt:
|
04/22/2010
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED-DOWN RDL AND RECESSED THV IN PERIPHERAL REGION OF THE DEVICE
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Patent #:
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Issue Dt:
|
04/14/2015
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Application #:
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12719398
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Filing Dt:
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03/08/2010
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Publication #:
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Pub Dt:
|
06/24/2010
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING RECESSED CONDUCTIVE VIAS IN SAW STREETS
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Patent #:
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Issue Dt:
|
09/03/2013
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Application #:
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12731330
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Filing Dt:
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03/25/2010
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Publication #:
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Pub Dt:
|
07/15/2010
| | | | |
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Title:
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FUSIBLE I/O INTERCONNECTION SYSTEMS AND METHODS FOR FLIP-CHIP PACKAGING INVOLVING SUBSTRATE-MOUNTED STUD BUMPS
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Patent #:
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Issue Dt:
|
06/05/2012
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Application #:
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12731354
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Filing Dt:
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03/25/2010
|
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Publication #:
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Pub Dt:
|
07/15/2010
| | | | |
|
Title:
|
FUSIBLE I/O INTERCONNECTION SYSTEMS AND METHODS FOR FLIP-CHIP PACKAGING INVOLVING SUBSTRATE-MOUNTED STUD BUMPS
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Patent #:
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Issue Dt:
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05/12/2015
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Application #:
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12775170
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Filing Dt:
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05/06/2010
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Publication #:
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Pub Dt:
|
09/02/2010
| | | | |
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Title:
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Semiconductor Device and Method of Forming an Interconnect Structure for 3-D Devices Using Encapsulant for Structural Support
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Patent #:
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Issue Dt:
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11/01/2011
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Application #:
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12775188
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Filing Dt:
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05/06/2010
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Publication #:
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Pub Dt:
|
08/26/2010
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR 3-D DEVICES USING ENCAPSULANT FOR STRUCTURAL SUPPORT
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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12775324
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Filing Dt:
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05/06/2010
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Publication #:
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Pub Dt:
|
08/26/2010
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH VIAS WITH REFLOWED CONDUCTIVE MATERIAL
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Patent #:
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Issue Dt:
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11/26/2013
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Application #:
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12775338
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Filing Dt:
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05/06/2010
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|
Publication #:
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Pub Dt:
|
08/26/2010
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH VIAS WITH REFLOWED CONDUCTIVE MATERIAL
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Patent #:
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Issue Dt:
|
08/23/2011
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Application #:
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12822080
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Filing Dt:
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06/23/2010
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Publication #:
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Pub Dt:
|
10/14/2010
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE FOR ENCAPSULATED DIE HAVING PRE-APPLIED PROTECTIVE LAYER
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Patent #:
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Issue Dt:
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02/07/2012
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Application #:
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12826368
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Filing Dt:
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06/29/2010
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Publication #:
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Pub Dt:
|
10/21/2010
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING HIGH-FREQUENCY CIRCUIT STRUCTURE AND METHOD THEREOF
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Patent #:
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Issue Dt:
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12/13/2011
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Application #:
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12830390
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Filing Dt:
|
07/05/2010
|
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Publication #:
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|
Pub Dt:
|
10/28/2010
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE HAVING ELECTRICAL DEVICES MOUNTED TO IPD STRUCTURE AND METHOD OF SHIELDING ELECTROMAGNETIC INTERFERENCE
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Patent #:
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Issue Dt:
|
10/15/2013
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Application #:
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12831047
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Filing Dt:
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07/06/2010
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Publication #:
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Pub Dt:
|
10/28/2010
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING ELECTROSTATIC DISCHARGE PROTECTION FOR INTEGRATED PASSIVE DEVICES
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Patent #:
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Issue Dt:
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04/24/2012
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Application #:
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12832821
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Filing Dt:
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07/08/2010
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Publication #:
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Pub Dt:
|
10/28/2010
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLARS IN RECESSED REGION OF PERIPHERAL AREA AROUND THE DEVICE FOR ELECTRICAL INTERCONNECTION TO OTHER DEVICES
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Patent #:
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Issue Dt:
|
05/07/2013
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Application #:
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12871401
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Filing Dt:
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08/30/2010
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|
Publication #:
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Pub Dt:
|
12/23/2010
| | | | |
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Title:
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Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-Up Interconnect Structure
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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12905825
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Filing Dt:
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10/15/2010
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Publication #:
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Pub Dt:
|
02/03/2011
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INTERPOSER PACKAGE WITH THROUGH SILICON VIAS
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Patent #:
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Issue Dt:
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05/08/2012
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Application #:
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12911042
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Filing Dt:
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10/25/2010
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Publication #:
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Pub Dt:
|
02/17/2011
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING A THERMAL DISSIPATION PATH THROUGH RDL AND CONDUCTIVE VIA
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Patent #:
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Issue Dt:
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07/17/2012
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Application #:
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12912467
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Filing Dt:
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10/26/2010
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Title:
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EMBEDDED SEMICONDUCTOR DIE PACKAGE AND METHOD OF MAKING THE SAME USING METAL FRAME CARRIER
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Patent #:
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Issue Dt:
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10/21/2014
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Application #:
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12941683
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Filing Dt:
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11/08/2010
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Publication #:
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Pub Dt:
|
03/03/2011
| | | | |
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Title:
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SEMICONDUCTOR DEVICE WITH OPTICAL SENSOR AND METHOD OF FORMING INTERCONNECT STRUCTURE ON FRONT AND BACKSIDE OF THE DEVICE
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Patent #:
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Issue Dt:
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06/05/2012
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Application #:
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12950591
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Filing Dt:
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11/19/2010
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Publication #:
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Pub Dt:
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03/24/2011
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Title:
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SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CORE STRUCTURE AND METHOD OF FORMING THE SAME
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Patent #:
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Issue Dt:
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02/28/2012
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Application #:
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13004111
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Filing Dt:
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01/11/2011
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Publication #:
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Pub Dt:
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05/05/2011
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Title:
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WAFER INTEGRATED WITH PERMANENT CARRIER AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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13019541
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Filing Dt:
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02/02/2011
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Publication #:
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Pub Dt:
|
05/26/2011
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING HOLES IN SUBSTRATE TO INTERCONNECT TOP SHIELD AND GROUND SHIELD
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Patent #:
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05/01/2012
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Application #:
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13019562
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Filing Dt:
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02/02/2011
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Publication #:
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Pub Dt:
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05/26/2011
| | | | |
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Title:
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SEMICONDUCTOR DEVICE HAVING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
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Patent #:
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Issue Dt:
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05/12/2015
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Application #:
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13090590
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04/20/2011
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Pub Dt:
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09/01/2011
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Title:
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SEMICONDUCTOR DEVICE HAVING IPD STRUCTURE WITH SMOOTH CONDUCTIVE LAYER AND BOTTOM-SIDE CONDUCTIVE LAYER
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08/06/2013
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13101657
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05/05/2011
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Publication #:
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Pub Dt:
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08/25/2011
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Title:
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WIREBONDLESS WAFER LEVEL PACKAGE WITH PLATED BUMPS AND INTERCONNECTS
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04/17/2012
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13155312
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06/07/2011
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Pub Dt:
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09/29/2011
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THREE-DIMENSIONAL VERTICALLY ORIENTED INTEGRATED CAPACITORS
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03/10/2015
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13170116
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06/27/2011
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10/20/2011
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Title:
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WAFER LEVEL DIE INTEGRATION AND METHOD THEREFOR
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05/20/2014
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13171341
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06/28/2011
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Pub Dt:
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10/20/2011
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Title:
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Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw Street
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Patent #:
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01/15/2013
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13174033
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06/30/2011
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Publication #:
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Pub Dt:
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10/20/2011
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Title:
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Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant
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Patent #:
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02/24/2015
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13181838
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07/13/2011
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Pub Dt:
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11/03/2011
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Title:
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Semiconductor Package with Penetrable Encapsulant Joining Semiconductor Die and Method Thereof
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01/08/2013
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13209620
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08/15/2011
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Publication #:
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Pub Dt:
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12/08/2011
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER AFTER ENCAPSULATION AND GROUNDED THROUGH INTERCONNECT STRUCTURE
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07/24/2012
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13212986
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08/18/2011
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Pub Dt:
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12/08/2011
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Title:
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APPARATUS FOR THERMALLY ENHANCED SEMICONDUCTOR PACKAGE
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Patent #:
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03/18/2014
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13218653
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08/26/2011
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Publication #:
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Pub Dt:
|
12/22/2011
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF SELF-CONFINEMENT OF CONDUCTIVE BUMP MATERIAL DURING REFLOW WITHOUT SOLDER MASK
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03/05/2013
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13219374
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08/26/2011
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Pub Dt:
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12/22/2011
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF INTEGRATING BALUN AND RF COUPLER ON A COMMON SUBSTRATE
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08/06/2013
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13228226
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09/08/2011
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Pub Dt:
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01/26/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF CONFORMING CONDUCTIVE VIAS BETWEEN INSULATING LAYERS IN SAW STREETS
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08/06/2013
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13228248
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09/08/2011
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Pub Dt:
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01/26/2012
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Title:
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SEMICONDUCTOR DEVICE WITH CONDUCTIVE VIAS BETWEEN SAW STREETS
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09/11/2012
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13241153
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09/22/2011
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01/26/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF DUAL-MOLDING DIE FORMED ON OPPOSITE SIDES OF BUILD-UP INTERCONNECT STRUCTURE
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02/25/2014
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13245099
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09/26/2011
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01/19/2012
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SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT STRUCTURE WITH TSV USING ENCAPSULANT FOR STRUCTURAL SUPPORT
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04/14/2015
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13248312
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09/29/2011
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09/06/2012
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Title:
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Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure
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01/27/2015
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13273537
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10/14/2011
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02/09/2012
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Title:
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Through Hole Vias at Saw Streets Including Protrusions or Recesses for Interconnection
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11/18/2014
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13312852
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12/06/2011
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Pub Dt:
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03/29/2012
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Title:
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Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Non-Linear Portions of Conductive Layers
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10/01/2013
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13335631
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12/22/2011
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Pub Dt:
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04/19/2012
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Title:
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SEMICONDUCTOR PACKAGE HAVING SEMICONDUCTOR DIE WITH INTERNAL VERTICAL INTERCONNECT STRUCTURE AND METHOD THEREFOR
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05/13/2014
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13335867
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12/22/2011
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Pub Dt:
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05/03/2012
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Title:
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Semiconductor Package Having Semiconductor Die with Internal Vertical Interconnect Structure and Method Therefor
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02/11/2014
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13339185
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12/28/2011
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Pub Dt:
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05/03/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF SHIELDING SEMICONDUCTOR DIE FROM INTER-DEVICE INTERFERENCE
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Issue Dt:
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10/28/2014
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13356485
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01/23/2012
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Pub Dt:
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05/17/2012
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Title:
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Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure
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12/03/2013
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13360549
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01/27/2012
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Publication #:
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Pub Dt:
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05/17/2012
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Title:
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SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIAS IN PERIPHERAL REGION CONNECTING SHIELDING LAYER TO GROUND
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Patent #:
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06/03/2014
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13405094
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02/24/2012
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Pub Dt:
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06/21/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING Z-INTERCONNECT CONDUCTIVE PILLARS WITH INNER POLYMER CORE
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Patent #:
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Issue Dt:
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11/19/2013
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Application #:
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13419242
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Filing Dt:
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03/13/2012
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Publication #:
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Pub Dt:
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07/05/2012
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Title:
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OPTICAL SEMICONDUCTOR DEVICE HAVING PRE-MOLDED LEADFRAME WITH WINDOW AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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07/02/2013
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Application #:
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13421770
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Filing Dt:
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03/15/2012
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Publication #:
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Pub Dt:
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07/05/2012
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Title:
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Semiconductor Device and Method of Forming With Three-Dimensional Vertically Oriented Integrated Capacitors
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Patent #:
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Issue Dt:
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01/08/2013
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Application #:
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13423263
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Filing Dt:
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03/18/2012
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Publication #:
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Pub Dt:
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07/12/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLARS IN RECESSED REGION OF PERIPHERAL AREA AROUND THE DEVICE FOR ELECTRICAL INTERCONNECTION TO OTHER DEVICES
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Patent #:
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Issue Dt:
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05/21/2013
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Application #:
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13423739
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Filing Dt:
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03/19/2012
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Publication #:
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Pub Dt:
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07/12/2012
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Title:
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SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CORE STRUCTURE AND METHOD OF FORMING SAME
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Patent #:
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Issue Dt:
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03/05/2013
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Application #:
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13431816
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Filing Dt:
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03/27/2012
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Publication #:
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Pub Dt:
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07/19/2012
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Title:
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METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
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Patent #:
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Issue Dt:
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02/25/2014
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Application #:
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13446741
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Filing Dt:
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04/13/2012
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Publication #:
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Pub Dt:
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08/09/2012
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Title:
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EMBEDDED SEMICONDUCTOR DIE PACKAGE AND METHOD OF MAKING THE SAME USING METAL FRAME CARRIER
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Patent #:
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Issue Dt:
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07/02/2013
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Application #:
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13476899
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Filing Dt:
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05/21/2012
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Publication #:
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Pub Dt:
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09/13/2012
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Title:
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Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
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Patent #:
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Issue Dt:
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10/15/2013
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Application #:
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13492646
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Filing Dt:
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06/08/2012
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Publication #:
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Pub Dt:
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09/27/2012
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Title:
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APPARATUS FOR THERMALLY ENHANCED SEMICONDUCTOR PACKAGE
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Patent #:
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Issue Dt:
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11/05/2013
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Application #:
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13492668
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Filing Dt:
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06/08/2012
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Publication #:
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Pub Dt:
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09/27/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING THERMALLY CONDUCTIVE LAYER IN INTERCONNECT STRUCTURE FOR HEAT DISSIPATION
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Patent #:
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Issue Dt:
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09/30/2014
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Application #:
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13555531
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Filing Dt:
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07/23/2012
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Publication #:
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Pub Dt:
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11/15/2012
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Title:
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Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die having Pre-Applied Protective Layer
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Patent #:
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Issue Dt:
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11/26/2013
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Application #:
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13559430
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Filing Dt:
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07/26/2012
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Publication #:
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Pub Dt:
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11/15/2012
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Title:
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Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure
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Patent #:
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Issue Dt:
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06/23/2015
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Application #:
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13566287
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Filing Dt:
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08/03/2012
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Publication #:
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Pub Dt:
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11/22/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING DIE WITH TSV IN CAVITY OF SUBSTRATE FOR ELECTRICAL INTERCONNECT OF FI-POP
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Patent #:
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Issue Dt:
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07/14/2015
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Application #:
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13572517
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Filing Dt:
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08/10/2012
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Publication #:
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Pub Dt:
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11/29/2012
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Title:
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Semicinductor Device with Cross-Talk Isolation Using M-CAP
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Patent #:
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Issue Dt:
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11/11/2014
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Application #:
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13606451
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Filing Dt:
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09/07/2012
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Publication #:
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Pub Dt:
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09/25/2014
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PIP WITH INNER KNOWN GOOD DIE INTERCONNECTED WITH CONDUCTIVE BUMPS
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Patent #:
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Issue Dt:
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09/16/2014
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Application #:
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13679792
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Filing Dt:
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11/16/2012
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Publication #:
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Pub Dt:
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03/28/2013
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING FO-WLCSP HAVING CONDUCTIVE LAYERS AND CONDUCTIVE VIAS SEPARATED BY POLYMER LAYERS
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Patent #:
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Issue Dt:
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12/09/2014
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Application #:
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13691440
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
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04/11/2013
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Title:
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Semiconductor Device and Method of Forming a Shielding Layer Between Stacked Semiconductor Die
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Patent #:
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Issue Dt:
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09/10/2013
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Application #:
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13706818
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Filing Dt:
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12/06/2012
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Publication #:
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Pub Dt:
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04/18/2013
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING AIR GAP ADJACENT TO STRESS SENSITIVE REGION OF THE DIE
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Patent #:
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Issue Dt:
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06/03/2014
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Application #:
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13727116
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Filing Dt:
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12/26/2012
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Publication #:
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Pub Dt:
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05/30/2013
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Title:
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SEMICONDUCTOR DEVICE HAVING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
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Patent #:
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Issue Dt:
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07/29/2014
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Application #:
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13845329
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Filing Dt:
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03/18/2013
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Publication #:
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Pub Dt:
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08/15/2013
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Title:
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Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-up Interconnect Structure
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Patent #:
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Issue Dt:
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06/03/2014
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Application #:
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13905845
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Filing Dt:
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05/30/2013
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Publication #:
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Pub Dt:
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10/10/2013
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF CONFINING CONDUCTIVE BUMP MATERIAL DURING REFLOW WITH SOLDER MASK PATCH
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Patent #:
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Issue Dt:
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01/20/2015
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Application #:
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13935312
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Filing Dt:
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07/03/2013
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Publication #:
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Pub Dt:
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11/07/2013
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SHIELDING LAYER OVER A SEMICONDUCTOR DIE DISPOSED IN A CAVITY OF AN INTERCONNECT STRUCTURE AND GROUNDED THROUGH THE DIE TSV
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Patent #:
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Issue Dt:
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06/02/2015
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Application #:
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14017963
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Filing Dt:
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09/04/2013
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Publication #:
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Pub Dt:
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01/02/2014
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Title:
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Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation
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Patent #:
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Issue Dt:
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03/10/2015
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Application #:
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14018282
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Filing Dt:
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09/04/2013
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Publication #:
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Pub Dt:
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01/02/2014
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Title:
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SEMICONDUCTOR DEVICE HAVING BALANCED BAND-PASS FILTER IMPLEMENTED WITH LC RESONATORS
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Patent #:
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Issue Dt:
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07/07/2015
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Application #:
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14063274
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Filing Dt:
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10/25/2013
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Publication #:
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Pub Dt:
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02/20/2014
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF DUAL-MOLDING DIE FORMED ON OPPOSITE SIDES OF BUILD-UP INTERCONNECT STRUCTURE
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Patent #:
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Issue Dt:
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06/09/2015
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Application #:
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14143891
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Filing Dt:
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12/30/2013
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Publication #:
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Pub Dt:
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04/24/2014
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Title:
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Semiconductor Device and Method of Making TSV Interconnect Structures Using Encapsulant for Structural Support
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Patent #:
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Issue Dt:
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11/11/2014
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Application #:
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14258300
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Filing Dt:
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04/22/2014
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Publication #:
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Pub Dt:
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08/14/2014
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Title:
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Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
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