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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	041741/0358			Pages:	8
		Recorded:	02/17/2017
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 84

Patent #:	5545581	Issue Dt:	08/13/1996	Application #:	08350445	Filing Dt:	12/06/1994
Title:	PLUG STRAP PROCESS UTILIZING SELECTIVE NITRIDE AND OXIDE ETCHES

Patent #:	5926359	Issue Dt:	07/20/1999	Application #:	08626310	Filing Dt:	04/01/1996
Title:	METAL-INSULATOR-METAL CAPACITOR

Patent #:	5990562	Issue Dt:	11/23/1999	Application #:	08806570	Filing Dt:	02/25/1997
Title:	SEMICONDUCTOR DEVICES HAVING BACKSIDE PROBING CAPABILITY

Patent #:	6150723	Issue Dt:	11/21/2000	Application #:	08941857	Filing Dt:	09/30/1997
Title:	COPPER STUD STRUCTURE WITH REFRACTORY METAL LINER

Patent #:	6078057	Issue Dt:	06/20/2000	Application #:	09010881	Filing Dt:	01/22/1998
Title:	SEMICONDUCTOR DEVICES HAVING BACKSIDE PROBING CAPABILITY

Patent #:	6097069	Issue Dt:	08/01/2000	Application #:	09102196	Filing Dt:	06/22/1998
Title:	METHOD AND STRUCTURE FOR INCREASING THE THRESHOLD VOLTAGE OF A CORNER DEVICE

Patent #:	6159807	Issue Dt:	12/12/2000	Application #:	09157691	Filing Dt:	09/21/1998
Title:	SELF-ALIGNED DYNAMIC THRESHOLD CMOS DEVICE

Patent #:	6268291	Issue Dt:	07/31/2001	Application #:	09204185	Filing Dt:	12/03/1998
Title:	METHOD FOR FORMING ELECTROMIGRATION-RESISTANT STRUCTURES BY DOPING

Patent #:	6635527	Issue Dt:	10/21/2003	Application #:	09318867	Filing Dt:	05/26/1999
Title:	METAL-INSULATOR-METAL CAPACITOR

Patent #:	6323128	Issue Dt:	11/27/2001	Application #:	09320499	Filing Dt:	05/26/1999
Title:	METHOD FOR FORMING CO-W-P-AU FILMS

Patent #:	6566759	Issue Dt:	05/20/2003	Application #:	09379453	Filing Dt:	08/23/1999
Title:	SELF-ALIGNED CONTACT AREAS FOR SIDEWALL IMAGE TRANSFER FORMED CONDUCTORS

Patent #:	6245587	Issue Dt:	06/12/2001	Application #:	09501920	Filing Dt:	02/10/2000
Title:	METHOD FOR MAKING SEMICONDUCTOR DEVICES HAVING BACKSIDE PROBING CAPABILITY

Patent #:	6365328	Issue Dt:	04/02/2002	Application #:	09522883	Filing Dt:	03/10/2000
Title:	SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD

Patent #:	6300657	Issue Dt:	10/09/2001	Application #:	09536503	Filing Dt:	03/27/2000
Title:	SELF-ALIGNED DYNAMIC THRESHOLD CMOS DEVICE

Patent #:	6300236	Issue Dt:	10/09/2001	Application #:	09553581	Filing Dt:	04/20/2000
Title:	COPPER STUD STRUCTURE WITH REFRACTORY METAL LINER

Patent #:	6303450	Issue Dt:	10/16/2001	Application #:	09717971	Filing Dt:	11/21/2000
Title:	Novel CMOS device structures and method of making same

Patent #:	6452209	Issue Dt:	09/17/2002	Application #:	09771778	Filing Dt:	01/29/2001
Publication #:	US20010006233	Pub Dt:	07/05/2001
Title:	SEMICONDUCTOR DEVICES HAVING BACKSIDE PROBING CAPABILITY

Patent #:	6943451	Issue Dt:	09/13/2005	Application #:	09897200	Filing Dt:	07/02/2001
Publication #:	US20030001240	Pub Dt:	01/02/2003
Title:	SEMICONDUCTOR DEVICES CONTAINING A DISCONTINUOUS CAP LAYER AND METHODS FOR FORMING SAME

Patent #:	6512266	Issue Dt:	01/28/2003	Application #:	09902830	Filing Dt:	07/11/2001
Publication #:	US20030011080	Pub Dt:	01/16/2003
Title:	METHOD OF FABRICATING SIO2 SPACERS AND ANNEALING CAPS

Patent #:	6570256	Issue Dt:	05/27/2003	Application #:	09910380	Filing Dt:	07/20/2001
Publication #:	US20030017642	Pub Dt:	01/23/2003
Title:	CARBON-GRADED LAYER FOR IMPROVED ADHESION OF LOW-K DIELECTRICS TO SILICON SUBSTRATES

Patent #:	6589874	Issue Dt:	07/08/2003	Application #:	09915932	Filing Dt:	07/26/2001
Publication #:	US20020115292	Pub Dt:	08/22/2002
Title:	METHOD FOR FORMING ELECTROMIGRATION-RESISTANT STRUCTURES BY DOPING

Patent #:	6646345	Issue Dt:	11/11/2003	Application #:	09966629	Filing Dt:	09/27/2001
Publication #:	US20020123220	Pub Dt:	09/05/2002
Title:	METHOD FOR FORMING CO-W-P-AU FILMS

Patent #:	6559543	Issue Dt:	05/06/2003	Application #:	09991769	Filing Dt:	11/16/2001
Publication #:	US20030094696	Pub Dt:	05/22/2003
Title:	STACKED FILL STRUCTURES FOR SUPPORT OF DIELECTRIC LAYERS

Patent #:	6653698	Issue Dt:	11/25/2003	Application #:	10034009	Filing Dt:	12/20/2001
Publication #:	US20030119292	Pub Dt:	06/26/2003
Title:	INTEGRATION OF DUAL WORKFUNCTION METAL GATE CMOS DEVICES

Patent #:	6518670	Issue Dt:	02/11/2003	Application #:	10091643	Filing Dt:	03/06/2002
Title:	ELECTRICALLY POROUS ON-CHIP DECOUPLING/SHIELDING LAYER

Patent #:	6690072	Issue Dt:	02/10/2004	Application #:	10156782	Filing Dt:	05/24/2002
Publication #:	US20030219965	Pub Dt:	11/27/2003
Title:	METHOD AND STRUCTURE FOR ULTRA-LOW CONTACT RESISTANCE CMOS FORMED BY VERTICALLY SELF-ALIGNED COSI2 ON RAISED SOURCE DRAIN SI/SIGE DEVICE

Patent #:	6909147	Issue Dt:	06/21/2005	Application #:	10249738	Filing Dt:	05/05/2003
Publication #:	US20040222477	Pub Dt:	11/11/2004
Title:	MULTI-HEIGHT FINFETS

Patent #:	6806584	Issue Dt:	10/19/2004	Application #:	10277907	Filing Dt:	10/21/2002
Publication #:	US20040075151	Pub Dt:	04/22/2004
Title:	SEMICONDUCTOR DEVICE STRUCTURE INCLUDING MULTIPLE FETS HAVING DIFFERENT SPACER WIDTHS

Patent #:	6630395	Issue Dt:	10/07/2003	Application #:	10280266	Filing Dt:	10/24/2002
Title:	METHODS FOR FABRICATING ELECTRICAL CONNECTIONS TO SEMICONDUCTOR STRUCTURES INCORPORATING LOW-K DIELECTRIC MATERIALS

Patent #:	6774000	Issue Dt:	08/10/2004	Application #:	10300239	Filing Dt:	11/20/2002
Publication #:	US20040097047	Pub Dt:	05/20/2004
Title:	METHOD OF MANUFACTURE OF MOSFET DEVICE WITH IN-SITU DOPED, RAISED SOURCE AND DRAIN STRUCTURES

Patent #:	6825529	Issue Dt:	11/30/2004	Application #:	10318602	Filing Dt:	12/12/2002
Publication #:	US20040113217	Pub Dt:	06/17/2004
Title:	STRESS INDUCING SPACERS

Patent #:	7041748	Issue Dt:	05/09/2006	Application #:	10338945	Filing Dt:	01/08/2003
Publication #:	US20040137241	Pub Dt:	07/15/2004
Title:	PATTERNABLE LOW DIELECTRIC CONSTSNT MATERIALS AND THEIR USE IN ULSI INTERCONNECTION

Patent #:	6743710	Issue Dt:	06/01/2004	Application #:	10345441	Filing Dt:	01/15/2003
Publication #:	US20030141598	Pub Dt:	07/31/2003
Title:	STACKED FILL STRUCTURES FOR SUPPORT OF DIELECTRIC LAYERS

Patent #:	6949458	Issue Dt:	09/27/2005	Application #:	10361228	Filing Dt:	02/10/2003
Publication #:	US20030115750	Pub Dt:	06/26/2003
Title:	SELF-ALIGNED CONTACT AREAS FOR SIDEWALL IMAGE TRANSFER FORMED CONDUCTORS

Patent #:	6740539	Issue Dt:	05/25/2004	Application #:	10366149	Filing Dt:	02/13/2003
Publication #:	US20030153198	Pub Dt:	08/14/2003
Title:	CARBON-GRADED LAYER FOR IMPROVED ADHESION OF LOW-K DIELECTRICS TO SILICON SUBSTRATES

Patent #:	6972250	Issue Dt:	12/06/2005	Application #:	10419888	Filing Dt:	04/22/2003
Publication #:	US20030219971	Pub Dt:	11/27/2003
Title:	Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device

Patent #:	7352025	Issue Dt:	04/01/2008	Application #:	10596029	Filing Dt:	05/25/2006
Publication #:	US20070085134	Pub Dt:	04/19/2007
Title:	SEMICONDUCTOR MEMORY DEVICE WITH INCREASED NODE CAPACITANCE

Patent #:	6958540	Issue Dt:	10/25/2005	Application #:	10604026	Filing Dt:	06/23/2003
Publication #:	US20040262764	Pub Dt:	12/30/2004
Title:	DUAL DAMASCENE INTERCONNECT STRUCTURES HAVING DIFFERENT MATERIALS FOR LINE AND VIA CONDUCTORS

Patent #:	6911383	Issue Dt:	06/28/2005	Application #:	10604097	Filing Dt:	06/26/2003
Publication #:	US20040266076	Pub Dt:	12/30/2004
Title:	HYBRID PLANAR AND FINFET CMOS DEVICES

Patent #:	7279746	Issue Dt:	10/09/2007	Application #:	10604190	Filing Dt:	06/30/2003
Publication #:	US20040262784	Pub Dt:	12/30/2004
Title:	HIGH PERFORMANCE CMOS DEVICE STRUCTURES AND METHOD OF MANUFACTURE

Patent #:	6991979	Issue Dt:	01/31/2006	Application #:	10605311	Filing Dt:	09/22/2003
Publication #:	US20050064635	Pub Dt:	03/24/2005
Title:	METHOD FOR AVOIDING OXIDE UNDERCUT DURING PRE-SILICIDE CLEAN FOR THIN SPACER FETS

Patent #:	6888224	Issue Dt:	05/03/2005	Application #:	10609784	Filing Dt:	06/30/2003
Title:	METHODS AND SYSTEMS FOR FABRICATING ELECTRICAL CONNECTIONS TO SEMICONDUCTOR STRUCTURES INCORPORATING LOW-K DIELECTRIC MATERIALS

Patent #:	6927440	Issue Dt:	08/09/2005	Application #:	10658036	Filing Dt:	09/09/2003
Publication #:	US20050037568	Pub Dt:	02/17/2005
Title:	METAL-INSULATOR-METAL CAPACITOR

Patent #:	7303949	Issue Dt:	12/04/2007	Application #:	10689506	Filing Dt:	10/20/2003
Publication #:	US20050082616	Pub Dt:	04/21/2005
Title:	HIGH PERFORMANCE STRESS-ENHANCED MOSFETS USING SI:C AND SIGE EPITAXIAL SOURCE/DRAIN AND METHOD OF MANUFACTURE

Patent #:	7018916	Issue Dt:	03/28/2006	Application #:	10698483	Filing Dt:	11/03/2003
Publication #:	US20050095837	Pub Dt:	05/05/2005
Title:	STRUCTURE AND METHOD FOR FORMING A DIELECTRIC CHAMBER AND ELECTRONIC DEVICE INCLUDING THE DIELECTRIC CHAMBER

Patent #:	7169698	Issue Dt:	01/30/2007	Application #:	10707811	Filing Dt:	01/14/2004
Publication #:	US20050153505	Pub Dt:	07/14/2005
Title:	SACRIFICIAL INORGANIC POLYMER INTERMETAL DIELECTRIC DAMASCENE WIRE AND VIA LINER

Patent #:	7381609	Issue Dt:	06/03/2008	Application #:	10707841	Filing Dt:	01/16/2004
Publication #:	US20050158937	Pub Dt:	07/21/2005
Title:	METHOD AND STRUCTURE FOR CONTROLLING STRESS IN A TRANSISTOR CHANNEL

Patent #:	7384829	Issue Dt:	06/10/2008	Application #:	10710608	Filing Dt:	07/23/2004
Publication #:	US20060019462	Pub Dt:	01/26/2006
Title:	PATTERNED STRAINED SEMICONDUCTOR SUBSTRATE AND DEVICE

Patent #:	6951784	Issue Dt:	10/04/2005	Application #:	10710822	Filing Dt:	08/05/2004
Title:	THREE-MASK METHOD OF CONSTRUCTING THE FINAL HARD MASK USED FOR ETCHING THE SILICON FINS FOR FINFETS

Patent #:	7176119	Issue Dt:	02/13/2007	Application #:	10711456	Filing Dt:	09/20/2004
Publication #:	US20060063373	Pub Dt:	03/23/2006
Title:	METHOD OF FABRICATING COPPER DAMASCENE AND DUAL DAMASCENE INTERCONNECT WIRING

Patent #:	6946709	Issue Dt:	09/20/2005	Application #:	10726326	Filing Dt:	12/02/2003
Publication #:	US20050116296	Pub Dt:	06/02/2005
Title:	COMPLEMENTARY TRANSISTORS HAVING DIFFERENT SOURCE AND DRAIN EXTENSION SPACING CONTROLLED BY DIFFERENT SPACER SIZES

Patent #:	7056782	Issue Dt:	06/06/2006	Application #:	10786901	Filing Dt:	02/25/2004
Publication #:	US20050186747	Pub Dt:	08/25/2005
Title:	CMOS SILICIDE METAL GATE INTEGRATION

Patent #:	7002209	Issue Dt:	02/21/2006	Application #:	10851830	Filing Dt:	05/21/2004
Publication #:	US20050260808	Pub Dt:	11/24/2005
Title:	MOSFET STRUCTURE WITH HIGH MECHANICAL STRESS IN THE CHANNEL

Patent #:	7105889	Issue Dt:	09/12/2006	Application #:	10863830	Filing Dt:	06/04/2004
Publication #:	US20050269634	Pub Dt:	12/08/2005
Title:	SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH K DIELECTRICS

Patent #:	6858903	Issue Dt:	02/22/2005	Application #:	10881449	Filing Dt:	06/30/2004
Publication #:	US20040248368	Pub Dt:	12/09/2004
Title:	MOSFET DEVICE WITH IN-SITU DOPED, RAISED SOURCE AND DRAIN STRUCTURES

Patent #:	7374987	Issue Dt:	05/20/2008	Application #:	10935136	Filing Dt:	09/07/2004
Publication #:	US20050040460	Pub Dt:	02/24/2005
Title:	STRESS INDUCING SPACERS

Patent #:	7479683	Issue Dt:	01/20/2009	Application #:	10957342	Filing Dt:	10/01/2004
Publication #:	US20050269635	Pub Dt:	12/08/2005
Title:	SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH-K DIELECTRICS

Patent #:	7250658	Issue Dt:	07/31/2007	Application #:	11122193	Filing Dt:	05/04/2005
Publication #:	US20050263831	Pub Dt:	12/01/2005
Title:	HYBRID PLANAR AND FINFET CMOS DEVICES

Patent #:	7307011	Issue Dt:	12/11/2007	Application #:	11129325	Filing Dt:	05/16/2005
Publication #:	US20050199977	Pub Dt:	09/15/2005
Title:	STRUCTURE AND METHOD FOR FORMING A DIELECTRIC CHAMBER AND ELECTRONIC DEVICE INCLUDING THE DIELECTRIC CHAMBER

Patent #:	7669159	Issue Dt:	02/23/2010	Application #:	11160339	Filing Dt:	06/20/2005
Publication #:	US20050273744	Pub Dt:	12/08/2005
Title:	IC TILING PATTERN METHOD, IC SO FORMED AND ANALYSIS METHOD

Patent #:	7300867	Issue Dt:	11/27/2007	Application #:	11174985	Filing Dt:	07/05/2005
Publication #:	US20050245068	Pub Dt:	11/03/2005
Title:	DUAL DAMASCENE INTERCONNECT STRUCTURES HAVING DIFFERENT MATERIALS FOR LINE AND VIA CONDUCTORS

Patent #:	7572692	Issue Dt:	08/11/2009	Application #:	11191426	Filing Dt:	07/27/2005
Publication #:	US20050263826	Pub Dt:	12/01/2005
Title:	COMPLEMENTARY TRANSISTORS HAVING DIFFERENT SOURCE AND DRAIN EXTENSION SPACING CONTROLLED BY DIFFERENT SPACER SIZES

Patent #:	7091128	Issue Dt:	08/15/2006	Application #:	11266855	Filing Dt:	11/04/2005
Publication #:	US20060057797	Pub Dt:	03/16/2006
Title:	METHOD FOR AVOIDING OXIDE UNDERCUT DURING PRE-SILICIDE CLEAN FOR THIN SPACER FETS

Patent #:	7306853	Issue Dt:	12/11/2007	Application #:	11314307	Filing Dt:	12/21/2005
Publication #:	US20060105181	Pub Dt:	05/18/2006
Title:	PATTERNABLE LOW DIELECTRIC CONSTANT MATERIALS AND THEIR USE IN ULSI INTERCONNECTION

Patent #:	7411227	Issue Dt:	08/12/2008	Application #:	11407313	Filing Dt:	04/19/2006
Publication #:	US20060189061	Pub Dt:	08/24/2006
Title:	CMOS SILICIDE METAL GATE INTEGRATION

Patent #:	7452767	Issue Dt:	11/18/2008	Application #:	11500254	Filing Dt:	08/07/2006
Publication #:	US20060275977	Pub Dt:	12/07/2006
Title:	SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH K DIELECTRICS

Patent #:	7678683	Issue Dt:	03/16/2010	Application #:	11555383	Filing Dt:	11/01/2006
Publication #:	US20070059920	Pub Dt:	03/15/2007
Title:	METHOD OF FABRICATING COPPER DAMASCENE AND DUAL DAMASCENE INTERCONNECT WIRING

Patent #:	7288475	Issue Dt:	10/30/2007	Application #:	11558959	Filing Dt:	11/13/2006
Publication #:	US20070087551	Pub Dt:	04/19/2007
Title:	SACRIFICIAL INORGANIC POLYMER INTERMETAL DIELECTRIC DAMASCENE WIRE AND VIA LINER

Patent #:	7704876	Issue Dt:	04/27/2010	Application #:	11847657	Filing Dt:	08/30/2007
Publication #:	US20080026566	Pub Dt:	01/31/2008
Title:	DUAL DAMASCENE INTERCONNECT STRUCTURES HAVING DIFFERENT MATERIALS FOR LINE AND VIA CONDUCTORS

Patent #:	8901566	Issue Dt:	12/02/2014	Application #:	11848268	Filing Dt:	08/31/2007
Publication #:	US20070296038	Pub Dt:	12/27/2007
Title:	HIGH PERFORMANCE STRESS-ENHANCED MOSFETS USING SI:C AND SIGE EPITAXIAL SOURCE/DRAIN AND METHOD OF MANUFACTURE

Patent #:	7436029	Issue Dt:	10/14/2008	Application #:	11867271	Filing Dt:	10/04/2007
Publication #:	US20080026522	Pub Dt:	01/31/2008
Title:	HIGH PERFORMANCE CMOS DEVICE STRUCTURES AND METHOD OF MANUFACTURE

Patent #:	7847409	Issue Dt:	12/07/2010	Application #:	11873300	Filing Dt:	10/16/2007
Publication #:	US20080036092	Pub Dt:	02/14/2008
Title:	SACRIFICIAL INORGANIC POLYMER INTERMETAL DIELECTRIC DAMASCENE WIRE AND VIA LINER

Patent #:	7682859	Issue Dt:	03/23/2010	Application #:	11931836	Filing Dt:	10/31/2007
Publication #:	US20080061317	Pub Dt:	03/13/2008
Title:	PATTERNED STRAINED SEMICONDUCTOR SUBSTRATE AND DEVICE

Patent #:	7714079	Issue Dt:	05/11/2010	Application #:	11933530	Filing Dt:	11/01/2007
Publication #:	US20080063880	Pub Dt:	03/13/2008
Title:	PATTERNABLE LOW DIELECTRIC CONSTANT MATERIALS AND THEIR USE IN ULSI INTERCONNECTION

Patent #:	9515140	Issue Dt:	12/06/2016	Application #:	12015272	Filing Dt:	01/16/2008
Publication #:	US20080135874	Pub Dt:	06/12/2008
Title:	PATTERNED STRAINED SEMICONDUCTOR SUBSTRATE AND DEVICE

Patent #:	9006836	Issue Dt:	04/14/2015	Application #:	12104526	Filing Dt:	04/17/2008
Publication #:	US20080217696	Pub Dt:	09/11/2008
Title:	METHOD AND STRUCTURE FOR CONTROLLING STRESS IN A TRANSISTOR CHANNEL

Patent #:	7655557	Issue Dt:	02/02/2010	Application #:	12145113	Filing Dt:	06/24/2008
Publication #:	US20080254622	Pub Dt:	10/16/2008
Title:	CMOS SILICIDE METAL GATE INTEGRATION

Patent #:	7745278	Issue Dt:	06/29/2010	Application #:	12211530	Filing Dt:	09/16/2008
Publication #:	US20090011610	Pub Dt:	01/08/2009
Title:	SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE TRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH K DIELECTRICS

Patent #:	7928514	Issue Dt:	04/19/2011	Application #:	12355368	Filing Dt:	01/16/2009
Publication #:	US20090152642	Pub Dt:	06/18/2009
Title:	SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH-K DIELECTRICS

Patent #:	8106513	Issue Dt:	01/31/2012	Application #:	12614861	Filing Dt:	11/09/2009
Publication #:	US20100052172	Pub Dt:	03/04/2010
Title:	COPPER DAMASCENE AND DUAL DAMASCENE INTERCONNECT WIRING

Patent #:	9053970	Issue Dt:	06/09/2015	Application #:	12686040	Filing Dt:	01/12/2010
Publication #:	US20100109049	Pub Dt:	05/06/2010
Title:	PATTERNED STRAINED SEMICONDUCTOR SUBSTRATE AND DEVICE

Patent #:	8053901	Issue Dt:	11/08/2011	Application #:	12917154	Filing Dt:	11/01/2010
Publication #:	US20110042826	Pub Dt:	02/24/2011
Title:	SACRIFICIAL INORGANIC POLYMER INTERMETAL DIELECTRIC DAMASCENE WIRE AND VIA LINER

Patent #:	8193051	Issue Dt:	06/05/2012	Application #:	13047172	Filing Dt:	03/14/2011
Publication #:	US20110165767	Pub Dt:	07/07/2011
Title:	SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH-K DIELECTRICS

Patent #:	8349728	Issue Dt:	01/08/2013	Application #:	13301837	Filing Dt:	11/22/2011
Publication #:	US20120064718	Pub Dt:	03/15/2012
Title:	METHOD OF FABRICATING COPPER DAMASCENE AND DUAL DAMASCENE INTERCONNECT WIRING

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

12/07/2016

Assignee

AURIGA INNOVATIONS, INC.

303 TERRY FOX DRIVE

SUITE 300

OTTAWA, CANADA K2K 3J1

Correspondence name and address
	AURIGA INNOVATIONS, INC.
	303 TERRY FOX DRIVE
	SUITE 300
	OTTAWA, K2K 3J1 CANADA

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