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Patent Assignment Details
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Reel/Frame:009662/0361   Pages: 10
Recorded: 08/17/1998
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 16
1
Patent #:
Issue Dt:
08/29/1989
Application #:
07147843
Filing Dt:
01/25/1988
Title:
PROCESS FOR MAKING A HIGH DENSITY SPLIT GATE NONVOLATILE MEMORY CELL
2
Patent #:
Issue Dt:
01/16/1990
Application #:
07151379
Filing Dt:
02/02/1988
Title:
NONVOLATILE MEMORY CELL FOR EEPROM INCLUDING A FLOATING GATE TO DRAIN TUNNEL AREA POSITIONED AWAY FROM THE CHANNEL REGION TO PREVENT TRAPPING OF ELECTRONS IN THE GATE OXIDE DURING CELL ERASE
3
Patent #:
Issue Dt:
03/07/1989
Application #:
07173954
Filing Dt:
03/28/1988
Title:
CMOS RECTIFIER CIRCUIT
4
Patent #:
Issue Dt:
07/16/1991
Application #:
07179196
Filing Dt:
04/08/1988
Title:
HIGH DENSITY EEPROM CELL AND PROCESS FOR MAKING THE CELL
5
Patent #:
Issue Dt:
08/14/1990
Application #:
07192580
Filing Dt:
05/11/1988
Title:
EEPROM UTILIZING SINGLE TRANSISTOR PER CELL CAPABLE OF BOTH BYTE ERASE AND FLASH ERASE
6
Patent #:
Issue Dt:
02/20/1990
Application #:
07227584
Filing Dt:
08/02/1988
Title:
DIFFERENTIAL SENSE AMPLIFIER CIRCUIT FOR HIGH SPEED EPROMS, AND FLASH MEMORY DEVICES
7
Patent #:
Issue Dt:
04/06/1993
Application #:
07602999
Filing Dt:
10/24/1990
Title:
REDUNDANCY CIRCUIT FOR HIGH SPEED EPROM AND FLASH MEMORY DEVICES
8
Patent #:
Issue Dt:
06/08/1993
Application #:
07637405
Filing Dt:
01/04/1991
Title:
POWER STEALING CIRCUIT
9
Patent #:
Issue Dt:
02/09/1993
Application #:
07658279
Filing Dt:
02/19/1991
Title:
MEMORY ARRAY ARCHITECTURE FOR FLASH MEMORY
10
Patent #:
Issue Dt:
06/01/1993
Application #:
07837172
Filing Dt:
02/14/1992
Title:
CHARGE PUMP WITH HIGH OUTPUT CURRENT
11
Patent #:
Issue Dt:
05/17/1994
Application #:
07837303
Filing Dt:
02/14/1992
Title:
MEMORY CIRCUIT WITH PUMPED VOLTAGE FOR ERASE AND PROGRAM OPERATIONS
12
Patent #:
Issue Dt:
03/21/1995
Application #:
08107479
Filing Dt:
08/17/1993
Title:
SELF-RECOVERING ERASE SCHEME TO ENHANCE FLASH MEMORY ENDURANCE
13
Patent #:
Issue Dt:
08/06/1996
Application #:
08307998
Filing Dt:
09/16/1994
Title:
CHARGE STACKING ON-CHIP HIGH-VOLTAGE GENERATOR AND METHOD
14
Patent #:
Issue Dt:
05/21/1996
Application #:
08336886
Filing Dt:
11/10/1994
Title:
STRUCTURE AND METHOD FOR IMPROVED MEMORY ARRAYS AND IMPROVED ELECTRICAL CONTACTS IN SEMICONDUCTOR DEVICES
15
Patent #:
Issue Dt:
08/20/1996
Application #:
08409779
Filing Dt:
03/24/1995
Title:
NEGATIVE VOLTAGE DECODING IN NON-VOLATILE MEMORIES
16
Patent #:
Issue Dt:
06/09/1998
Application #:
08729009
Filing Dt:
10/10/1996
Title:
INTERMEDIATE SIZE NON-VOLATILE ELECTRICALLY ALTERABLE SEMICONDUCTOR MEMORY DEVICE
Assignor
1
Exec Dt:
07/31/1998
Assignee
1
12121 WILSHIRE BLVD.
LOS ANGELES, CALIFORNIA 90025
Correspondence name and address
BUCHALTER, NEMER, FIELDS & YOUNGER
MR. SIGI HINOJOSA, PARALEGAL
601 SO. FIGUEROA ST., STE. 2400
LOS ANGELES, CA 90017

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