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Reel/Frame:064803/0368   Pages: 19
Recorded: 09/01/2023
Attorney Dkt #:392739-00007
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE." TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0227. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.
Total properties: 61
1
Patent #:
8698294
Issue Dt:
04/15/2014
Application #:
11307129
Filing Dt:
01/24/2006
Publication #:
US20070170570
Pub Dt:
07/26/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING WIDE FLANGE LEADFRAME
2
Patent #:
8704349
Issue Dt:
04/22/2014
Application #:
11354806
Filing Dt:
02/14/2006
Publication #:
US20070190690
Pub Dt:
08/16/2007
Title:
Integrated circuit package system with exposed interconnects
3
Patent #:
8669637
Issue Dt:
03/11/2014
Application #:
11553949
Filing Dt:
10/27/2006
Publication #:
US20070114634
Pub Dt:
05/24/2007
Title:
INTEGRATED PASSIVE DEVICE SYSTEM
4
Patent #:
8710675
Issue Dt:
04/29/2014
Application #:
11677477
Filing Dt:
02/21/2007
Publication #:
US20070194462
Pub Dt:
08/23/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH BONDING LANDS
5
Patent #:
8709934
Issue Dt:
04/29/2014
Application #:
11758635
Filing Dt:
06/05/2007
Publication #:
US20080303142
Pub Dt:
12/11/2008
Title:
ELECTRONIC SYSTEM WITH VERTICAL INTERMETALLIC COMPOUND
6
Patent #:
8659175
Issue Dt:
02/25/2014
Application #:
11762055
Filing Dt:
06/12/2007
Publication #:
US20070296086
Pub Dt:
12/27/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACK
7
Patent #:
8643157
Issue Dt:
02/04/2014
Application #:
11766771
Filing Dt:
06/21/2007
Publication #:
US20080315380
Pub Dt:
12/25/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING PERIMETER PADDLE
8
Patent #:
8722457
Issue Dt:
05/13/2014
Application #:
11965383
Filing Dt:
12/27/2007
Publication #:
US20090166825
Pub Dt:
07/02/2009
Title:
SYSTEM AND APPARATUS FOR WAFER LEVEL INTEGRATION OF COMPONENTS
9
Patent #:
8685792
Issue Dt:
04/01/2014
Application #:
12040558
Filing Dt:
02/29/2008
Publication #:
US20080211084
Pub Dt:
09/04/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERPOSER
10
Patent #:
8652881
Issue Dt:
02/18/2014
Application #:
12235288
Filing Dt:
09/22/2008
Publication #:
US20100072591
Pub Dt:
03/25/2010
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ANTI-PEEL CONTACT PADS
11
Patent #:
8664038
Issue Dt:
03/04/2014
Application #:
12328759
Filing Dt:
12/04/2008
Publication #:
US20100140763
Pub Dt:
06/10/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED PADDLE AND METHOD OF MANUFACTURE THEREOF
12
Patent #:
8723302
Issue Dt:
05/13/2014
Application #:
12333298
Filing Dt:
12/11/2008
Publication #:
US20100148344
Pub Dt:
06/17/2010
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INPUT/OUTPUT EXPANSION
13
Patent #:
8643163
Issue Dt:
02/04/2014
Application #:
12371730
Filing Dt:
02/16/2009
Publication #:
US20090146315
Pub Dt:
06/11/2009
Title:
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM AND METHOD OF MANUFACTURE THEREOF
14
Patent #:
8710634
Issue Dt:
04/29/2014
Application #:
12410945
Filing Dt:
03/25/2009
Publication #:
US20100244222
Pub Dt:
09/30/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STRUCTURE AND METHOD OF MANUFACTURE THEREOF
15
Patent #:
8729693
Issue Dt:
05/20/2014
Application #:
12565144
Filing Dt:
09/23/2009
Publication #:
US20110068458
Pub Dt:
03/24/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A LEADED PACKAGE AND METHOD OF MANUFACTURE THEREOF
16
Patent #:
8653654
Issue Dt:
02/18/2014
Application #:
12639990
Filing Dt:
12/16/2009
Publication #:
US20110140283
Pub Dt:
06/16/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A STACKABLE PACKAGE AND METHOD OF MANUFACTURE THEREOF
17
Patent #:
8716853
Issue Dt:
05/06/2014
Application #:
12704345
Filing Dt:
02/11/2010
Publication #:
US20100140799
Pub Dt:
06/10/2010
Title:
Extended Redistribution Layers Bumped Wafer
18
Patent #:
8643181
Issue Dt:
02/04/2014
Application #:
12730989
Filing Dt:
03/24/2010
Publication #:
US20110233751
Pub Dt:
09/29/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
19
Patent #:
8669649
Issue Dt:
03/11/2014
Application #:
12890491
Filing Dt:
09/24/2010
Publication #:
US20120074548
Pub Dt:
03/29/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERLOCK AND METHOD OF MANUFACTURE THEREOF
20
Patent #:
8704366
Issue Dt:
04/22/2014
Application #:
12911592
Filing Dt:
10/25/2010
Publication #:
US20110037172
Pub Dt:
02/17/2011
Title:
Ultra Thin Bumped Wafer With Under-Film
21
Patent #:
8723324
Issue Dt:
05/13/2014
Application #:
12961489
Filing Dt:
12/06/2010
Publication #:
US20120139104
Pub Dt:
06/07/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF
22
Patent #:
8659172
Issue Dt:
02/25/2014
Application #:
12963919
Filing Dt:
12/09/2010
Publication #:
US20120211882
Pub Dt:
08/23/2012
Title:
Semiconductor Device and Method of Confining Conductive Bump Material with Solder Mask Patch
23
Patent #:
8709932
Issue Dt:
04/29/2014
Application #:
12966071
Filing Dt:
12/13/2010
Publication #:
US20120146230
Pub Dt:
06/14/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
24
Patent #:
8692377
Issue Dt:
04/08/2014
Application #:
13069744
Filing Dt:
03/23/2011
Publication #:
US20120241966
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLATED LEADS AND METHOD OF MANUFACTURE THEREOF
25
Patent #:
8658470
Issue Dt:
02/25/2014
Application #:
13102052
Filing Dt:
05/05/2011
Publication #:
US20120280408
Pub Dt:
11/08/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
26
Patent #:
8692365
Issue Dt:
04/08/2014
Application #:
13163611
Filing Dt:
06/17/2011
Publication #:
US20120319267
Pub Dt:
12/20/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL DISPERSAL STRUCTURES AND METHOD OF MANUFACTURE THEREOF
27
Patent #:
8674516
Issue Dt:
03/18/2014
Application #:
13166802
Filing Dt:
06/22/2011
Publication #:
US20120326331
Pub Dt:
12/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
28
Patent #:
8697490
Issue Dt:
04/15/2014
Application #:
13175694
Filing Dt:
07/01/2011
Publication #:
US20110260321
Pub Dt:
10/27/2011
Title:
FLIP CHIP INTERCONNECTION STRUCTURE
29
Patent #:
8704365
Issue Dt:
04/22/2014
Application #:
13187252
Filing Dt:
07/20/2011
Publication #:
US20110272807
Pub Dt:
11/10/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING A CAVITY
30
Patent #:
8648469
Issue Dt:
02/11/2014
Application #:
13191386
Filing Dt:
07/26/2011
Publication #:
US20110278721
Pub Dt:
11/17/2011
Title:
SEMICONDUCTOR PACKAGE AND METHOD OF MOUNTING SEMICONDUCTOR DIE TO OPPOSITE SIDES OF TSV SUBSTRATE
31
Patent #:
8709873
Issue Dt:
04/29/2014
Application #:
13195465
Filing Dt:
08/01/2011
Publication #:
US20110285001
Pub Dt:
11/24/2011
Title:
LEADLESS INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
32
Patent #:
8669654
Issue Dt:
03/11/2014
Application #:
13197070
Filing Dt:
08/03/2011
Publication #:
US20120032315
Pub Dt:
02/09/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DIE PADDLE AND METHOD OF MANUFACTURE THEREOF
33
Patent #:
8674500
Issue Dt:
03/18/2014
Application #:
13218653
Filing Dt:
08/26/2011
Publication #:
US20110309500
Pub Dt:
12/22/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF SELF-CONFINEMENT OF CONDUCTIVE BUMP MATERIAL DURING REFLOW WITHOUT SOLDER MASK
34
Patent #:
8699232
Issue Dt:
04/15/2014
Application #:
13237918
Filing Dt:
09/20/2011
Publication #:
US20130070438
Pub Dt:
03/21/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND METHOD OF MANUFACTURE THEREOF
35
Patent #:
8698297
Issue Dt:
04/15/2014
Application #:
13243699
Filing Dt:
09/23/2011
Publication #:
US20130075926
Pub Dt:
03/28/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK DEVICE
36
Patent #:
8716065
Issue Dt:
05/06/2014
Application #:
13243886
Filing Dt:
09/23/2011
Publication #:
US20130075927
Pub Dt:
03/28/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
37
Patent #:
8703538
Issue Dt:
04/22/2014
Application #:
13244262
Filing Dt:
09/23/2011
Publication #:
US20130075916
Pub Dt:
03/28/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXTERNAL WIRE CONNECTION AND METHOD OF MANUFACTURE THEREOF
38
Patent #:
8659162
Issue Dt:
02/25/2014
Application #:
13245099
Filing Dt:
09/26/2011
Publication #:
US20120013004
Pub Dt:
01/19/2012
Title:
SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT STRUCTURE WITH TSV USING ENCAPSULANT FOR STRUCTURAL SUPPORT
39
Patent #:
8710640
Issue Dt:
04/29/2014
Application #:
13325359
Filing Dt:
12/14/2011
Publication #:
US20130154078
Pub Dt:
06/20/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SLUG AND METHOD OF MANUFACTURE THEREOF
40
Patent #:
8679900
Issue Dt:
03/25/2014
Application #:
13325530
Filing Dt:
12/14/2011
Publication #:
US20130154085
Pub Dt:
06/20/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT CONDUCTION AND METHOD OF MANUFACTURE THEREOF
41
Patent #:
8710670
Issue Dt:
04/29/2014
Application #:
13326116
Filing Dt:
12/14/2011
Publication #:
US20130154107
Pub Dt:
06/20/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COUPLING FEATURES AND METHOD OF MANUFACTURE THEREOF
42
Patent #:
8648470
Issue Dt:
02/11/2014
Application #:
13326157
Filing Dt:
12/14/2011
Publication #:
US20120187568
Pub Dt:
07/26/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING FO-WLCSP WITH MULTIPLE ENCAPSULANTS
43
Patent #:
8643166
Issue Dt:
02/04/2014
Application #:
13327529
Filing Dt:
12/15/2011
Publication #:
US20130154115
Pub Dt:
06/20/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
44
Patent #:
8723305
Issue Dt:
05/13/2014
Application #:
13335867
Filing Dt:
12/22/2011
Publication #:
US20120104599
Pub Dt:
05/03/2012
Title:
Semiconductor Package Having Semiconductor Die with Internal Vertical Interconnect Structure and Method Therefor
45
Patent #:
8648448
Issue Dt:
02/11/2014
Application #:
13339185
Filing Dt:
12/28/2011
Publication #:
US20120104573
Pub Dt:
05/03/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF SHIELDING SEMICONDUCTOR DIE FROM INTER-DEVICE INTERFERENCE
46
Patent #:
8716108
Issue Dt:
05/06/2014
Application #:
13426529
Filing Dt:
03/21/2012
Publication #:
US20130249117
Pub Dt:
09/26/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ULTRA-THIN CHIP AND METHOD OF MANUFACTURE THEREOF
47
Patent #:
8703541
Issue Dt:
04/22/2014
Application #:
13441550
Filing Dt:
04/06/2012
Publication #:
US20120193132
Pub Dt:
08/02/2012
Title:
ELECTRONIC SYSTEM WITH EXPANSION FEATURE
48
Patent #:
8659113
Issue Dt:
02/25/2014
Application #:
13446741
Filing Dt:
04/13/2012
Publication #:
US20120199971
Pub Dt:
08/09/2012
Title:
EMBEDDED SEMICONDUCTOR DIE PACKAGE AND METHOD OF MAKING THE SAME USING METAL FRAME CARRIER
49
Patent #:
8703535
Issue Dt:
04/22/2014
Application #:
13490908
Filing Dt:
06/07/2012
Publication #:
US20130328179
Pub Dt:
12/12/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE PREVENTING MECHANISM AND METHOD OF MANUFACTURE THEREOF
50
Patent #:
8709877
Issue Dt:
04/29/2014
Application #:
13495663
Filing Dt:
06/13/2012
Publication #:
US20130334668
Pub Dt:
12/19/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
51
Patent #:
8723309
Issue Dt:
05/13/2014
Application #:
13517897
Filing Dt:
06/14/2012
Publication #:
US20130334697
Pub Dt:
12/19/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MANUFACTURE THEREOF
52
Patent #:
8723310
Issue Dt:
05/13/2014
Application #:
13526877
Filing Dt:
06/19/2012
Publication #:
US20130334714
Pub Dt:
12/19/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING WARPAGE PREVENTION STRUCTURES
53
Patent #:
8692388
Issue Dt:
04/08/2014
Application #:
13536268
Filing Dt:
06/28/2012
Publication #:
US20120261810
Pub Dt:
10/18/2012
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WAFERSCALE SPACER
54
Patent #:
8710635
Issue Dt:
04/29/2014
Application #:
13560008
Filing Dt:
07/27/2012
Publication #:
US20120292749
Pub Dt:
11/22/2012
Title:
Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor Die
55
Patent #:
8723338
Issue Dt:
05/13/2014
Application #:
13586178
Filing Dt:
08/15/2012
Publication #:
US20140048919
Pub Dt:
02/20/2014
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ARRAY CONTACTS AND METHOD OF MANUFACTURE THEREOF
56
Patent #:
8685797
Issue Dt:
04/01/2014
Application #:
13597086
Filing Dt:
08/28/2012
Publication #:
US20120319266
Pub Dt:
12/20/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND UNDERFILL AND METHOD OF MANUFACTURE THEREOF
57
Patent #:
8729687
Issue Dt:
05/20/2014
Application #:
13649834
Filing Dt:
10/11/2012
Publication #:
US20130032954
Pub Dt:
02/07/2013
Title:
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM
58
Patent #:
8703610
Issue Dt:
04/22/2014
Application #:
13691578
Filing Dt:
11/30/2012
Publication #:
US20130087928
Pub Dt:
04/11/2013
Title:
Semiconductor Device and Method of Forming Conductive TSV With Insulating Annular Ring
59
Patent #:
RE44761
Issue Dt:
02/11/2014
Application #:
13756817
Filing Dt:
02/01/2013
Title:
SOLDER JOINT FLIP CHIP INTERCONNECTION HAVING RELIEF STRUCTURE
60
Patent #:
8703548
Issue Dt:
04/22/2014
Application #:
13765478
Filing Dt:
02/12/2013
Publication #:
US20130171800
Pub Dt:
07/04/2013
Title:
Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)
61
Patent #:
8709935
Issue Dt:
04/29/2014
Application #:
13768862
Filing Dt:
02/15/2013
Publication #:
US20130154090
Pub Dt:
06/20/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES
Assignor
1
STATS CHIPPAC LTD.
Exec Dt:
03/29/2016
Assignee
1
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 23
SINGAPORE, SINT MAARTEEN
Correspondence name and address
DARIA DELIZIO
1919 PENNSYLVANIA AVE., SUITE 800
WASHINGTON, DC 20006

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