Total properties:
524
Page
5
of
6
Pages:
1 2 3 4 5 6
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10939292
|
Filing Dt:
|
09/10/2004
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
Title:
|
Wire bonding method for copper interconnects in semiconductor devices
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10951430
|
Filing Dt:
|
09/28/2004
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
Title:
|
Whisker-free lead frames
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
10953291
|
Filing Dt:
|
09/29/2004
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
Title:
|
METHOD AND STRUCTURES FOR TESTING A SEMICONDUCTOR WAFER PRIOR TO PERFORMING A FLIP CHIP BUMPING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
10954940
|
Filing Dt:
|
09/30/2004
|
Publication #:
|
|
Pub Dt:
|
04/06/2006
| | | | |
Title:
|
CONSTRUCTION TO IMPROVE THERMAL PERFORMANCE AND REDUCE DIE BACKSIDE WARPAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
10955912
|
Filing Dt:
|
09/30/2004
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR FORMING SOLDER JOINTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10955913
|
Filing Dt:
|
09/30/2004
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
Title:
|
REINFORCED BOND PAD FOR A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10960680
|
Filing Dt:
|
10/07/2004
|
Publication #:
|
|
Pub Dt:
|
04/13/2006
| | | | |
Title:
|
MULTI-CHIP INTEGRATED CIRCUIT MODULE FOR HIGH-FREQUENCY OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
10979491
|
Filing Dt:
|
11/02/2004
|
Publication #:
|
|
Pub Dt:
|
03/24/2005
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
10997630
|
Filing Dt:
|
11/24/2004
|
Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
Title:
|
LEADFRAME DESIGNS FOR INTEGRATED CIRCUIT PLASTIC PACKAGES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11012838
|
Filing Dt:
|
12/15/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
System and method for using film deposition techniques to provide an antenna within an integrated circuit package
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
11015534
|
Filing Dt:
|
12/18/2004
|
Publication #:
|
|
Pub Dt:
|
06/22/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICE PACKAGE WITH REDUCED LEAKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
11015535
|
Filing Dt:
|
12/18/2004
|
Publication #:
|
|
Pub Dt:
|
06/22/2006
| | | | |
Title:
|
PACKAGES FOR ENCAPSULATED SEMICONDUCTOR DEVICES AND METHOD OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2007
|
Application #:
|
11028695
|
Filing Dt:
|
01/04/2005
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
FAILURE ANALYSIS AND TESTING OF SEMI-CONDUCTOR DEVICES USING INTELLIGENT SOFTWARE ON AUTOMATED TEST EQUIPMENT (ATE)
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2007
|
Application #:
|
11049246
|
Filing Dt:
|
02/02/2005
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
DEVICE PACKAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2007
|
Application #:
|
11049407
|
Filing Dt:
|
02/02/2005
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
DEVICE PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
11055712
|
Filing Dt:
|
02/10/2005
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
PACKAGING FOR ELECTRONIC MODULES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
11065838
|
Filing Dt:
|
02/25/2005
|
Publication #:
|
|
Pub Dt:
|
08/31/2006
| | | | |
Title:
|
INTEGRATED CIRCUIT WITH STAGGERED DIFFERENTIAL WIRE BOND PAIRS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2006
|
Application #:
|
11073802
|
Filing Dt:
|
03/07/2005
|
Title:
|
SUBSTRATE VIA LAYOUT TO IMPROVE BIAS HUMIDITY TESTING RELIABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2006
|
Application #:
|
11074358
|
Filing Dt:
|
03/07/2005
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE WITH LEAD FINGERS EXTENDING INTO A SLOT OF A DIE PADDLE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2009
|
Application #:
|
11079028
|
Filing Dt:
|
03/14/2005
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
COMPOSABLE SYSTEM-IN-PACKAGE INTEGRATED CIRCUITS AND PROCESS OF COMPOSING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
11080859
|
Filing Dt:
|
03/15/2005
|
Publication #:
|
|
Pub Dt:
|
07/21/2005
| | | | |
Title:
|
ELECTRONIC COMPONENT PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2008
|
Application #:
|
11095929
|
Filing Dt:
|
03/31/2005
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
Title:
|
CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2006
|
Application #:
|
11097796
|
Filing Dt:
|
04/02/2005
|
Title:
|
METHOD OF TESTING ELECTRONIC WAFERS HAVING LEAD-FREE SOLDER CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2008
|
Application #:
|
11097895
|
Filing Dt:
|
04/01/2005
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
Title:
|
BALL ASSIGNMENT SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
11102156
|
Filing Dt:
|
04/08/2005
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
TEST VEHICLE DATA ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
11131885
|
Filing Dt:
|
05/18/2005
|
Title:
|
PROBING FIXTURE FOR SEMICONDUCTOR WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
11132751
|
Filing Dt:
|
05/18/2005
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR AVOIDING DICING CHIP-OUTS IN INTEGRATED CIRCUIT DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
11140455
|
Filing Dt:
|
05/27/2005
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
ZERO ATE INSERTION FORCE INTERPOSER DAUGHTER CARD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
|
Application #:
|
11158370
|
Filing Dt:
|
06/22/2005
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
INTEGRATED CIRCUIT WITH HEAT CONDUCTING STRUCTURES FOR LOCALIZED THERMAL CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2009
|
Application #:
|
11158435
|
Filing Dt:
|
06/22/2005
|
Publication #:
|
|
Pub Dt:
|
11/03/2005
| | | | |
Title:
|
Integrated circuit die for wire bonding and flip-chip mounting
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
11235920
|
Filing Dt:
|
09/27/2005
|
Publication #:
|
|
Pub Dt:
|
03/29/2007
| | | | |
Title:
|
INTEGRATED CIRCUIT DEVICE INCORPORATING METALLURIGICAL BOND TO ENHANCE THERMAL CONDUCTION TO A HEAT SINK
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2009
|
Application #:
|
11258253
|
Filing Dt:
|
10/25/2005
|
Publication #:
|
|
Pub Dt:
|
02/16/2006
| | | | |
Title:
|
I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
11260334
|
Filing Dt:
|
10/27/2005
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
Title:
|
ASYMMETRIC ALIGNMENT OF SUBSTRATE INTERCONNECT TO SEMICONDUCTOR DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2011
|
Application #:
|
11277188
|
Filing Dt:
|
03/22/2006
|
Publication #:
|
|
Pub Dt:
|
09/27/2007
| | | | |
Title:
|
DEVICE FOR AVOIDING PARASITIC CAPACITANCE IN AN INTEGRATED CIRCUIT PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
11283340
|
Filing Dt:
|
11/18/2005
|
Publication #:
|
|
Pub Dt:
|
05/24/2007
| | | | |
Title:
|
SCALING OF FUNCTIONAL ASSIGNMENTS IN PACKAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2009
|
Application #:
|
11298030
|
Filing Dt:
|
12/09/2005
|
Publication #:
|
|
Pub Dt:
|
06/14/2007
| | | | |
Title:
|
INTEGRATED CIRCUIT HAVING BOND PAD WITH IMPROVED THERMAL AND MECHANICAL PROPERTIES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
|
Application #:
|
11300789
|
Filing Dt:
|
12/14/2005
|
Publication #:
|
|
Pub Dt:
|
06/14/2007
| | | | |
Title:
|
METHOD OF USING AUTOMATED TEST EQUIPMENT TO SCREEN FOR LEAKAGE INDUCING DEFECTS AFTER CALIBRATION TO INTRINSIC LEAKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2009
|
Application #:
|
11302690
|
Filing Dt:
|
12/14/2005
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
INTEGRATED CIRCUIT DEVICE HAVING FLEXIBLE LEADFRAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
11304862
|
Filing Dt:
|
12/14/2005
|
Publication #:
|
|
Pub Dt:
|
06/14/2007
| | | | |
Title:
|
SEMICONDUCTOR PACKAGE HAVING INCREASED RESISTANCE TO ELECTROSTATIC DISCHARGE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
11324119
|
Filing Dt:
|
12/30/2005
|
Title:
|
SOCKETLESS/BOARDLESS TEST INTERPOSER CARD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
11334870
|
Filing Dt:
|
01/19/2006
|
Publication #:
|
|
Pub Dt:
|
07/19/2007
| | | | |
Title:
|
POWER CONFIGURATION METHOD FOR STRUCTURED ASICS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2008
|
Application #:
|
11360200
|
Filing Dt:
|
02/23/2006
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
Title:
|
FLEXIBLE CIRCUIT SUBSTRATE FOR FLIP-CHIP-ON-FLEX APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2009
|
Application #:
|
11375302
|
Filing Dt:
|
03/14/2006
|
Publication #:
|
|
Pub Dt:
|
09/20/2007
| | | | |
Title:
|
LOW THERMAL RESISTANCE ASSEMBLY FOR FLIP CHIP APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2010
|
Application #:
|
11385086
|
Filing Dt:
|
03/21/2006
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
METHODS AND APPARATUS FOR DETERMINING PAD HEIGHT FOR A WIRE-BONDING OPERATION IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11385245
|
Filing Dt:
|
03/21/2006
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
METHODS AND APPARATUS FOR WIRE BONDING WITH WIRE LENGTH ADJUSTMENT IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2011
|
Application #:
|
11395779
|
Filing Dt:
|
03/31/2006
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
METHODS AND APPARATUS FOR INTEGRATED CIRCUIT BALL BONDING WITH SUBSTANTIALLY PERPENDICULAR WIRE BOND PROFILES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2010
|
Application #:
|
11399723
|
Filing Dt:
|
04/06/2006
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
SEMICONDUCTOR PACKAGE AND METHOD USING ISOLATED VSS PLANE TO ACCOMMODATE HIGH SPEED CIRCUITRY GROUND ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
11448560
|
Filing Dt:
|
06/07/2006
|
Publication #:
|
|
Pub Dt:
|
10/12/2006
| | | | |
Title:
|
REINFORCED BOND PAD FOR A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
|
Application #:
|
11459249
|
Filing Dt:
|
07/21/2006
|
Publication #:
|
|
Pub Dt:
|
03/29/2007
| | | | |
Title:
|
SOLDER BUMP STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURE THEREFORE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2010
|
Application #:
|
11460459
|
Filing Dt:
|
07/27/2006
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
ON-CHIP SENSOR ARRAY FOR TEMPERATURE MANAGEMENT IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2009
|
Application #:
|
11468901
|
Filing Dt:
|
08/31/2006
|
Publication #:
|
|
Pub Dt:
|
03/22/2007
| | | | |
Title:
|
HEAT DISSIPATION IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2012
|
Application #:
|
11469960
|
Filing Dt:
|
09/05/2006
|
Publication #:
|
|
Pub Dt:
|
03/22/2007
| | | | |
Title:
|
ROUTING UNDER BOND PAD FOR THE REPLACEMENT OF AN INTERCONNECT LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11494221
|
Filing Dt:
|
07/27/2006
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
INTEGRATED CIRCUIT WITH SUBSTANTIALLY PERPENDICULAR WIRE BONDS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2008
|
Application #:
|
11505152
|
Filing Dt:
|
08/16/2006
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
PLASTIC OVERMOLDED PACKAGES WITH MECHANICALLY DECOUPLED LID ATTACH ATTACHMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2008
|
Application #:
|
11506680
|
Filing Dt:
|
08/18/2006
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE AND SYSTEM INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
11530550
|
Filing Dt:
|
09/11/2006
|
Title:
|
SYSTEMS AND METHODS FOR DISTRIBUTING I/O IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2010
|
Application #:
|
11565701
|
Filing Dt:
|
12/01/2006
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
WIRE BOND INTEGRATED CIRCUIT PACKAGE FOR HIGH SPEED I/O
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2009
|
Application #:
|
11641989
|
Filing Dt:
|
12/18/2006
|
Publication #:
|
|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
ELECTRONIC COMPONENT CONNECTION SUPPORT STRUCTURES INCLUDING AIR AS A DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2008
|
Application #:
|
11670031
|
Filing Dt:
|
02/01/2007
|
Publication #:
|
|
Pub Dt:
|
08/02/2007
| | | | |
Title:
|
FAILURE ANALYSIS AND TESTING OF SEMI-CONDUCTOR DEVICES USING INTELLIGENT SOFTWARE ON AUTOMATED TEST EQUIPMENT (ATE)
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
11684674
|
Filing Dt:
|
03/12/2007
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
SYSTEMS AND METHODS FOR SUPPORTING A SUBSET OF MULTIPLE INTERFACE TYPES IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2010
|
Application #:
|
11717227
|
Filing Dt:
|
03/12/2007
|
Publication #:
|
|
Pub Dt:
|
09/18/2008
| | | | |
Title:
|
WIRE BONDING METHOD AND RELATED DEVICE FOR HIGH-FREQUENCY APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2009
|
Application #:
|
11772267
|
Filing Dt:
|
07/02/2007
|
Publication #:
|
|
Pub Dt:
|
01/08/2009
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE WITH SPUTTERED HEAT SINK FOR IMPROVED THERMAL PERFORMANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2009
|
Application #:
|
11788346
|
Filing Dt:
|
04/19/2007
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE PACKAGE WITH BASE FEATURES TO REDUCE LEAKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2008
|
Application #:
|
11868624
|
Filing Dt:
|
10/08/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT DEVICE INCORPORATING METALLURGICAL BOND TO ENHANCE THERMAL CONDUCTION TO A HEAT SINK
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
11884328
|
Filing Dt:
|
05/30/2008
|
Publication #:
|
|
Pub Dt:
|
03/19/2009
| | | | |
Title:
|
STRUCTURE AND METHOD FOR FABRICATING FLIP CHIP DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
11973859
|
Filing Dt:
|
10/10/2007
|
Publication #:
|
|
Pub Dt:
|
04/16/2009
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE INCLUDING WIRE BONDS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
12034745
|
Filing Dt:
|
02/21/2008
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
Title:
|
BALL GRID ARRAY PACKAGE LAYOUT SUPPORTING MANY VOLTAGE SPLITS AND FLEXIBLE SPLIT LOCATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
12038911
|
Filing Dt:
|
02/28/2008
|
Publication #:
|
|
Pub Dt:
|
09/03/2009
| | | | |
Title:
|
PROCESS OF GROUNDING HEAT SPREADER/STIFFENER TO A FLIP CHIP PACKAGE USING SOLDER AND FILM ADHESIVE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
12060387
|
Filing Dt:
|
04/01/2008
|
Publication #:
|
|
Pub Dt:
|
06/18/2009
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE FOR HIGH-SPEED SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
12061728
|
Filing Dt:
|
04/03/2008
|
Publication #:
|
|
Pub Dt:
|
10/08/2009
| | | | |
Title:
|
HEAT DISSIPATION FOR INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2009
|
Application #:
|
12079124
|
Filing Dt:
|
03/25/2008
|
Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
LEADFRAME DESIGNS FOR PLASTIC OVERMOLD PACKAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2009
|
Application #:
|
12119575
|
Filing Dt:
|
05/13/2008
|
Title:
|
PAD CURRENT SPLITTING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
12121363
|
Filing Dt:
|
05/15/2008
|
Publication #:
|
|
Pub Dt:
|
11/19/2009
| | | | |
Title:
|
FLIPCHIP BUMP PATTERNS FOR EFFICIENT I-MESH POWER DISTRIBUTION SCHEMES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2011
|
Application #:
|
12139185
|
Filing Dt:
|
06/13/2008
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
Title:
|
ASYMMETRIC ALIGNMENT OF SUBSTRATE INTERCONNECT TO SEMICONDUCTOR DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
12151108
|
Filing Dt:
|
05/02/2008
|
Publication #:
|
|
Pub Dt:
|
11/05/2009
| | | | |
Title:
|
ELECTRONIC PACKAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
12154794
|
Filing Dt:
|
05/27/2008
|
Publication #:
|
|
Pub Dt:
|
12/03/2009
| | | | |
Title:
|
METHOD OF MAKING ELECTRONIC ENTITIES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
12160233
|
Filing Dt:
|
07/08/2008
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
Title:
|
HIGH THERMAL PERFORMANCE PACKAGING FOR CIRCUIT DIES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2009
|
Application #:
|
12163453
|
Filing Dt:
|
06/27/2008
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2009
|
Application #:
|
12171903
|
Filing Dt:
|
07/11/2008
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
Title:
|
METHODS AND APPARATUS FOR WIRE BONDING WITH WIRE LENGTH ADJUSTMENT IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
12194706
|
Filing Dt:
|
08/20/2008
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
Title:
|
THERMAL MONITORING AND MANAGEMENT OF INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
12206786
|
Filing Dt:
|
09/09/2008
|
Publication #:
|
|
Pub Dt:
|
03/11/2010
| | | | |
Title:
|
PACKAGE WITH POWER AND GROUND THROUGH VIA
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
12220182
|
Filing Dt:
|
07/22/2008
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
Title:
|
MANUFACTURE OF DEVICES INCLUDING SOLDER BUMPS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2009
|
Application #:
|
12228720
|
Filing Dt:
|
08/15/2008
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
PLASTIC OVERMOLDED PACKAGES WITH MECHANCIALLY DECOUPLED LID ATTACH ATTACHMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
12253403
|
Filing Dt:
|
10/17/2008
|
Publication #:
|
|
Pub Dt:
|
02/12/2009
| | | | |
Title:
|
ELECTRICAL DEVICES HAVING ADJUSTABLE CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2009
|
Application #:
|
12283820
|
Filing Dt:
|
09/15/2008
|
Publication #:
|
|
Pub Dt:
|
01/22/2009
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE AND SYSTEM INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
12327987
|
Filing Dt:
|
12/04/2008
|
Publication #:
|
|
Pub Dt:
|
06/10/2010
| | | | |
Title:
|
PREFERENTIALLY COOLED ELECTRONIC DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2012
|
Application #:
|
12331561
|
Filing Dt:
|
12/10/2008
|
Publication #:
|
|
Pub Dt:
|
09/24/2009
| | | | |
Title:
|
WIRE BONDING OVER ACTIVE CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2012
|
Application #:
|
12337519
|
Filing Dt:
|
12/17/2008
|
Publication #:
|
|
Pub Dt:
|
04/23/2009
| | | | |
Title:
|
SEMICONDUCTOR PACKAGE HAVING INCREASED RESISTANCE TO ELECTROSTATIC DISCHARGE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
|
Application #:
|
12432763
|
Filing Dt:
|
04/30/2009
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
Title:
|
SEPARATE PROBE AND BOND REGIONS OF AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
12462069
|
Filing Dt:
|
07/28/2009
|
Publication #:
|
|
Pub Dt:
|
11/26/2009
| | | | |
Title:
|
WHISKER-FREE LEAD FRAMES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
12463718
|
Filing Dt:
|
05/11/2009
|
Title:
|
CIRCUIT APPARATUS INCLUDING REMOVABLE BOND PAD EXTENSION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
12469985
|
Filing Dt:
|
05/21/2009
|
Publication #:
|
|
Pub Dt:
|
11/26/2009
| | | | |
Title:
|
SOLUTION FOR PACKAGE CROSSTALK MINIMIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2012
|
Application #:
|
12471982
|
Filing Dt:
|
05/26/2009
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
ALUMINUM BOND PADS WITH ENHANCED WIRE BOND STABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
12483139
|
Filing Dt:
|
06/11/2009
|
Publication #:
|
|
Pub Dt:
|
12/16/2010
| | | | |
Title:
|
ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
12485238
|
Filing Dt:
|
06/16/2009
|
Publication #:
|
|
Pub Dt:
|
12/16/2010
| | | | |
Title:
|
METHOD OF GENERATING A LEADFRAME IC PACKAGE MODEL, A LEADFRAME MODELER AND AN IC DESIGN SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2012
|
Application #:
|
12486592
|
Filing Dt:
|
06/17/2009
|
Publication #:
|
|
Pub Dt:
|
12/23/2010
| | | | |
Title:
|
LEAD FRAME DESIGN TO IMPROVE RELIABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
12501686
|
Filing Dt:
|
07/13/2009
|
Publication #:
|
|
Pub Dt:
|
01/13/2011
| | | | |
Title:
|
SOLDER INTERCONNECT BY ADDITION OF COPPER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2011
|
Application #:
|
12506746
|
Filing Dt:
|
07/21/2009
|
Publication #:
|
|
Pub Dt:
|
12/03/2009
| | | | |
Title:
|
I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
|
Application #:
|
12546083
|
Filing Dt:
|
08/24/2009
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
Title:
|
CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
12625457
|
Filing Dt:
|
11/24/2009
|
Publication #:
|
|
Pub Dt:
|
03/18/2010
| | | | |
Title:
|
SEMICONDUCTOR PACKAGE AND METHOD USING ISOLATED VSS PLANE TO ACCOMMODATE HIGH SPEED CIRCUITRY GROUND ISOLATION
|
|