USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Assignments on the Web > Patent Query

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	056702/0387			Pages:	7
		Recorded:	06/29/2021
Conveyance:	MERGER AND CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).

Total properties: 94

Patent #:	7036064	Issue Dt:	04/25/2006	Application #:	09872212	Filing Dt:	05/31/2001
Title:	SYNCHRONIZATION POINT ACROSS DIFFERENT MEMORY BIST CONTROLLERS

Patent #:	7168059	Issue Dt:	01/23/2007	Application #:	10126913	Filing Dt:	04/19/2002
Publication #:	US20030005404	Pub Dt:	01/02/2003
Title:	GRAPHICAL LOOP PROFILE ANALYSIS

Patent #:	6757882	Issue Dt:	06/29/2004	Application #:	10132587	Filing Dt:	04/24/2002
Publication #:	US20030009658	Pub Dt:	01/09/2003
Title:	SELF-DESCRIBING IP PACKAGE FOR ENHANCED PLATFORM BASED SOC DESIGN

Patent #:	7020855	Issue Dt:	03/28/2006	Application #:	10222429	Filing Dt:	08/16/2002
Publication #:	US20030009731	Pub Dt:	01/09/2003
Title:	DIGITAL CIRCUIT LAYOUT TECHNIQUES USING IDENTIFICATION OF INPUT EQUIVALENCE

Patent #:	6708192	Issue Dt:	03/16/2004	Application #:	10346699	Filing Dt:	01/16/2003
Publication #:	US20030110193	Pub Dt:	06/12/2003
Title:	METHOD FOR SYNTHESIZING LINEAR FINITE STATE MACHINES

Patent #:	7111209	Issue Dt:	09/19/2006	Application #:	10355941	Filing Dt:	01/31/2003
Publication #:	US20030131298	Pub Dt:	07/10/2003
Title:	TEST PATTERN COMPRESSION FOR AN INTEGRATED CIRCUIT TEST ENVIRONMENT

Patent #:	7305648	Issue Dt:	12/04/2007	Application #:	10870072	Filing Dt:	06/18/2004
Publication #:	US20050114821	Pub Dt:	05/26/2005
Title:	DISTRIBUTED AUTOROUTING OF CONDUCTIVE PATHS IN PRINTED CIRCUIT BOARDS

Patent #:	7290193	Issue Dt:	10/30/2007	Application #:	10957259	Filing Dt:	09/30/2004
Publication #:	US20050071720	Pub Dt:	03/31/2005
Title:	SYSTEM VERIFICATION USING ONE OR MORE AUTOMATA

Patent #:	7500163	Issue Dt:	03/03/2009	Application #:	10973522	Filing Dt:	10/25/2004
Publication #:	US20050097419	Pub Dt:	05/05/2005
Title:	METHOD AND APPARATUS FOR SELECTIVELY COMPACTING TEST RESPONSES

Patent #:	7412676	Issue Dt:	08/12/2008	Application #:	11209252	Filing Dt:	08/22/2005
Publication #:	US20060005154	Pub Dt:	01/05/2006
Title:	INTEGRATED OPC VERIFICATION TOOL

Patent #:	7302624	Issue Dt:	11/27/2007	Application #:	11213327	Filing Dt:	08/25/2005
Publication #:	US20060041813	Pub Dt:	02/23/2006
Title:	ADAPTIVE FAULT DIAGNOSIS OF COMPRESSED TEST RESPONSES

Patent #:	7512508	Issue Dt:	03/31/2009	Application #:	11221395	Filing Dt:	09/06/2005
Publication #:	US20060066339	Pub Dt:	03/30/2006
Title:	DETERMINING AND ANALYZING INTEGRATED CIRCUIT YIELD AND QUALITY

Patent #:	7428680	Issue Dt:	09/23/2008	Application #:	11283527	Filing Dt:	11/18/2005
Publication #:	US20060156134	Pub Dt:	07/13/2006
Title:	PROGRAMMABLE MEMORY BUILT-IN-SELF-TEST (MBIST) METHOD AND APPARATUS

Patent #:	7506232	Issue Dt:	03/17/2009	Application #:	11502655	Filing Dt:	08/11/2006
Publication #:	US20070011530	Pub Dt:	01/11/2007
Title:	DECOMPRESSOR/PRPG FOR APPLYING PSEUDO-RANDOM AND DETERMINISTIC TEST PATTERNS

Patent #:	8280687	Issue Dt:	10/02/2012	Application #:	11584038	Filing Dt:	10/20/2006
Publication #:	US20070100586	Pub Dt:	05/03/2007
Title:	DIRECT FAULT DIAGNOSTICS USING PER-PATTERN COMPACTOR SIGNATURES

Patent #:	7562336	Issue Dt:	07/14/2009	Application #:	11669100	Filing Dt:	01/30/2007
Publication #:	US20070124708	Pub Dt:	05/31/2007
Title:	CONTRAST BASED RESOLUTION ENHANCEMENT FOR PHOTOLITHOGRAPHIC PROCESSING

Patent #:	8417504	Issue Dt:	04/09/2013	Application #:	11811695	Filing Dt:	06/11/2007
Publication #:	US20070276644	Pub Dt:	11/29/2007
Title:	CONVERSION OF CIRCUIT DESCRIPTION TO A TRANSACTION MODEL

Patent #:	8205175	Issue Dt:	06/19/2012	Application #:	11877599	Filing Dt:	10/23/2007
Publication #:	US20080141227	Pub Dt:	06/12/2008
Title:	STRUCTURED ALGORITHMIC PROGRAMMING LANGUAGE APPROACH TO SYSTEM DESIGN

Patent #:	7647540	Issue Dt:	01/12/2010	Application #:	11880192	Filing Dt:	07/19/2007
Publication #:	US20080052578	Pub Dt:	02/28/2008
Title:	DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS

Patent #:	7523372	Issue Dt:	04/21/2009	Application #:	11895845	Filing Dt:	08/27/2007
Publication #:	US20070300110	Pub Dt:	12/27/2007
Title:	PHASE SHIFTER WITH REDUCED LINEAR DEPENDENCY

Patent #:	8103988	Issue Dt:	01/24/2012	Application #:	11937411	Filing Dt:	11/08/2007
Publication #:	US20080178139	Pub Dt:	07/24/2008
Title:	USE OF BREAKOUTS IN PRINTED CIRCUIT BOARD DESIGNS

Patent #:	7831938	Issue Dt:	11/09/2010	Application #:	11986329	Filing Dt:	11/21/2007
Publication #:	US20080077906	Pub Dt:	03/27/2008
Title:	INTERACTIVE INTERFACE RESOURCE ALLOCATION IN A BEHAVIORAL SYNTHESIS TOOL

Patent #:	7554870	Issue Dt:	06/30/2009	Application #:	12018860	Filing Dt:	01/24/2008
Publication #:	US20080137390	Pub Dt:	06/12/2008
Title:	DRAM WITH REDUCED POWER CONSUMPTION

Patent #:	7712062	Issue Dt:	05/04/2010	Application #:	12029440	Filing Dt:	02/11/2008
Publication #:	US20080134115	Pub Dt:	06/05/2008
Title:	METASTABILITY EFFECTS SIMULATION FOR A CIRCUIT DESCRIPTION

Patent #:	7840931	Issue Dt:	11/23/2010	Application #:	12039679	Filing Dt:	02/28/2008
Publication #:	US20080148215	Pub Dt:	06/19/2008
Title:	LOOP MANIPULATION IF A BEHAVIORAL SYNTHESIS TOOL

Patent #:	8356265	Issue Dt:	01/15/2013	Application #:	12046628	Filing Dt:	03/12/2008
Publication #:	US20090013298	Pub Dt:	01/08/2009
Title:	OFFSET FILL

Patent #:	7715262	Issue Dt:	05/11/2010	Application #:	12163989	Filing Dt:	06/27/2008
Publication #:	US20090010041	Pub Dt:	01/08/2009
Title:	HYBRID DRAM

Patent #:	8091054	Issue Dt:	01/03/2012	Application #:	12210915	Filing Dt:	09/15/2008
Publication #:	US20090013300	Pub Dt:	01/08/2009
Title:	SYNTHESIS STRATEGIES BASED ON THE APPROPRIATE USE OF INDUCTANCE EFFECTS

Patent #:	7903497	Issue Dt:	03/08/2011	Application #:	12258231	Filing Dt:	10/24/2008
Publication #:	US20090190389	Pub Dt:	07/30/2009
Title:	MULTI-PORT SRAM IMPLEMENTED WITH SINGLE-PORT 6-TRANSISTOR MEMORY CELLS COUPLED TO AN INPUT MULTIPLEXER AND AN OUTPUT DEMULTIPLEXER

Patent #:	7852113	Issue Dt:	12/14/2010	Application #:	12326086	Filing Dt:	12/01/2008
Publication #:	US20090189685	Pub Dt:	07/30/2009
Title:	LEAKAGE CONTROL

Patent #:	7877656	Issue Dt:	01/25/2011	Application #:	12352994	Filing Dt:	01/13/2009
Publication #:	US20090183041	Pub Dt:	07/16/2009
Title:	CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS TO A CIRCUIT-UNDER-TEST

Patent #:	8549449	Issue Dt:	10/01/2013	Application #:	12380138	Filing Dt:	02/23/2009
Publication #:	US20090172613	Pub Dt:	07/02/2009
Title:	MUTUAL INDUCTANCE EXTRACTION USING DIPOLE APPROXIMATIONS

Patent #:	8214788	Issue Dt:	07/03/2012	Application #:	12400672	Filing Dt:	03/09/2009
Publication #:	US20090228847	Pub Dt:	09/10/2009
Title:	HIGH-FREQUENCY VLSI INTERCONNECT AND INTENTIONAL INDUCTOR IMPEDANCE EXTRACTION IN THE PRESENCE OF A MULTI-LAYER CONDUCTIVE SUBSTRATE

Patent #:	9323161	Issue Dt:	04/26/2016	Application #:	12606098	Filing Dt:	10/26/2009
Publication #:	US20100039633	Pub Dt:	02/18/2010
Title:	SOURCE OPTIMIZATION BY ASSIGNING PIXEL INTENSITIES FOR DIFFRACTIVE OPTICAL ELEMENT USING MATHEMATICAL RELATIONSHIP

Patent #:	8015461	Issue Dt:	09/06/2011	Application #:	12641150	Filing Dt:	12/17/2009
Publication #:	US20100138708	Pub Dt:	06/03/2010
Title:	DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS

Patent #:	8250495	Issue Dt:	08/21/2012	Application #:	12689972	Filing Dt:	01/19/2010
Publication #:	US20100223590	Pub Dt:	09/02/2010
Title:	MASK DECOMPOSITION FOR DOUBLE DIPOLE LITHOGRAPHY

Patent #:	7865792	Issue Dt:	01/04/2011	Application #:	12703057	Filing Dt:	02/09/2010
Publication #:	US20100146350	Pub Dt:	06/10/2010
Title:	TEST GENERATION METHODS FOR REDUCING POWER DISSIPATION AND SUPPLY CURRENTS

Patent #:	8321817	Issue Dt:	11/27/2012	Application #:	12723619	Filing Dt:	03/12/2010
Publication #:	US20110307844	Pub Dt:	12/15/2011
Title:	MODEL-BASED FILL

Patent #:	8667446	Issue Dt:	03/04/2014	Application #:	12749237	Filing Dt:	03/29/2010
Publication #:	US20100251191	Pub Dt:	09/30/2010
Title:	EXTRACTING HIGH FREQUENCY IMPEDANCE IN A CIRCUIT DESIGN USING AN ELECTRONIC DESIGN AUTOMATION TOOL

Patent #:	8510690	Issue Dt:	08/13/2013	Application #:	12777226	Filing Dt:	05/10/2010
Publication #:	US20100223583	Pub Dt:	09/02/2010
Title:	HIERARCHICAL FEATURE EXTRACTION FOR ELECTRICAL INTERACTION CALCULATIONS

Patent #:	8209572	Issue Dt:	06/26/2012	Application #:	12941404	Filing Dt:	11/08/2010
Publication #:	US20110145774	Pub Dt:	06/16/2011
Title:	TESTING EMBEDDED MEMORIES IN AN INTEGRATED CIRCUIT

Patent #:	8645880	Issue Dt:	02/04/2014	Application #:	12945674	Filing Dt:	11/12/2010
Publication #:	US20110119643	Pub Dt:	05/19/2011
Title:	SUM OF COHERENT SYSTEMS (SOCS) APPROXIMATION BASED ON OBJECT INFORMATION

Patent #:	10596219	Issue Dt:	03/24/2020	Application #:	13017788	Filing Dt:	01/31/2011
Publication #:	US20110320990	Pub Dt:	12/29/2011
Title:	LOGIC-DRIVEN LAYOUT VERIFICATION

Patent #:	8516317	Issue Dt:	08/20/2013	Application #:	13018279	Filing Dt:	01/31/2011
Publication #:	US20120198294	Pub Dt:	08/02/2012
Title:	METHODS FOR AT-SPEED TESTING OF MEMORY INTERFACE

Patent #:	8418121	Issue Dt:	04/09/2013	Application #:	13027090	Filing Dt:	02/14/2011
Publication #:	US20110138346	Pub Dt:	06/09/2011
Title:	MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING

Patent #:	8290738	Issue Dt:	10/16/2012	Application #:	13049844	Filing Dt:	03/16/2011
Publication #:	US20110166818	Pub Dt:	07/07/2011
Title:	LOW POWER SCAN TESTING TECHNIQUES AND APPARATUS

Patent #:	8628236	Issue Dt:	01/14/2014	Application #:	13091867	Filing Dt:	04/21/2011
Publication #:	US20110268147	Pub Dt:	11/03/2011
Title:	THERMAL ANALYSIS

Patent #:	8607168	Issue Dt:	12/10/2013	Application #:	13092440	Filing Dt:	04/22/2011
Publication #:	US20110202898	Pub Dt:	08/18/2011
Title:	CONTOUR ALIGNMENT FOR MODEL CALIBRATION

Patent #:	8225266	Issue Dt:	07/17/2012	Application #:	13235934	Filing Dt:	09/19/2011
Publication #:	US20120011485	Pub Dt:	01/12/2012
Title:	MODELING THE SKIN EFFECT USING EFFICIENT CONDUCTION MODE TECHNIQUES

Patent #:	8434031	Issue Dt:	04/30/2013	Application #:	13283523	Filing Dt:	10/27/2011
Publication #:	US20120042291	Pub Dt:	02/16/2012
Title:	INVERSE MASK DESIGN AND CORRECTION FOR ELECTRONIC DESIGN

Patent #:	8504959	Issue Dt:	08/06/2013	Application #:	13290891	Filing Dt:	11/07/2011
Publication #:	US20120144351	Pub Dt:	06/07/2012
Title:	ANALYSIS OPTIMZER

Patent #:	8726113	Issue Dt:	05/13/2014	Application #:	13453929	Filing Dt:	04/23/2012
Publication #:	US20120210181	Pub Dt:	08/16/2012
Title:	SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

Patent #:	8935582	Issue Dt:	01/13/2015	Application #:	13460407	Filing Dt:	04/30/2012
Publication #:	US20120216088	Pub Dt:	08/23/2012
Title:	GENERATING TEST SETS FOR DIAGNOSING SCAN CHAIN FAILURES

Patent #:	8566068	Issue Dt:	10/22/2013	Application #:	13480426	Filing Dt:	05/24/2012
Publication #:	US20120232881	Pub Dt:	09/13/2012
Title:	TRACE ROUTING NETWORK

Patent #:	8707232	Issue Dt:	04/22/2014	Application #:	13492763	Filing Dt:	06/08/2012
Publication #:	US20130024830	Pub Dt:	01/24/2013
Title:	FAULT DIAGNOSIS BASED ON DESIGN PARTITIONING

Patent #:	8751981	Issue Dt:	06/10/2014	Application #:	13532484	Filing Dt:	06/25/2012
Publication #:	US20120266117	Pub Dt:	10/18/2012
Title:	LOGIC INJECTION

Patent #:	8638620	Issue Dt:	01/28/2014	Application #:	13599682	Filing Dt:	08/30/2012
Publication #:	US20120320692	Pub Dt:	12/20/2012
Title:	RANDOM ACCESS MEMORY FOR USE IN AN EMULATION ENVIRONMENT

Patent #:	8635562	Issue Dt:	01/21/2014	Application #:	13651691	Filing Dt:	10/15/2012
Publication #:	US20130042213	Pub Dt:	02/14/2013
Title:	Data Flow Branching in Mask Data Preparation

Patent #:	8661304	Issue Dt:	02/25/2014	Application #:	13681182	Filing Dt:	11/19/2012
Publication #:	US20130080849	Pub Dt:	03/28/2013
Title:	TEST PATTERN GENERATION FOR DIAGNOSING SCAN CHAIN FAILURES

Patent #:	9015543	Issue Dt:	04/21/2015	Application #:	13689653	Filing Dt:	11/29/2012
Publication #:	US20130166976	Pub Dt:	06/27/2013
Title:	Diagnosis-Aware Scan Chain Stitching

Patent #:	9619598	Issue Dt:	04/11/2017	Application #:	13755639	Filing Dt:	01/31/2013
Publication #:	US20140013290	Pub Dt:	01/09/2014
Title:	Input Space Reduction for Verification Test Set Generation

Patent #:	8694952	Issue Dt:	04/08/2014	Application #:	13770995	Filing Dt:	02/19/2013
Publication #:	US20130226531	Pub Dt:	08/29/2013
Title:	DESIGNING WIRING HARNESSES

Patent #:	8843861	Issue Dt:	09/23/2014	Application #:	13771057	Filing Dt:	02/19/2013
Publication #:	US20130318484	Pub Dt:	11/28/2013
Title:	THIRD PARTY COMPONENT DEBUGGING FOR INTEGRATED CIRCUIT DESIGN

Patent #:	9097755	Issue Dt:	08/04/2015	Application #:	13781676	Filing Dt:	02/28/2013
Publication #:	US20130275074	Pub Dt:	10/17/2013
Title:	GENERATING TRANSMISSION-CODE COMPLIANT TEST SEQUENCES

Patent #:	9009553	Issue Dt:	04/14/2015	Application #:	13919991	Filing Dt:	06/17/2013
Publication #:	US20140372819	Pub Dt:	12/18/2014
Title:	Scan Chain Configuration For Test-Per-Clock Based On Circuit Topology

Patent #:	8645118	Issue Dt:	02/04/2014	Application #:	13924810	Filing Dt:	06/24/2013
Publication #:	US20130289969	Pub Dt:	10/31/2013
Title:	FAULT SUPPORT IN AN EMULATION ENVIRONMENT

Patent #:	9389945	Issue Dt:	07/12/2016	Application #:	14022216	Filing Dt:	09/09/2013
Title:	Test Access Architecture For Stacked Dies

Patent #:	9086454	Issue Dt:	07/21/2015	Application #:	14053322	Filing Dt:	10/14/2013
Publication #:	US20140047404	Pub Dt:	02/13/2014
Title:	TIMING-AWARE TEST GENERATION AND FAULT SIMULATION

Patent #:	9015647	Issue Dt:	04/21/2015	Application #:	14149564	Filing Dt:	01/07/2014
Publication #:	US20140123098	Pub Dt:	05/01/2014
Title:	DYNAMIC PRINTED CIRCUIT BOARD DESIGN REUSE

Patent #:	9262567	Issue Dt:	02/16/2016	Application #:	14178973	Filing Dt:	02/12/2014
Publication #:	US20140236562	Pub Dt:	08/21/2014
Title:	Resource Mapping in a Hardware Emulation Environment

Patent #:	9747398	Issue Dt:	08/29/2017	Application #:	14254765	Filing Dt:	04/16/2014
Publication #:	US20140317583	Pub Dt:	10/23/2014
Title:	MANAGING AND CONTROLLING THE USE OF HARDWARE RESOURCES ON INTEGRATED CIRCUITS

Patent #:	9720038	Issue Dt:	08/01/2017	Application #:	14281231	Filing Dt:	05/19/2014
Publication #:	US20140347088	Pub Dt:	11/27/2014
Title:	Method and Circuit Of Pulse-Vanishing Test

Patent #:	9117044	Issue Dt:	08/25/2015	Application #:	14331434	Filing Dt:	07/15/2014
Publication #:	US20150026654	Pub Dt:	01/22/2015
Title:	HIERARCHICAL VERIFICATION OF CLOCK DOMAIN CROSSINGS

Patent #:	9679095	Issue Dt:	06/13/2017	Application #:	14493089	Filing Dt:	09/22/2014
Title:	Layout Decomposition For Multiple Patterning Lithography

Patent #:	10402519	Issue Dt:	09/03/2019	Application #:	14537440	Filing Dt:	11/10/2014
Publication #:	US20150169812	Pub Dt:	06/18/2015
Title:	Coherent State Among Multiple Simulation Models In An EDA Simulation Environment

Patent #:	NONE	Issue Dt:		Application #:	14610725	Filing Dt:	01/30/2015
Publication #:	US20150213069	Pub Dt:	07/30/2015
Title:	Tag Based System For Leveraging Design Data

Patent #:	9773085	Issue Dt:	09/26/2017	Application #:	14610948	Filing Dt:	01/30/2015
Publication #:	US20150347632	Pub Dt:	12/03/2015
Title:	SYSTEM DESIGN MANAGEMENT

Patent #:	9195786	Issue Dt:	11/24/2015	Application #:	14641922	Filing Dt:	03/09/2015
Publication #:	US20150178426	Pub Dt:	06/25/2015
Title:	HARDWARE SIMULATION CONTROLLER, SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION

Patent #:	9817929	Issue Dt:	11/14/2017	Application #:	14664763	Filing Dt:	03/20/2015
Title:	FORMAL VERIFICATION USING MICROTRANSACTIONS

Patent #:	10185799	Issue Dt:	01/22/2019	Application #:	14693851	Filing Dt:	04/22/2015
Publication #:	US20160055289	Pub Dt:	02/25/2016
Title:	Verification Of Photonic Integrated Circuits

Patent #:	9626474	Issue Dt:	04/18/2017	Application #:	14789088	Filing Dt:	07/01/2015
Publication #:	US20150302137	Pub Dt:	10/22/2015
Title:	Expanded Canonical Forms Of Layout Patterns

Patent #:	10380299	Issue Dt:	08/13/2019	Application #:	14873008	Filing Dt:	10/01/2015
Publication #:	US20160018979	Pub Dt:	01/21/2016
Title:	CLOCK TREE SYNTHESIS GRAPHICAL USER INTERFACE

Patent #:	10348509	Issue Dt:	07/09/2019	Application #:	14964192	Filing Dt:	12/09/2015
Publication #:	US20170134175	Pub Dt:	05/11/2017
Title:	TOLERANT OF ABSOLUTE OFFSETS PHYSICAL UNCLONABLE FUNCTION DEVICE

Patent #:	10664637	Issue Dt:	05/26/2020	Application #:	14981524	Filing Dt:	12/28/2015
Publication #:	US20170185710	Pub Dt:	06/29/2017
Title:	TESTBENCH RESTORATION BASED ON CAPTURE AND REPLAY

Patent #:	10444734	Issue Dt:	10/15/2019	Application #:	15002239	Filing Dt:	01/20/2016
Publication #:	US20160136899	Pub Dt:	05/19/2016
Title:	DESIGN AND MANUFACTURE OF NON-RECTILINEAR FEATURES

Patent #:	9996651	Issue Dt:	06/12/2018	Application #:	15074996	Filing Dt:	03/18/2016
Publication #:	US20160203252	Pub Dt:	07/14/2016
Title:	MASK CREATION WITH HIERARCHY MANAGEMENT USING COVER CELLS

Patent #:	9857421	Issue Dt:	01/02/2018	Application #:	15146761	Filing Dt:	05/04/2016
Publication #:	US20160245866	Pub Dt:	08/25/2016
Title:	DYNAMIC DESIGN PARTITIONING FOR DIAGNOSIS

Patent #:	9977856	Issue Dt:	05/22/2018	Application #:	15174914	Filing Dt:	06/06/2016
Publication #:	US20170004250	Pub Dt:	01/05/2017
Title:	INTEGRATED CIRCUIT LAYOUT DESIGN METHODOLOGY WITH PROCESS VARIATION BANDS

Patent #:	10740506	Issue Dt:	08/11/2020	Application #:	15181152	Filing Dt:	06/13/2016
Publication #:	US20160371409	Pub Dt:	12/22/2016
Title:	STATISTICAL CHANNEL ANALYSIS WITH CORRELATED MULTIPLE-LEVEL INPUT MODULATION

Patent #:	10496779	Issue Dt:	12/03/2019	Application #:	15263014	Filing Dt:	09/12/2016
Publication #:	US20170103158	Pub Dt:	04/13/2017
Title:	GENERATING ROOT CAUSE CANDIDATES FOR YIELD ANALYSIS

Patent #:	10157089	Issue Dt:	12/18/2018	Application #:	15433912	Filing Dt:	02/15/2017
Publication #:	US20170262324	Pub Dt:	09/14/2017
Title:	EVENT QUEUE MANAGEMENT FOR EMBEDDED SYSTEMS

Patent #:	NONE	Issue Dt:		Application #:	15646003	Filing Dt:	07/10/2017
Publication #:	US20180032357	Pub Dt:	02/01/2018
Title:	DEBUG ENVIRONMENT FOR A MULTI USER HARDWARE ASSISTED VERIFICATION SYSTEM

Patent #:	10521544	Issue Dt:	12/31/2019	Application #:	15792101	Filing Dt:	10/24/2017
Publication #:	US20180113972	Pub Dt:	04/26/2018
Title:	Traffic Shaping In Networking System-On-Chip Verification

Patent #:	10476740	Issue Dt:	11/12/2019	Application #:	15925649	Filing Dt:	03/19/2018
Title:	Data Generation For Streaming Networks In Circuits

Assignor

MENTOR GRAPHICS CORPORATION

Exec Dt:

12/30/2020

Newly Merged Entity Data

SIEMENS INDUSTRY SOFTWARE INC.

Exec Dt:

12/30/2020

Newly Merged Entity's New Name

SIEMENS INDUSTRY SOFTWARE INC.

5800 GRANITE PARKWAY, SUITE 600

PLANO, TEXAS 75024

Correspondence name and address
	SIEMENS CORPORATION IP DEPT - MAIL CODE INT-244
	3850 QUADRANGLE BOULEVARD
	ORLANDO, FL 32817

Search Results as of: 06/01/2024 04:24 AM

If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6

Web interface last modified: August 25, 2017 v.2.6