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Reel/Frame:035390/0388   Pages: 247
Recorded: 04/03/2015
Attorney Dkt #:040981-0072
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 5804
Page 27 of 59
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
1
Patent #:
Issue Dt:
10/19/2004
Application #:
10459072
Filing Dt:
06/11/2003
Title:
METHOD FOR COMPOSING A DIELECTRIC LAYER WITHIN AN INTERCONNECT STRUCTURE OF A MULTILAYER SEMICONDUCTOR DEVICE
2
Patent #:
Issue Dt:
03/22/2005
Application #:
10459158
Filing Dt:
06/11/2003
Publication #:
Pub Dt:
12/16/2004
Title:
METHOD AND APPARATUS FOR AUTOMATICALLY CONFIGURING AND/OR INSERTING CHIP RESOURCES FOR MANUFACTURING TESTS
3
Patent #:
Issue Dt:
10/19/2004
Application #:
10461255
Filing Dt:
06/13/2003
Title:
SEMICONDUCTOR WAFER CHUCK ASSEMBLY FOR A SEMICONDUCTOR PROCESSING DEVICE
4
Patent #:
Issue Dt:
05/01/2007
Application #:
10461780
Filing Dt:
06/13/2003
Publication #:
Pub Dt:
12/16/2004
Title:
METHOD AND/OR APPARATUS FOR DETERMINING MINIMUM POSITIVE REFERENCE INDICES FOR A DIRECT PREDICTION MODE
5
Patent #:
Issue Dt:
03/23/2004
Application #:
10462524
Filing Dt:
06/16/2003
Publication #:
Pub Dt:
11/13/2003
Title:
INTEGRATED CIRCUIT CONTAINING REDUNDANT CORE AND PERIPHERAL CONTACTS
6
Patent #:
Issue Dt:
11/08/2005
Application #:
10464178
Filing Dt:
06/18/2003
Title:
MULTI-CHIP PACKAGE HAVING A CONTIGUOUS HEAT SPREADER ASSEMBLY
7
Patent #:
Issue Dt:
10/25/2005
Application #:
10465186
Filing Dt:
06/19/2003
Publication #:
Pub Dt:
12/23/2004
Title:
DESIGNING AND TESTING THE INTERCONNECTION OF ADDRESSABLE DEVICES OF INTEGRATED CIRCUITS
8
Patent #:
Issue Dt:
05/26/2009
Application #:
10511211
Filing Dt:
10/13/2004
Publication #:
Pub Dt:
10/20/2005
Title:
MULTITRACK OPTICAL DISC READER
9
Patent #:
Issue Dt:
03/06/2007
Application #:
10513505
Filing Dt:
11/04/2004
Publication #:
Pub Dt:
10/27/2005
Title:
ANTENNA ARRANGEMENT AND MODULE INCLUDING THE ARRANGEMENT
10
Patent #:
Issue Dt:
06/24/2008
Application #:
10537601
Filing Dt:
06/03/2005
Publication #:
Pub Dt:
01/26/2006
Title:
METHOD AND APPARATUS FOR TRUE DIVERSITY RECEPTION WITH SINGLE ANTENNA
11
Patent #:
Issue Dt:
10/21/2008
Application #:
10558145
Filing Dt:
11/21/2005
Publication #:
Pub Dt:
11/02/2006
Title:
OPERATING LONG ON-CHIP BUSES
12
Patent #:
Issue Dt:
03/03/2009
Application #:
10600079
Filing Dt:
06/20/2003
Publication #:
Pub Dt:
12/23/2004
Title:
DUAL BLOCK MOTION VECTOR STORAGE IN COMPRESSED FORM
13
Patent #:
Issue Dt:
11/23/2004
Application #:
10600665
Filing Dt:
06/20/2003
Publication #:
Pub Dt:
12/25/2003
Title:
METHOD OF CHEMICALLY ALTERING A SILICON SURFACE AND ASSOCIATED ELECTRICAL DEVICES
14
Patent #:
Issue Dt:
08/04/2009
Application #:
10601175
Filing Dt:
06/19/2003
Publication #:
Pub Dt:
01/06/2005
Title:
CONFIGURABLE, FAST, 32-BIT CRC GENERATOR FOR 1-BYTE TO 16-BYTES VARIABLE WIDTH INPUT DATA
15
Patent #:
Issue Dt:
06/26/2007
Application #:
10601265
Filing Dt:
06/19/2003
Publication #:
Pub Dt:
12/30/2004
Title:
METHOD FOR RECOVERING DATA FROM A REDUNDANT STORAGE OBJECT
16
Patent #:
Issue Dt:
10/11/2005
Application #:
10602357
Filing Dt:
06/23/2003
Publication #:
Pub Dt:
12/23/2004
Title:
METHOD OF SCREENING DEFECTS USING LOW VOLTAGE IDDQ MEASUREMENT
17
Patent #:
Issue Dt:
07/27/2004
Application #:
10602510
Filing Dt:
06/24/2003
Publication #:
Pub Dt:
04/29/2004
Title:
INTEGRATION OF SEMICONDUCTOR ON IMPLANTED INSULATOR
18
Patent #:
Issue Dt:
03/28/2006
Application #:
10602570
Filing Dt:
06/24/2003
Publication #:
Pub Dt:
01/06/2005
Title:
PROCESS FOR DESIGNING COMPARATORS AND ADDERS OF SMALL DEPTH
19
Patent #:
Issue Dt:
06/13/2006
Application #:
10602937
Filing Dt:
06/24/2003
Publication #:
Pub Dt:
12/30/2004
Title:
TIMING CONSTRAINT GENERATOR
20
Patent #:
Issue Dt:
10/23/2007
Application #:
10603905
Filing Dt:
06/25/2003
Publication #:
Pub Dt:
12/30/2004
Title:
METHOD AND APPARATUS FOR EXPOSING PRE-DIFFUSED IP BLOCKS IN A SEMICONDUCTOR DEVICE FOR PROTOTYPING BASED ON HARDWARE EMULATION
21
Patent #:
Issue Dt:
04/11/2006
Application #:
10606138
Filing Dt:
06/25/2003
Publication #:
Pub Dt:
12/30/2004
Title:
METHOD AND APPARATUS OF AUTOMATIC POWER MANAGEMENT CONTROL FOR SERIAL ATA INTERFACE
22
Patent #:
Issue Dt:
06/28/2011
Application #:
10606731
Filing Dt:
06/26/2003
Publication #:
Pub Dt:
12/30/2004
Title:
METHOD AND/OR APPARATUS FOR DECODING AN INTRA-ONLY MPEG-2 STREAM COMPOSED OF TWO SEPARATE FIELDS ENCODED AS A SPECIAL FRAME PICTURE
23
Patent #:
Issue Dt:
12/27/2005
Application #:
10607116
Filing Dt:
06/26/2003
Publication #:
Pub Dt:
12/30/2004
Title:
METHOD AND APPARATUS TO ADD SLURRY TO A POLISHING SYSTEM
24
Patent #:
Issue Dt:
12/14/2004
Application #:
10607353
Filing Dt:
06/26/2003
Title:
METHOD AND APPARATUS FOR REMOVING WATER VAPOR AS A BYPRODUCT OF CHEMICAL REACTION IN A WAFER PROCESSING CHAMBER
25
Patent #:
Issue Dt:
06/28/2005
Application #:
10608707
Filing Dt:
06/27/2003
Publication #:
Pub Dt:
12/30/2004
Title:
SYSTEMS AND METHODS FOR EVALUATING A CHARGE STATE OF A BATTERY BASED ON OPTICAL PROPERTIES OF THE BATTERY ELECTROLYTE MATERIAL
26
Patent #:
Issue Dt:
10/11/2005
Application #:
10610619
Filing Dt:
06/30/2003
Publication #:
Pub Dt:
12/30/2004
Title:
TRANSPARENT SWITCH
27
Patent #:
Issue Dt:
08/07/2007
Application #:
10614307
Filing Dt:
07/02/2003
Publication #:
Pub Dt:
01/06/2005
Title:
INTEGRATED CIRCUIT WITH INDUCTOR HAVING HORIZONTAL MAGNETIC FLUX LINES
28
Patent #:
Issue Dt:
12/28/2004
Application #:
10614402
Filing Dt:
07/03/2003
Title:
INTEGRATD CIRCUIT DESIGN FOR BOTH INPUT OUTPUT LIMITED AND CORE LIMITED INTEGRATED CIRCUITS
29
Patent #:
Issue Dt:
04/19/2005
Application #:
10614776
Filing Dt:
07/07/2003
Publication #:
Pub Dt:
01/15/2004
Title:
PROCESS FOR PLANARIZING UPPER SURFACE OF DAMASCENE WIRING STRUCTURE FOR INTEGRATED CIRCUIT STRUCTURES
30
Patent #:
Issue Dt:
07/03/2007
Application #:
10614956
Filing Dt:
07/08/2003
Publication #:
Pub Dt:
01/13/2005
Title:
APPARATUS AND METHODS FOR IMPROVED INPUT/OUTPUT CELLS
31
Patent #:
Issue Dt:
11/01/2005
Application #:
10615039
Filing Dt:
07/08/2003
Publication #:
Pub Dt:
01/08/2004
Title:
LOW TEMPERATURE COEFFICIENT RESISTOR
32
Patent #:
Issue Dt:
06/01/2004
Application #:
10615063
Filing Dt:
07/08/2003
Title:
ISOLATED STRIPLINE STRUCTURE
33
Patent #:
Issue Dt:
01/24/2006
Application #:
10615558
Filing Dt:
07/08/2003
Publication #:
Pub Dt:
01/13/2005
Title:
HARD MASK REMOVAL
34
Patent #:
Issue Dt:
08/22/2006
Application #:
10616623
Filing Dt:
07/10/2003
Publication #:
Pub Dt:
01/13/2005
Title:
OPTIMIZING IC CLOCK STRUCTURES BY MINIMIZING CLOCK UNCERTAINTY
35
Patent #:
Issue Dt:
01/12/2010
Application #:
10619531
Filing Dt:
07/15/2003
Publication #:
Pub Dt:
01/20/2005
Title:
INTRA ESTIMATION CHROMA MODE 0 SUB-BLOCK DEPENDENT PREDICTION
36
Patent #:
Issue Dt:
07/04/2006
Application #:
10619978
Filing Dt:
07/14/2003
Publication #:
Pub Dt:
04/15/2004
Title:
PROCESS FOR REMOVAL OF PHOTORESIST MASK USED FOR MAKING VIAS IN LOW K CARBON-DOPED SILICON OXIDE DIELECTRIC MATERIAL, AND FOR REMOVAL OF ETCH RESIDUES FROM FORMATION OF VIAS AND REMOVAL OF PHOTORESIST MASK
37
Patent #:
Issue Dt:
09/20/2005
Application #:
10620057
Filing Dt:
07/15/2003
Publication #:
Pub Dt:
12/16/2004
Title:
MEASUREMENT OF PACKAGE INTERCONNECT IMPEDANCE USING TESTER AND SUPPORTING TESTER
38
Patent #:
Issue Dt:
08/23/2005
Application #:
10620074
Filing Dt:
07/14/2003
Title:
SEMICONDUCTOR PACKAGE HAVING A THERMALLY AND ELECTRICALLY CONNECTED HEATSPREADER
39
Patent #:
Issue Dt:
07/18/2006
Application #:
10620105
Filing Dt:
07/15/2003
Publication #:
Pub Dt:
01/20/2005
Title:
METHOD TO MAINTAIN DATA INTEGRITY DURING FLASH FILE TRANSFER TO RAID CONTROLLER FLASH USING A TERMINAL EMULATION PROGRAM
40
Patent #:
Issue Dt:
06/22/2010
Application #:
10620581
Filing Dt:
07/15/2003
Publication #:
Pub Dt:
01/20/2005
Title:
FLEXIBLE ARCHITECTURE COMPONENT (FAC) FOR EFFICIENT DATA INTEGRATION AND INFORMATION INTERCHANGE USING WEB SERVICES
41
Patent #:
Issue Dt:
06/12/2007
Application #:
10620680
Filing Dt:
07/15/2003
Publication #:
Pub Dt:
01/20/2005
Title:
DEBUGGING WITH SET VERBOSITY LEVEL DURING READ & ANALYSIS OF EXECUTABLE CODE AND ASSOCIATED COMMENTS WHILE LOGGING ACCORDING TO SET VERBOSITY LEVEL
42
Patent #:
Issue Dt:
07/25/2006
Application #:
10621737
Filing Dt:
07/17/2003
Publication #:
Pub Dt:
01/20/2005
Title:
METHOD AND APPARATUS OF IC IMPLEMENTATION BASED ON C++ LANGUAGE DESCRIPTION
43
Patent #:
Issue Dt:
03/07/2006
Application #:
10623329
Filing Dt:
07/18/2003
Publication #:
Pub Dt:
01/20/2005
Title:
INTRA 4 X 4 MODES 3, 7 AND 8 AVAILABILITY DETERMINATION INTRA ESTIMATION AND COMPENSATION
44
Patent #:
Issue Dt:
03/30/2010
Application #:
10624253
Filing Dt:
07/22/2003
Publication #:
Pub Dt:
01/27/2005
Title:
METHOD AND/OR CIRCUIT FOR BINARY ARITHMETIC DECODING DECISIONS BEFORE TERMINATION
45
Patent #:
Issue Dt:
04/22/2008
Application #:
10624264
Filing Dt:
07/22/2003
Publication #:
Pub Dt:
01/27/2005
Title:
INTEGRATED CIRCUIT WITH ON-CHIP CLOCK FREQUENCY MATCHING TO UPSTREAM HEAD END EQUIPMENT
46
Patent #:
Issue Dt:
08/22/2006
Application #:
10624347
Filing Dt:
07/22/2003
Publication #:
Pub Dt:
01/27/2005
Title:
METHODS AND SYSTEMS FOR AUTOMATIC VERIFICATION OF SPECIFICATION DOCUMENT TO HARDWARE DESIGN
47
Patent #:
Issue Dt:
06/06/2006
Application #:
10626825
Filing Dt:
07/23/2003
Publication #:
Pub Dt:
07/15/2004
Title:
ARCHITECTURE FOR A SEA OF PLATFORMS
48
Patent #:
Issue Dt:
10/25/2005
Application #:
10627289
Filing Dt:
07/25/2003
Publication #:
Pub Dt:
01/27/2005
Title:
LOW GATE RESISTANCE LAYOUT PROCEDURE FOR RF TRANSISTOR DEVICES
49
Patent #:
Issue Dt:
02/24/2009
Application #:
10628194
Filing Dt:
07/28/2003
Publication #:
Pub Dt:
02/03/2005
Title:
STANDARD ATA QUEUING AUTOMATION IN SERIAL ATA INTERFACE FOR CREATING A FRAME INFORMATION STRUCTURE (FIS) CORRESPONDING TO COMMAND FROM TRANSPORT LAYER
50
Patent #:
Issue Dt:
09/13/2005
Application #:
10628601
Filing Dt:
07/28/2003
Publication #:
Pub Dt:
04/15/2004
Title:
METHOD AND APPARATUS FOR DETECTING BACKSIDE CONTAMINATION DURING FABRICATION OF A SEMICONDUCTOR WAFER
51
Patent #:
Issue Dt:
06/28/2011
Application #:
10628614
Filing Dt:
07/28/2003
Publication #:
Pub Dt:
02/03/2005
Title:
WAFER EDGE DEFECT INSPECTION USING CAPTURED IMAGE ANALYSIS
52
Patent #:
Issue Dt:
01/10/2006
Application #:
10628986
Filing Dt:
07/28/2003
Publication #:
Pub Dt:
02/03/2005
Title:
METHOD OF MAPPING LOGIC FAILURES IN AN INTEGRATED CIRCUIT DIE
53
Patent #:
Issue Dt:
11/16/2004
Application #:
10629496
Filing Dt:
07/29/2003
Title:
SELECTIVE HIGH K DIELECTRICS REMOVAL
54
Patent #:
Issue Dt:
09/06/2005
Application #:
10629507
Filing Dt:
07/29/2003
Publication #:
Pub Dt:
02/03/2005
Title:
VIDEO DECODING DURING I-FRAME DECODE AT RESOLUTION CHANGE
55
Patent #:
Issue Dt:
10/19/2004
Application #:
10631328
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
06/24/2004
Title:
METHOD OF BALANCED COEFFICIENT OF THERMAL EXPANSION FOR FLIP CHIP BALL GRID ARRAY
56
Patent #:
Issue Dt:
09/21/2004
Application #:
10631528
Filing Dt:
07/31/2003
Title:
METHOD AND APPARATUS FOR REDUCING MICROTRENCHING FOR BORDERLESS VIAS CREATED IN A DUAL DAMASCENE PROCESS
57
Patent #:
Issue Dt:
07/25/2006
Application #:
10631610
Filing Dt:
07/31/2003
Publication #:
Pub Dt:
02/03/2005
Title:
METHOD AND APPARATUS FOR MEASURING HIGH SPEED GLITCH ENERGY IN AN INTEGRATED CIRCUIT
58
Patent #:
Issue Dt:
04/29/2008
Application #:
10632881
Filing Dt:
07/31/2003
Publication #:
Pub Dt:
02/03/2005
Title:
METHOD AND APPARATUS FOR CONTROLLING SAS/FIBRE TARGET BEHAVIOR FROM A HOST
59
Patent #:
Issue Dt:
01/13/2009
Application #:
10633224
Filing Dt:
07/31/2003
Publication #:
Pub Dt:
02/03/2005
Title:
CLOSED-LOOP SYSTEM FOR MASTERING, CERTIFICATION AND PRODUCTION OF COMPACT DISCS
60
Patent #:
Issue Dt:
01/17/2006
Application #:
10633856
Filing Dt:
08/04/2003
Publication #:
Pub Dt:
02/10/2005
Title:
UNIVERSAL GATES FOR ICS AND TRANSFORMATION OF NETLISTS FOR THEIR IMPLEMENTATION
61
Patent #:
Issue Dt:
02/20/2007
Application #:
10634416
Filing Dt:
08/04/2003
Publication #:
Pub Dt:
02/10/2005
Title:
METHOD AND APPARATUS FOR INTEGRATING SIX SIGMA METHODOLOGY INTO INSPECTION RECEIVING PROCESS OF OUTSOURCED SUBASSEMBLIES, PARTS, AND MATERIALS: ACCEPTANCE, REJECTION, TRENDING, TRACKING AND CLOSED LOOP CORRECTIVE ACTION
62
Patent #:
Issue Dt:
05/23/2006
Application #:
10634634
Filing Dt:
08/04/2003
Publication #:
Pub Dt:
02/10/2005
Title:
METHOD AND APPARATUS FOR MAPPING PLATFORM-BASED DESIGN TO MULTIPLE FOUNDRY PROCESSES
63
Patent #:
Issue Dt:
05/04/2010
Application #:
10635015
Filing Dt:
08/04/2003
Publication #:
Pub Dt:
02/10/2005
Title:
3-PRONG SECURITY/RELIABILITY/REAL-TIME DISTRIBUTED ARCHITECTURE OF INFORMATION HANDLING SYSTEM
64
Patent #:
Issue Dt:
12/07/2004
Application #:
10635276
Filing Dt:
08/06/2003
Title:
SUBSTRATE VOLTAGE CONNECTION
65
Patent #:
Issue Dt:
06/27/2006
Application #:
10637385
Filing Dt:
08/08/2003
Publication #:
Pub Dt:
02/10/2005
Title:
METHOD TO IMPROVE THE CONTROL OF ELECTRO-POLISHING BY USE OF A PLATING ELECTRODE AN ELECTROLYTE BATH
66
Patent #:
Issue Dt:
02/22/2005
Application #:
10638772
Filing Dt:
08/11/2003
Publication #:
Pub Dt:
04/08/2004
Title:
MULTI CHIP MODULE
67
Patent #:
Issue Dt:
06/19/2007
Application #:
10639338
Filing Dt:
08/12/2003
Publication #:
Pub Dt:
02/17/2005
Title:
REDUCED COMPLEXITY EFFICIENT BINARIZATION METHOD AND/OR CIRCUIT FOR MOTION VECTOR RESIDUALS
68
Patent #:
Issue Dt:
11/07/2006
Application #:
10639701
Filing Dt:
08/12/2003
Publication #:
Pub Dt:
02/17/2005
Title:
STATIC TIMING ANALYSIS APPROACH FOR MULTI-CLOCK DOMAIN DESIGNS
69
Patent #:
Issue Dt:
08/02/2005
Application #:
10640738
Filing Dt:
08/13/2003
Publication #:
Pub Dt:
02/17/2005
Title:
METHOD OF ROUTING A REDISTRIBUTION LAYER TRACE IN AN INTEGRATED CIRCUIT DIE
70
Patent #:
Issue Dt:
09/13/2005
Application #:
10640778
Filing Dt:
08/13/2003
Publication #:
Pub Dt:
02/19/2004
Title:
METHOD OF DETECTING SPATIALLY CORRELATED VARIATIONS IN A PARAMETER OF AN INTEGRATED CIRCUIT DIE
71
Patent #:
Issue Dt:
01/17/2006
Application #:
10641768
Filing Dt:
08/14/2003
Title:
METHOD AND STRUCTURE FOR CREATING ULTRA LOW RESISTANCE DAMASCENE COPPER WIRING
72
Patent #:
Issue Dt:
11/30/2004
Application #:
10641799
Filing Dt:
08/15/2003
Title:
SYSTEM FOR YIELD ENHANCEMENT IN PROGRAMMABLE LOGIC
73
Patent #:
Issue Dt:
01/31/2006
Application #:
10642706
Filing Dt:
08/18/2003
Publication #:
Pub Dt:
09/23/2004
Title:
INSULATED BONDING WIRE TOOL FOR MICROELECTRONIC PACKAGING
74
Patent #:
Issue Dt:
05/29/2007
Application #:
10642954
Filing Dt:
08/18/2003
Publication #:
Pub Dt:
02/24/2005
Title:
METHODS AND SYSTEMS FOR END-TO-END DATA PROTECTION IN A MEMORY CONTROLLER
75
Patent #:
Issue Dt:
11/28/2006
Application #:
10643463
Filing Dt:
08/19/2003
Publication #:
Pub Dt:
02/24/2005
Title:
TYPE CONFIGURABLE MEMORY METHODOLOGY FOR USE WITH METAL PROGRAMMABLE DEVICES
76
Patent #:
Issue Dt:
07/19/2005
Application #:
10643687
Filing Dt:
08/19/2003
Publication #:
Pub Dt:
05/13/2004
Title:
HIGH-K DIELECTRIC GATE MATERIAL UNIQUELY FORMED
77
Patent #:
Issue Dt:
07/17/2007
Application #:
10644116
Filing Dt:
08/20/2003
Publication #:
Pub Dt:
02/24/2005
Title:
WHOLE-WAFER PHOTOEMISSION ANALYSIS
78
Patent #:
Issue Dt:
12/19/2006
Application #:
10645900
Filing Dt:
08/20/2003
Publication #:
Pub Dt:
02/24/2005
Title:
METHOD AND CIRCUIT FOR SCAN TESTING LATCH BASED RANDOM ACCESS MEMORY
79
Patent #:
Issue Dt:
12/04/2007
Application #:
10646535
Filing Dt:
08/22/2003
Title:
SYSTEM AND METHOD FOR EFFICIENTLY TESTING A LARGE RANDOM ACCESS MEMORY SPACE
80
Patent #:
Issue Dt:
08/31/2004
Application #:
10646570
Filing Dt:
08/22/2003
Title:
MICROCHANNEL FORMATION FOR FUSES, INTERCONNECTS, CAPACITORS, AND INDUCTORS
81
Patent #:
Issue Dt:
12/12/2006
Application #:
10647863
Filing Dt:
08/25/2003
Publication #:
Pub Dt:
03/03/2005
Title:
ZERO CAPACITANCE BONDPAD UTILIZING ACTIVE NEGATIVE CAPACITANCE
82
Patent #:
Issue Dt:
05/24/2005
Application #:
10647993
Filing Dt:
08/26/2003
Publication #:
Pub Dt:
03/03/2005
Title:
SHARING FUSE BLOCKS BETWEEN MEMORIES IN HARD-BISR
83
Patent #:
Issue Dt:
12/04/2007
Application #:
10648038
Filing Dt:
08/26/2003
Publication #:
Pub Dt:
03/03/2005
Title:
MEMORY MAPPING FOR PARALLEL TURBO DECODING
84
Patent #:
Issue Dt:
06/27/2006
Application #:
10648054
Filing Dt:
08/26/2003
Publication #:
Pub Dt:
03/03/2005
Title:
MULTI-LAYER STAGGERED POWER BUS LAYOUT DESIGN
85
Patent #:
Issue Dt:
04/26/2005
Application #:
10648602
Filing Dt:
08/25/2003
Title:
FORMING COPPER INTERCONNECTS WITH SN COATINGS
86
Patent #:
Issue Dt:
08/01/2006
Application #:
10648967
Filing Dt:
08/27/2003
Publication #:
Pub Dt:
03/03/2005
Title:
MEMORY WINDOW MANAGER FOR CONTROL STRUCTURE ACCESS
87
Patent #:
Issue Dt:
07/11/2006
Application #:
10649215
Filing Dt:
08/26/2003
Publication #:
Pub Dt:
03/03/2005
Title:
METHODOLOGY FOR GENERATING A MODIFIED VIEW OF A CIRCUIT LAYOUT
88
Patent #:
Issue Dt:
02/28/2006
Application #:
10650192
Filing Dt:
08/27/2003
Publication #:
Pub Dt:
03/03/2005
Title:
DESIGN AND USE OF A SPACER CELL TO SUPPORT RECONFIGURABLE MEMORIES
89
Patent #:
Issue Dt:
06/27/2006
Application #:
10650395
Filing Dt:
08/28/2003
Publication #:
Pub Dt:
03/03/2005
Title:
HIGH QUALITY FACTOR SPIRAL INDUCTOR THAT UTILIZES ACTIVE NEGATIVE CAPACITANCE
90
Patent #:
Issue Dt:
06/13/2006
Application #:
10651742
Filing Dt:
08/29/2003
Publication #:
Pub Dt:
03/17/2005
Title:
METHODS AND STRUCTURE FOR PCI BUS BROADCAST USING DEVICE ID MESSAGING
91
Patent #:
Issue Dt:
03/21/2006
Application #:
10652007
Filing Dt:
08/29/2003
Publication #:
Pub Dt:
05/12/2005
Title:
LOW DIELECTRIC CONSTANT FLUORINE AND CARBON-CONTAINING SILICON OXIDE DIELECTRIC MATERIAL CHARACTERIZED BY IMPROVED RESISTANCE TO OXIDATION
92
Patent #:
Issue Dt:
08/30/2005
Application #:
10652369
Filing Dt:
08/29/2003
Publication #:
Pub Dt:
03/03/2005
Title:
VOLTAGE CONTRAST MONITOR FOR INTEGRATED CIRCUIT DEFECTS
93
Patent #:
Issue Dt:
07/11/2006
Application #:
10653588
Filing Dt:
09/02/2003
Publication #:
Pub Dt:
03/03/2005
Title:
WIDELY TUNEABLE AND FULLY DIFFERENTIAL LC OSCILLATOR UTILIZING AN ACTIVE INDUCTOR
94
Patent #:
Issue Dt:
09/13/2005
Application #:
10653593
Filing Dt:
09/02/2003
Publication #:
Pub Dt:
03/03/2005
Title:
WIDELY TUNABLE RING OSCILLATOR UTILIZING ACTIVE NEGATIVE CAPACITANCE
95
Patent #:
Issue Dt:
08/23/2005
Application #:
10655053
Filing Dt:
09/03/2003
Publication #:
Pub Dt:
03/03/2005
Title:
RECONFIGURABLE MEMORY ARRAYS
96
Patent #:
Issue Dt:
06/20/2006
Application #:
10655191
Filing Dt:
09/04/2003
Publication #:
Pub Dt:
03/10/2005
Title:
CONTROLLER ARCHITECTURE FOR MEMORY MAPPING
97
Patent #:
Issue Dt:
12/25/2007
Application #:
10656195
Filing Dt:
09/04/2003
Publication #:
Pub Dt:
03/10/2005
Title:
DATA STREAM FREQUENCY REDUCTION AND/OR PHASE SHIFT
98
Patent #:
Issue Dt:
03/08/2005
Application #:
10658017
Filing Dt:
09/08/2003
Publication #:
Pub Dt:
03/10/2005
Title:
METHOD OF TRANSLATING A NET DESCRIPTION OF AN INTEGRATED CIRCUIT DIE
99
Patent #:
Issue Dt:
07/18/2006
Application #:
10658168
Filing Dt:
09/08/2003
Publication #:
Pub Dt:
03/24/2005
Title:
METHOD OF QUALIFYING A PROCESS TOOL WITH WAFER DEFECT MAPS
100
Patent #:
Issue Dt:
11/21/2006
Application #:
10659134
Filing Dt:
09/10/2003
Publication #:
Pub Dt:
03/10/2005
Title:
APPARATUS AND METHOD OF MANUFACTURE FOR INTEGRATED CIRCUIT AND CMOS DEVICE INCLUDING EPITAXIALLY GROWN DIELECTRIC ON SILICON CARBIDE
Assignor
1
Exec Dt:
08/14/2014
Assignee
1
1 YISHUN AVENUE 7
SINGAPORE, SINGAPORE 768923
Correspondence name and address
LATHAM & WATKINS LLP
650 TOWN CENTER DRIVE, SUITE 2000
COSTA MESA, CA 92626

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