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Reel/Frame:	035390/0388			Pages:	247
		Recorded:	04/03/2015
Attorney Dkt #:	040981-0072
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 5804
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Patent #:	6998638	Issue Dt:	02/14/2006	Application #:	10856213	Filing Dt:	05/28/2004
Publication #:	US20040217487	Pub Dt:	11/04/2004
Title:	TEST STRUCTURE FOR DETECTING BONDING-INDUCED CRACKS

Patent #:	7065734	Issue Dt:	06/20/2006	Application #:	10859857	Filing Dt:	06/02/2004
Publication #:	US20050273751	Pub Dt:	12/08/2005
Title:	METHOD OF GENERATING MULTIPLE HARDWARE DESCRIPTION LANGUAGE CONFIGURATIONS FOR A PHASE LOCKED LOOP FROM A SINGLE GENETIC MODEL FOR INTEGRATED CIRCUIT DESIGN

Patent #:	7412678	Issue Dt:	08/12/2008	Application #:	10859874	Filing Dt:	06/02/2004
Publication #:	US20050273741	Pub Dt:	12/08/2005
Title:	METHOD AND COMPUTER PROGRAM FOR MANAGEMENT OF SYNCHRONOUS AND ASYNCHRONOUS CLOCK DOMAIN CROSSING IN INTEGRATED CIRCUIT DESIGN

Patent #:	7478303	Issue Dt:	01/13/2009	Application #:	10862039	Filing Dt:	06/04/2004
Publication #:	US20050273681	Pub Dt:	12/08/2005
Title:	SYSTEM AND METHOD FOR TESTING NODES IN A NETWORK

Patent #:	7223616	Issue Dt:	05/29/2007	Application #:	10862049	Filing Dt:	06/04/2004
Publication #:	US20050272174	Pub Dt:	12/08/2005
Title:	TEST STRUCTURES IN UNUSED AREAS OF SEMICONDUCTOR INTEGRATED CIRCUITS AND METHODS FOR DESIGNING THE SAME

Patent #:	7471337	Issue Dt:	12/30/2008	Application #:	10863908	Filing Dt:	06/09/2004
Publication #:	US20050276282	Pub Dt:	12/15/2005
Title:	METHOD OF AUDIO-VIDEO SYNCHRONIZATION

Patent #:	7436060	Issue Dt:	10/14/2008	Application #:	10865179	Filing Dt:	06/09/2004
Publication #:	US20050275086	Pub Dt:	12/15/2005
Title:	SEMICONDUCTOR PACKAGE AND PROCESS UTILIZING PRE-FORMED MOLD CAP AND HEATSPREADER ASSEMBLY

Patent #:	7039556	Issue Dt:	05/02/2006	Application #:	10867003	Filing Dt:	06/14/2004
Publication #:	US20050288896	Pub Dt:	12/29/2005
Title:	SUBSTRATE PROFILE ANALYSIS

Patent #:	7013192	Issue Dt:	03/14/2006	Application #:	10867014	Filing Dt:	06/14/2004
Publication #:	US20050278678	Pub Dt:	12/15/2005
Title:	SUBSTRATE CONTACT ANALYSIS

Patent #:	7146463	Issue Dt:	12/05/2006	Application #:	10868555	Filing Dt:	06/15/2004
Publication #:	US20050278484	Pub Dt:	12/15/2005
Title:	METHODS AND STRUCTURE FOR OPTIMIZING DISK SPACE UTILIZATION

Patent #:	7168052	Issue Dt:	01/23/2007	Application #:	10875128	Filing Dt:	06/23/2004
Publication #:	US20060010092	Pub Dt:	01/12/2006
Title:	YIELD DRIVEN MEMORY PLACEMENT SYSTEM

Patent #:	7149178	Issue Dt:	12/12/2006	Application #:	10877374	Filing Dt:	06/25/2004
Publication #:	US20040233815	Pub Dt:	11/25/2004
Title:	METHOD AND FORMAT FOR READING AND WRITING IN A MULTILEVEL OPTICAL DATA SYSTEMS

Patent #:	7205803	Issue Dt:	04/17/2007	Application #:	10879438	Filing Dt:	06/29/2004
Publication #:	US20050285653	Pub Dt:	12/29/2005
Title:	HIGH SPEED FULLY SCALEABLE, PROGRAMMABLE AND LINEAR DIGITAL DELAY CIRCUIT

Patent #:	7042296	Issue Dt:	05/09/2006	Application #:	10879443	Filing Dt:	06/29/2004
Publication #:	US20060033544	Pub Dt:	02/16/2006
Title:	DIGITAL PROGRAMMABLE DELAY SCHEME TO CONTINUOUSLY CALIBRATE AND TRACK DELAY OVER PROCESS, VOLTAGE AND TEMPERATURE

Patent #:	7198546	Issue Dt:	04/03/2007	Application #:	10879629	Filing Dt:	06/29/2004
Publication #:	US20050287927	Pub Dt:	12/29/2005
Title:	METHOD TO MONITOR PAD WEAR IN CMP PROCESSING

Patent #:	7181710	Issue Dt:	02/20/2007	Application #:	10879768	Filing Dt:	06/28/2004
Publication #:	US20050289491	Pub Dt:	12/29/2005
Title:	DEVICE FOR ESTIMATING CELL DELAY FROM A TABLE WITH ADDED VOLTAGE SWING

Patent #:	8869104	Issue Dt:	10/21/2014	Application #:	10881663	Filing Dt:	06/30/2004
Publication #:	US20060005167	Pub Dt:	01/05/2006
Title:	Object code configuration tool

Patent #:	7015096	Issue Dt:	03/21/2006	Application #:	10883137	Filing Dt:	07/01/2004
Title:	BIMETALLIC OXIDE COMPOSITIONS FOR GATE DIELECTRICS

Patent #:	7365015	Issue Dt:	04/29/2008	Application #:	10889901	Filing Dt:	07/13/2004
Publication #:	US20060011994	Pub Dt:	01/19/2006
Title:	DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING SI1-XGEX AS SACRIFICIAL MATERIAL

Patent #:	7246216	Issue Dt:	07/17/2007	Application #:	10891393	Filing Dt:	07/14/2004
Publication #:	US20060015473	Pub Dt:	01/19/2006
Title:	DYNAMIC PARTITIONING OF STORAGE MEDIA FOR MIXED APPLICATIONS

Patent #:	7071094	Issue Dt:	07/04/2006	Application #:	10893659	Filing Dt:	07/16/2004
Publication #:	US20040253784	Pub Dt:	12/16/2004
Title:	DUAL LAYER BARRIER FILM TECHNIQUES TO PREVENT RESIST POISONING

Patent #:	7415691	Issue Dt:	08/19/2008	Application #:	10894781	Filing Dt:	07/20/2004
Publication #:	US20060020927	Pub Dt:	01/26/2006
Title:	METHOD AND SYSTEM FOR OUTPUTTING A SEQUENCE OF COMMANDS AND DATA DESCRIBED BY A FLOWCHART

Patent #:	7634748	Issue Dt:	12/15/2009	Application #:	10897655	Filing Dt:	07/22/2004
Publication #:	US20060031798	Pub Dt:	02/09/2006
Title:	SPECIAL ENGINEERING CHANGE ORDER CELLS

Patent #:	7660355	Issue Dt:	02/09/2010	Application #:	10898125	Filing Dt:	07/23/2004
Publication #:	US20050147173	Pub Dt:	07/07/2005
Title:	LOW COMPLEXITY TRANSCODING BETWEEN VIDEO STREAMS USING DIFFERENT ENTROPY CODING

Patent #:	7216280	Issue Dt:	05/08/2007	Application #:	10900224	Filing Dt:	07/27/2004
Publication #:	US20050235188	Pub Dt:	10/20/2005
Title:	METHOD OF GENERATING TEST PATTERNS TO EFFICIENTLY SCREEN INLINE RESISTANCE DELAY DEFECTS IN COMPLEX ASICS

Patent #:	7308627	Issue Dt:	12/11/2007	Application #:	10900642	Filing Dt:	07/27/2004
Publication #:	US20050015651	Pub Dt:	01/20/2005
Title:	SELF-TIMED RELIABILITY AND YIELD VEHICLE WITH GATED DATA AND CLOCK

Patent #:	7096748	Issue Dt:	08/29/2006	Application #:	10900869	Filing Dt:	07/28/2004
Publication #:	US20060021453	Pub Dt:	02/02/2006
Title:	EMBEDDED STRAIN GAUGE IN PRINTED CIRCUIT BOARDS

Patent #:	7254732	Issue Dt:	08/07/2007	Application #:	10901518	Filing Dt:	07/29/2004
Publication #:	US20050005178	Pub Dt:	01/06/2005
Title:	METHOD AND APPARATUS OF AUTOMATIC POWER MANAGEMENT CONTROL FOR SERIAL ATA DEVICE DIRECTLY ATTACHED TO SAS/SATA HOST CONTROLLER

Patent #:	7330989	Issue Dt:	02/12/2008	Application #:	10901519	Filing Dt:	07/29/2004
Publication #:	US20050010831	Pub Dt:	01/13/2005
Title:	METHOD AND APPARATUS OF AUTOMATIC POWER MANAGEMENT CONTROL FOR SERIAL ATA INTERFACE UTILIZING A COMBINATION OF IOP CONTROL AND SPECIALIZED HARDWARE CONTROL

Patent #:	7010711	Issue Dt:	03/07/2006	Application #:	10901520	Filing Dt:	07/29/2004
Publication #:	US20040268169	Pub Dt:	12/30/2004
Title:	METHOD AND APPARATUS OF AUTOMATIC POWER MANAGEMENT CONTROL FOR NATIVE COMMAND QUEUING SERIAL ATA DEVICE

Patent #:	7231563	Issue Dt:	06/12/2007	Application #:	10901609	Filing Dt:	07/28/2004
Publication #:	US20050268185	Pub Dt:	12/01/2005
Title:	METHOD AND APPARATUS FOR HIGH SPEED TESTING OF LATCH BASED RANDOM ACCESS MEMORY

Patent #:	7062737	Issue Dt:	06/13/2006	Application #:	10901841	Filing Dt:	07/28/2004
Publication #:	US20060026539	Pub Dt:	02/02/2006
Title:	METHOD OF AUTOMATED REPAIR OF CROSSTALK VIOLATIONS AND TIMING VIOLATIONS IN AN INTEGRATED CIRCUIT DESIGN

Patent #:	7331028	Issue Dt:	02/12/2008	Application #:	10902987	Filing Dt:	07/30/2004
Publication #:	US20060026546	Pub Dt:	02/02/2006
Title:	ENGINEERING CHANGE ORDER SCENARIO MANAGER

Patent #:	7599501	Issue Dt:	10/06/2009	Application #:	10903069	Filing Dt:	07/30/2004
Publication #:	US20060023894	Pub Dt:	02/02/2006
Title:	SINGLE BIT PER-VOICE DRY/WET REVERB CONTROL

Patent #:	7174526	Issue Dt:	02/06/2007	Application #:	10903836	Filing Dt:	07/30/2004
Publication #:	US20060026551	Pub Dt:	02/02/2006
Title:	ACCURATE DENSITY CALCULATION WITH DENSITY VIEWS IN LAYOUT DATABASES

Patent #:	7231370	Issue Dt:	06/12/2007	Application #:	10904177	Filing Dt:	10/27/2004
Title:	METHOD AND APPARATUS FOR ORGANIZATIONAL SOFTWARE LICENSE SHARING

Patent #:	8169908	Issue Dt:	05/01/2012	Application #:	10905998	Filing Dt:	01/29/2005
Title:	METHOD FOR DISCARDING CORRUPTED DATA PACKETS IN A RELIABLE TRANSPORT FABRIC

Patent #:	7430730	Issue Dt:	09/30/2008	Application #:	10909603	Filing Dt:	08/02/2004
Publication #:	US20060022687	Pub Dt:	02/02/2006
Title:	DISABLING UNUSED IO RESOURCES IN PLATFORM-BASED INTEGRATED CIRCUITS

Patent #:	7363423	Issue Dt:	04/22/2008	Application #:	10909632	Filing Dt:	08/02/2004
Publication #:	US20060023481	Pub Dt:	02/02/2006
Title:	MULTIPLE MATCH DETECTION CIRCUIT

Patent #:	7574541	Issue Dt:	08/11/2009	Application #:	10909999	Filing Dt:	08/03/2004
Publication #:	US20060031610	Pub Dt:	02/09/2006
Title:	FIFO SUB-SYSTEM WITH IN-LINE CORRECTION

Patent #:	7461183	Issue Dt:	12/02/2008	Application #:	10910000	Filing Dt:	08/03/2004
Publication #:	US20060031600	Pub Dt:	02/09/2006
Title:	METHOD OF PROCESSING A CONTEXT FOR EXECUTION

Patent #:	7676613	Issue Dt:	03/09/2010	Application #:	10910594	Filing Dt:	08/03/2004
Publication #:	US20060031612	Pub Dt:	02/09/2006
Title:	METHODS AND STRUCTURE FOR ASSURING CORRECT DATA ORDER IN SATA TRANSMISSIONS OVER A SAS WIDE PORT

Patent #:	7061822	Issue Dt:	06/13/2006	Application #:	10911457	Filing Dt:	08/04/2004
Publication #:	US20050007837	Pub Dt:	01/13/2005
Title:	CLOCK GENERATOR FOR PSEUDO DUAL PORT MEMORY

Patent #:	7167939	Issue Dt:	01/23/2007	Application #:	10911798	Filing Dt:	08/05/2004
Publication #:	US20060031619	Pub Dt:	02/09/2006
Title:	ASYNCHRONOUS SYSTEM BUS ADAPTER FOR A COMPUTER SYSTEM HAVING A HIERARCHICAL BUS STRUCTURE

Patent #:	7334056	Issue Dt:	02/19/2008	Application #:	10914296	Filing Dt:	08/09/2004
Publication #:	US20060031602	Pub Dt:	02/09/2006
Title:	SCALABLE ARCHITECTURE FOR CONTEXT EXECUTION

Patent #:	7107561	Issue Dt:	09/12/2006	Application #:	10914657	Filing Dt:	08/09/2004
Publication #:	US20060027919	Pub Dt:	02/09/2006
Title:	METHOD OF SIZING VIA ARRAYS AND INTERCONNECTS TO REDUCE ROUTING CONGESTION IN FLIP CHIP INTEGRATED CIRCUITS

Patent #:	7168055	Issue Dt:	01/23/2007	Application #:	10914921	Filing Dt:	08/10/2004
Publication #:	US20060036982	Pub Dt:	02/16/2006
Title:	METHOD AND APPARATUS FOR DETECTING NETS PHYSICALLY CHANGED AND ELECTRICALLY AFFECTED BY DESIGN ECO

Patent #:	7081406	Issue Dt:	07/25/2006	Application #:	10915719	Filing Dt:	08/10/2004
Publication #:	US20060035455	Pub Dt:	02/16/2006
Title:	INTERCONNECT DIELECTRIC TUNING

Patent #:	7405116	Issue Dt:	07/29/2008	Application #:	10916322	Filing Dt:	08/11/2004
Publication #:	US20060035425	Pub Dt:	02/16/2006
Title:	APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPLACEMENT GATE TRANSISTOR FLOW

Patent #:	7117467	Issue Dt:	10/03/2006	Application #:	10918933	Filing Dt:	08/16/2004
Publication #:	US20060036987	Pub Dt:	02/16/2006
Title:	METHODS FOR OPTIMIZING PACKAGE AND SILICON CO-DESIGN OF INTEGRATED CIRCUIT

Patent #:	7171500	Issue Dt:	01/30/2007	Application #:	10920897	Filing Dt:	08/18/2004
Publication #:	US20060041699	Pub Dt:	02/23/2006
Title:	SYSTEMS AND METHODS FOR TARGET MODE CONNECTION MANAGEMENT IN SAS CONNECTIONS

Patent #:	7689763	Issue Dt:	03/30/2010	Application #:	10920975	Filing Dt:	08/18/2004
Publication #:	US20060041713	Pub Dt:	02/23/2006
Title:	METHOD AND SYSTEM FOR REDUCING PIN COUNT IN AN INTEGRATED CIRCUIT WHEN INTERFACING TO A MEMORY

Patent #:	8065401	Issue Dt:	11/22/2011	Application #:	10920984	Filing Dt:	08/18/2004
Publication #:	US20060039405	Pub Dt:	02/23/2006
Title:	SYSTEMS AND METHODS FOR FRAME ORDERING IN WIDE PORT SAS CONNECTIONS

Patent #:	7334042	Issue Dt:	02/19/2008	Application #:	10920987	Filing Dt:	08/18/2004
Publication #:	US20060041672	Pub Dt:	02/23/2006
Title:	SYSTEMS AND METHODS FOR INITIATOR MODE CONNECTION MANAGEMENT IN SAS CONNECTIONS

Patent #:	8612632	Issue Dt:	12/17/2013	Application #:	10921018	Filing Dt:	08/18/2004
Publication #:	US20060039406	Pub Dt:	02/23/2006
Title:	SYSTEMS AND METHODS FOR TAG INFORMATION VALIDATION IN WIDE PORT SAS CONNECTIONS

Patent #:	7129101	Issue Dt:	10/31/2006	Application #:	10921538	Filing Dt:	08/18/2004
Publication #:	US20050041454	Pub Dt:	02/24/2005
Title:	FAILURE ANALYSIS VEHICLE FOR YIELD ENHANCEMENT WITH SELF TEST AT SPEED BURNIN CAPABILITY FOR RELIABILITY TESTING

Patent #:	7424422	Issue Dt:	09/09/2008	Application #:	10921643	Filing Dt:	08/19/2004
Publication #:	US20060041434	Pub Dt:	02/23/2006
Title:	VOICE CHANNEL BUSSING IN SOUND PROCESSORS

Patent #:	7296094	Issue Dt:	11/13/2007	Application #:	10923326	Filing Dt:	08/20/2004
Publication #:	US20060041691	Pub Dt:	02/23/2006
Title:	CIRCUIT AND METHOD TO PROVIDE CONFIGURATION OF SERIAL ATA QUEUE DEPTH VERSUS NUMBER OF DEVICES

Patent #:	7107558	Issue Dt:	09/12/2006	Application #:	10924531	Filing Dt:	08/23/2004
Publication #:	US20050022145	Pub Dt:	01/27/2005
Title:	METHOD OF FINDING CRITICAL NETS IN AN INTEGRATED CIRCUIT DESIGN

Patent #:	7312880	Issue Dt:	12/25/2007	Application #:	10925497	Filing Dt:	08/24/2004
Publication #:	US20060044571	Pub Dt:	03/02/2006
Title:	WAFER EDGE STRUCTURE MEASUREMENT METHOD

Patent #:	7137098	Issue Dt:	11/14/2006	Application #:	10927802	Filing Dt:	08/27/2004
Publication #:	US20060059452	Pub Dt:	03/16/2006
Title:	PATTERN COMPONENT ANALYSIS AND MANIPULATION

Patent #:	7237218	Issue Dt:	06/26/2007	Application #:	10927919	Filing Dt:	08/26/2004
Publication #:	US20060046353	Pub Dt:	03/02/2006
Title:	OPTIMIZING DYNAMIC POWER CHARACTERISTICS OF AN INTEGRATED CIRCUIT CHIP

Patent #:	7015569	Issue Dt:	03/21/2006	Application #:	10927985	Filing Dt:	08/26/2004
Publication #:	US20060043541	Pub Dt:	03/02/2006
Title:	METHOD AND APPARATUS FOR IMPLEMENTING A CO-AXIAL WIRE IN A SEMICONDUCTOR CHIP

Patent #:	7062415	Issue Dt:	06/13/2006	Application #:	10928292	Filing Dt:	08/27/2004
Publication #:	US20060047485	Pub Dt:	03/02/2006
Title:	PARAMETRIC OUTLIER DETECTION

Patent #:	7111267	Issue Dt:	09/19/2006	Application #:	10928799	Filing Dt:	08/27/2004
Publication #:	US20060048087	Pub Dt:	03/02/2006
Title:	PROCESS AND APPARATUS TO ASSIGN COORDINATES TO NODES OF LOGICAL TREES WITHOUT INCREASE OF WIRE LENGTHS

Patent #:	7340634	Issue Dt:	03/04/2008	Application #:	10929011	Filing Dt:	08/27/2004
Publication #:	US20060047991	Pub Dt:	03/02/2006
Title:	REAL TIME CLOCK ARCHITECTURE AND/OR METHOD FOR A SYSTEM ON A CHIP (SOC) APPLICATION

Patent #:	7191424	Issue Dt:	03/13/2007	Application #:	10929218	Filing Dt:	08/30/2004
Publication #:	US20060048079	Pub Dt:	03/02/2006
Title:	SPECIAL TIE-HIGH/LOW CELLS FOR SINGLE METAL LAYER ROUTE CHANGES

Patent #:	8685633	Issue Dt:	04/01/2014	Application #:	10929706	Filing Dt:	08/30/2004
Publication #:	US20060046213	Pub Dt:	03/02/2006
Title:	Method for optimizing wafer edge patterning

Patent #:	8404960	Issue Dt:	03/26/2013	Application #:	10930590	Filing Dt:	08/31/2004
Publication #:	US20060043582	Pub Dt:	03/02/2006
Title:	METHOD FOR HEAT DISSIPATION ON SEMICONDUCTOR DEVICE

Patent #:	7610200	Issue Dt:	10/27/2009	Application #:	10930624	Filing Dt:	08/30/2004
Publication #:	US20060047503	Pub Dt:	03/02/2006
Title:	SYSTEM AND METHOD FOR CONTROLLING SOUND DATA

Patent #:	7145858	Issue Dt:	12/05/2006	Application #:	10930930	Filing Dt:	08/30/2004
Publication #:	US20050141384	Pub Dt:	06/30/2005
Title:	CREATION OF SYNCHRONIZATION MARKS IN MULTILEVEL OPTICAL DATA STORAGE

Patent #:	7587310	Issue Dt:	09/08/2009	Application #:	10931151	Filing Dt:	08/30/2004
Publication #:	US20060047519	Pub Dt:	03/02/2006
Title:	SOUND PROCESSOR ARCHITECTURE USING SINGLE PORT MEMORY UNIT

Patent #:	7189628	Issue Dt:	03/13/2007	Application #:	10931605	Filing Dt:	08/31/2004
Title:	FABRICATION OF TRENCHES WITH MULTIPLE DEPTHS ON THE SAME SUBSTRATE

Patent #:	7596639	Issue Dt:	09/29/2009	Application #:	10931668	Filing Dt:	09/01/2004
Publication #:	US20060047865	Pub Dt:	03/02/2006
Title:	SKIP MASK TABLE AUTOMATED CONTEXT GENERATION

Patent #:	7082067	Issue Dt:	07/25/2006	Application #:	10934970	Filing Dt:	09/03/2004
Publication #:	US20060050600	Pub Dt:	03/09/2006
Title:	CIRCUIT FOR VERIFYING THE WRITE SPEED OF SRAM CELLS

Patent #:	7038257	Issue Dt:	05/02/2006	Application #:	10936016	Filing Dt:	09/07/2004
Publication #:	US20060049496	Pub Dt:	03/09/2006
Title:	SYSTEM AND METHOD FOR PROVIDING SCALABILITY IN AN INTEGRATED CIRCUIT

Patent #:	7830756	Issue Dt:	11/09/2010	Application #:	10936017	Filing Dt:	09/08/2004
Publication #:	US20060062105	Pub Dt:	03/23/2006
Title:	DEMODULATION OF TRACKING ERROR SIGNAL TO OBTAIN LENS POSITION FOR LENS MOTION CONTROL IN AN OPTICAL DISC SYSTEM

Patent #:	7194717	Issue Dt:	03/20/2007	Application #:	10936202	Filing Dt:	09/06/2016
Publication #:	US20060085777	Pub Dt:	04/20/2006
Title:	COMPACT CUSTOM LAYOUT FOR RRAM COLUMN CONTROLLER

Patent #:	7376541	Issue Dt:	05/20/2008	Application #:	10937049	Filing Dt:	09/09/2004
Publication #:	US20060052996	Pub Dt:	03/09/2006
Title:	ACCURATE PIN-BASED MEMORY POWER MODEL USING ARC-BASED CHARACTERIZATION

Patent #:	7157948	Issue Dt:	01/02/2007	Application #:	10937911	Filing Dt:	09/10/2004
Publication #:	US20060055441	Pub Dt:	03/16/2006
Title:	METHOD AND APPARATUS FOR CALIBRATING A DELAY LINE

Patent #:	7235889	Issue Dt:	06/26/2007	Application #:	10939082	Filing Dt:	09/10/2004
Publication #:	US20060055029	Pub Dt:	03/16/2006
Title:	INTEGRATED HEATSPREADER FOR USE IN WIRE BONDED BALL GRID ARRAY SEMICONDUCTOR PACKAGES

Patent #:	8312499	Issue Dt:	11/13/2012	Application #:	10939786	Filing Dt:	09/13/2004
Publication #:	US20060056627	Pub Dt:	03/16/2006
Title:	TUNNELING INFORMATION IN COMPRESSED AUDIO AND/OR VIDEO BIT STREAMS

Patent #:	7381502	Issue Dt:	06/03/2008	Application #:	10942444	Filing Dt:	09/16/2004
Publication #:	US20050053851	Pub Dt:	03/10/2005
Title:	APPARATUS AND METHOD TO IMPROVE THE RESOLUTION OF PHOTOLITHOGRAPHY SYSTEMS BY IMPROVING THE TEMPERATURE STABILITY OF THE RETICLE

Patent #:	8467552	Issue Dt:	06/18/2013	Application #:	10943516	Filing Dt:	09/17/2004
Publication #:	US20060062409	Pub Dt:	03/23/2006
Title:	ASYMMETRIC HRTF/ITD STORAGE FOR 3D SOUND POSITIONING

Patent #:	7122436	Issue Dt:	10/17/2006	Application #:	10944373	Filing Dt:	09/16/2004
Publication #:	US20060054997	Pub Dt:	03/16/2006
Title:	TECHNIQUES FOR FORMING PASSIVE DEVICES DURING SEMICONDUCTOR BACK-END PROCESSING

Patent #:	7799166	Issue Dt:	09/21/2010	Application #:	10944996	Filing Dt:	09/20/2004
Publication #:	US20060060299	Pub Dt:	03/23/2006
Title:	WAFER EDGE EXPOSE ALIGNMENT METHOD

Patent #:	7154734	Issue Dt:	12/26/2006	Application #:	10945177	Filing Dt:	09/20/2004
Publication #:	US20060061935	Pub Dt:	03/23/2006
Title:	FULLY SHIELDED CAPACITOR CELL STRUCTURE

Patent #:	7300869	Issue Dt:	11/27/2007	Application #:	10945777	Filing Dt:	09/20/2004
Publication #:	US20060063375	Pub Dt:	03/23/2006
Title:	INTEGRATED BARRIER AND SEED LAYER FOR COPPER INTERCONNECT TECHNOLOGY

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Publication #:	US20060064664	Pub Dt:	03/23/2006
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100

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Assignor

LSI CORPORATION

Exec Dt:

08/14/2014

Assignee

AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

1 YISHUN AVENUE 7

SINGAPORE, SINGAPORE 768923

Correspondence name and address
	LATHAM & WATKINS LLP
	650 TOWN CENTER DRIVE, SUITE 2000
	COSTA MESA, CA 92626

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