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Reel/Frame:035390/0388   Pages: 247
Recorded: 04/03/2015
Attorney Dkt #:040981-0072
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 5804
Page 34 of 59
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
1
Patent #:
7580330
Issue Dt:
08/25/2009
Application #:
11259300
Filing Dt:
10/26/2005
Publication #:
US20070091742
Pub Dt:
04/26/2007
Title:
CE TO RRO CANCELLATION FOR SLED CONTROL
2
Patent #:
7595743
Issue Dt:
09/29/2009
Application #:
11259596
Filing Dt:
10/26/2005
Title:
SYSTEM AND METHOD FOR REDUCING STORAGE REQUIREMENTS FOR CONTENT ADAPTIVE BINARY ARITHMETIC CODING
3
Patent #:
7196420
Issue Dt:
03/27/2007
Application #:
11259965
Filing Dt:
10/26/2005
Title:
METHOD AND STRUCTURE FOR CREATING ULTRA LOW RESISTANCE DAMASCENE COPPER WIRING
4
Patent #:
7589594
Issue Dt:
09/15/2009
Application #:
11260442
Filing Dt:
10/27/2005
Publication #:
US20070099581
Pub Dt:
05/03/2007
Title:
VARIABLE LOOP BANDWIDTH PHASE LOCKED LOOP
5
Patent #:
7472358
Issue Dt:
12/30/2008
Application #:
11260517
Filing Dt:
10/27/2005
Publication #:
US20070169009
Pub Dt:
07/19/2007
Title:
METHOD AND SYSTEM FOR OUTPUTTING A SEQUENCE OF COMMANDS AND DATA DESCRIBED BY A FLOWCHART
6
Patent #:
7619294
Issue Dt:
11/17/2009
Application #:
11262173
Filing Dt:
10/28/2005
Title:
SHALLOW TRENCH ISOLATION STRUCTURE WITH LOW TRENCH PARASITIC CAPACITANCE
7
Patent #:
7783038
Issue Dt:
08/24/2010
Application #:
11262444
Filing Dt:
10/28/2005
Publication #:
US20070098157
Pub Dt:
05/03/2007
Title:
USING CODE AS KEYS FOR COPY PROTECTION
8
Patent #:
7401171
Issue Dt:
07/15/2008
Application #:
11262679
Filing Dt:
10/31/2005
Publication #:
US20070100847
Pub Dt:
05/03/2007
Title:
METHODS AND STRUCTURE FOR SAS EXPANDER INITIATING COMMUNICATION TO A SAS INITIATOR TO IDENTIFY CHANGES IN THE SAS DOMAIN
9
Patent #:
7389196
Issue Dt:
06/17/2008
Application #:
11262864
Filing Dt:
10/31/2005
Publication #:
US20070100574
Pub Dt:
05/03/2007
Title:
METHOD AND SYSTEM FOR VALIDATING PCI/PCI-X ADAPTERS
10
Patent #:
7376780
Issue Dt:
05/20/2008
Application #:
11263514
Filing Dt:
10/31/2005
Publication #:
US20070101043
Pub Dt:
05/03/2007
Title:
PROTOCOL CONVERTER TO ACCESS AHB SLAVE DEVICES USING THE MDIO PROTOCOL
11
Patent #:
7571397
Issue Dt:
08/04/2009
Application #:
11265040
Filing Dt:
11/02/2005
Publication #:
US20070099313
Pub Dt:
05/03/2007
Title:
METHOD OF DESIGN BASED PROCESS CONTROL OPTIMIZATION
12
Patent #:
7716543
Issue Dt:
05/11/2010
Application #:
11266056
Filing Dt:
11/02/2005
Publication #:
US20070101200
Pub Dt:
05/03/2007
Title:
METHODS AND SYSTEMS FOR ELIMINATING TEST SYSTEM REBOOTS BETWEEN FUNCTIONAL TESTS OF HOST ADAPTER BOARDS
13
Patent #:
7640396
Issue Dt:
12/29/2009
Application #:
11266132
Filing Dt:
11/02/2005
Publication #:
US20070101062
Pub Dt:
05/03/2007
Title:
ALL PURPOSE PROCESSOR IMPLEMENTATION TO SUPPORT DIFFERENT TYPES OF CACHE MEMORY ARCHITECTURES
14
Patent #:
7327011
Issue Dt:
02/05/2008
Application #:
11266133
Filing Dt:
11/02/2005
Publication #:
US20070096252
Pub Dt:
05/03/2007
Title:
MULTI-SURFACED PLATE-TO-PLATE CAPACITOR AND METHOD OF FORMING SAME
15
Patent #:
7467359
Issue Dt:
12/16/2008
Application #:
11266687
Filing Dt:
11/03/2005
Publication #:
US20060067436
Pub Dt:
03/30/2006
Title:
DECODER USING A MEMORY FOR STORING STATE METRICS INPLEMENTING A DECODER TRELLIS
16
Patent #:
7529968
Issue Dt:
05/05/2009
Application #:
11267999
Filing Dt:
11/07/2005
Publication #:
US20070168701
Pub Dt:
07/19/2007
Title:
STORING RAID CONFIGURATION DATA WITHIN A BIOS IMAGE
17
Patent #:
8076779
Issue Dt:
12/13/2011
Application #:
11269275
Filing Dt:
11/08/2005
Publication #:
US20070102812
Pub Dt:
05/10/2007
Title:
REDUCTION OF MACRO LEVEL STRESSES IN COPPER/LOW-K WAFERS
18
Patent #:
7328382
Issue Dt:
02/05/2008
Application #:
11270077
Filing Dt:
11/09/2005
Publication #:
US20060161804
Pub Dt:
07/20/2006
Title:
MEMORY BISR CONTROLLER ARCHITECTURE
19
Patent #:
7325216
Issue Dt:
01/29/2008
Application #:
11271991
Filing Dt:
11/09/2005
Publication #:
US20070104029
Pub Dt:
05/10/2007
Title:
METHOD AND COMPUTER PROGRAM FOR SPREADING TRACE SEGMENTS IN AN INTEGRATED CIRCUIT PACKAGE DESIGN
20
Patent #:
8401070
Issue Dt:
03/19/2013
Application #:
11272300
Filing Dt:
11/10/2005
Publication #:
US20070104273
Pub Dt:
05/10/2007
Title:
METHOD FOR ROBUST INVERSE TELECINE
21
Patent #:
7551232
Issue Dt:
06/23/2009
Application #:
11273304
Filing Dt:
11/14/2005
Publication #:
US20070109448
Pub Dt:
05/17/2007
Title:
NOISE ADAPTIVE 3D COMPOSITE NOISE REDUCTION
22
Patent #:
7583571
Issue Dt:
09/01/2009
Application #:
11273518
Filing Dt:
11/14/2005
Publication #:
US20070109937
Pub Dt:
05/17/2007
Title:
WRITE BASED POWER ADAPTIVE CONTROL SYSTEM
23
Patent #:
7545900
Issue Dt:
06/09/2009
Application #:
11273940
Filing Dt:
11/15/2005
Publication #:
US20070110206
Pub Dt:
05/17/2007
Title:
LOW JITTER AND/OR FAST LOCK-IN CLOCK RECOVERY CIRCUIT
24
Patent #:
7180011
Issue Dt:
02/20/2007
Application #:
11276938
Filing Dt:
03/17/2006
Title:
DEVICE FOR MINIMIZING DIFFERENTIAL PAIR LENGTH MISMATCH AND IMPEDANCE DISCONTINUITIES IN AN INTEGRATED CIRCUIT PACKAGE DESIGN
25
Patent #:
8049340
Issue Dt:
11/01/2011
Application #:
11277188
Filing Dt:
03/22/2006
Publication #:
US20070222084
Pub Dt:
09/27/2007
Title:
DEVICE FOR AVOIDING PARASITIC CAPACITANCE IN AN INTEGRATED CIRCUIT PACKAGE
26
Patent #:
7424687
Issue Dt:
09/09/2008
Application #:
11280110
Filing Dt:
11/16/2005
Publication #:
US20070113212
Pub Dt:
05/17/2007
Title:
METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRCUIT LAYOUT
27
Patent #:
7764614
Issue Dt:
07/27/2010
Application #:
11280590
Filing Dt:
11/15/2005
Publication #:
US20070110086
Pub Dt:
05/17/2007
Title:
MULTI-MODE MANAGEMENT OF A SERIAL COMMUNICATION LINK
28
Patent #:
7496474
Issue Dt:
02/24/2009
Application #:
11280639
Filing Dt:
11/16/2005
Publication #:
US20070112544
Pub Dt:
05/17/2007
Title:
DYNAMIC ON-CHIP LOGIC ANALYSIS
29
Patent #:
7389484
Issue Dt:
06/17/2008
Application #:
11280879
Filing Dt:
11/16/2005
Publication #:
US20070108961
Pub Dt:
05/17/2007
Title:
METHOD AND APPARATUS FOR TILING MEMORIES IN INTEGRATED CIRCUIT LAYOUT
30
Patent #:
7539091
Issue Dt:
05/26/2009
Application #:
11282881
Filing Dt:
11/18/2005
Publication #:
US20070115792
Pub Dt:
05/24/2007
Title:
DIFFERENTIAL PUSH-PULL GAIN CONTROLLING METHOD AND APPARATUS TO REDUCE THE EFFECTS OF ROTATIONAL ECCENTRICITY
31
Patent #:
7205673
Issue Dt:
04/17/2007
Application #:
11283044
Filing Dt:
11/18/2005
Title:
REDUCE OR ELIMINATE IMC CRACKING IN POST WIRE BONDED DIES BY DOPING ALUMINUM USED IN BOND PADS DURING CU/LOW-K BEOL PROCESSING
32
Patent #:
8552560
Issue Dt:
10/08/2013
Application #:
11283219
Filing Dt:
11/18/2005
Publication #:
US20070114667
Pub Dt:
05/24/2007
Title:
ALTERNATE PAD STRUCTURES/PASSIVATION INEGRATION SCHEMES TO REDUCE OR ELIMINATE IMC CRACKING IN POST WIRE BONDED DIES DURING CU/LOW-K BEOL PROCESSING
33
Patent #:
7298036
Issue Dt:
11/20/2007
Application #:
11283340
Filing Dt:
11/18/2005
Publication #:
US20070114644
Pub Dt:
05/24/2007
Title:
SCALING OF FUNCTIONAL ASSIGNMENTS IN PACKAGES
34
Patent #:
7793010
Issue Dt:
09/07/2010
Application #:
11285243
Filing Dt:
11/22/2005
Publication #:
US20070130407
Pub Dt:
06/07/2007
Title:
BUS SYSTEM WITH MULTIPLE MODES OF OPERATION
35
Patent #:
7494842
Issue Dt:
02/24/2009
Application #:
11286546
Filing Dt:
11/23/2005
Publication #:
US20070114613
Pub Dt:
05/24/2007
Title:
PROGRAMMABLE NANOTUBE INTERCONNECT
36
Patent #:
7655548
Issue Dt:
02/02/2010
Application #:
11286557
Filing Dt:
11/23/2005
Publication #:
US20070114517
Pub Dt:
05/24/2007
Title:
PROGRAMMABLE POWER MANAGEMENT USING A NANOTUBE STRUCTURE
37
Patent #:
7847285
Issue Dt:
12/07/2010
Application #:
11286558
Filing Dt:
11/23/2005
Publication #:
US20070125999
Pub Dt:
06/07/2007
Title:
CONFIGURABLE POWER SEGMENTATION USING A NANOTUBE STRUCTURE
38
Patent #:
7379281
Issue Dt:
05/27/2008
Application #:
11287615
Filing Dt:
11/28/2005
Publication #:
US20070121262
Pub Dt:
05/31/2007
Title:
BIAS FOR ELECTROSTATIC DISCHARGE PROTECTION
39
Patent #:
7254761
Issue Dt:
08/07/2007
Application #:
11287927
Filing Dt:
11/28/2005
Publication #:
US20070122922
Pub Dt:
05/31/2007
Title:
PLATFORM ASIC RELIABILITY
40
Patent #:
7531442
Issue Dt:
05/12/2009
Application #:
11290087
Filing Dt:
11/30/2005
Publication #:
US20070123024
Pub Dt:
05/31/2007
Title:
ELIMINATE IMC CRACKING IN POST WIREBONDED DIES: MACRO LEVEL STRESS REDUCTION BY MODIFYING DIELECTRIC/METAL FILM STACK IN BE LAYERS DURING CU/LOW-K PROCESSING
41
Patent #:
7698477
Issue Dt:
04/13/2010
Application #:
11290096
Filing Dt:
11/30/2005
Publication #:
US20070121495
Pub Dt:
05/31/2007
Title:
METHOD AND APPARATUS FOR MANAGING FLOW CONTROL IN PCI EXPRESS TRANSACTION LAYER
42
Patent #:
NONE
Issue Dt:
Application #:
11290178
Filing Dt:
11/30/2005
Publication #:
US20070124628
Pub Dt:
05/31/2007
Title:
Methods of memory bitmap verification for finished product
43
Patent #:
7496861
Issue Dt:
02/24/2009
Application #:
11290186
Filing Dt:
11/30/2005
Publication #:
US20070124716
Pub Dt:
05/31/2007
Title:
METHOD FOR GENERALIZING DESIGN ATTRIBUTES IN A DESIGN CAPTURE ENVIRONMENT
44
Patent #:
7701508
Issue Dt:
04/20/2010
Application #:
11290194
Filing Dt:
11/30/2005
Publication #:
US20070121001
Pub Dt:
05/31/2007
Title:
ACCURATE MOTION DETECTION FOR THE COMBINATION OF MOTION ADAPTIVE AND MOTION COMPENSATION DE-INTERLACING APPLICATIONS
45
Patent #:
8243804
Issue Dt:
08/14/2012
Application #:
11292198
Filing Dt:
12/01/2005
Publication #:
US20070127573
Pub Dt:
06/07/2007
Title:
HIERARCHICAL MOTION ESTIMATION FOR IMAGES WITH VARYING HORIZONTAL AND/OR VERTICAL DIMENSIONS
46
Patent #:
7813429
Issue Dt:
10/12/2010
Application #:
11293404
Filing Dt:
12/02/2005
Publication #:
US20060083311
Pub Dt:
04/20/2006
Title:
SYSTEM AND METHOD FOR SEGMENTATION OF MACROBLOCKS
47
Patent #:
7721143
Issue Dt:
05/18/2010
Application #:
11295344
Filing Dt:
12/06/2005
Publication #:
US20070168706
Pub Dt:
07/19/2007
Title:
METHOD FOR REDUCING REBUILD TIME ON A RAID DEVICE
48
Patent #:
7406669
Issue Dt:
07/29/2008
Application #:
11295351
Filing Dt:
12/06/2005
Publication #:
US20070130486
Pub Dt:
06/07/2007
Title:
TIMING CONSTRAINTS METHODOLOGY FOR ENABLING CLOCK RECONVERGENCE PESSIMISM REMOVAL IN EXTRACTED TIMING MODELS
49
Patent #:
7584442
Issue Dt:
09/01/2009
Application #:
11298894
Filing Dt:
12/09/2005
Publication #:
US20070136704
Pub Dt:
06/14/2007
Title:
METHOD AND APPARATUS FOR GENERATING MEMORY MODELS AND TIMING DATABASE
50
Patent #:
7624330
Issue Dt:
11/24/2009
Application #:
11299506
Filing Dt:
12/12/2005
Publication #:
US20070136641
Pub Dt:
06/14/2007
Title:
UNIFIED MEMORY ARCHITECTURE FOR RECORDING APPLICATIONS
51
Patent #:
7539798
Issue Dt:
05/26/2009
Application #:
11300012
Filing Dt:
12/14/2005
Publication #:
US20070136521
Pub Dt:
06/14/2007
Title:
MITIGATING PERFORMANCE DEGRADATION CAUSED BY A SATA DRIVE ATTACHED TO A SAS DOMAIN
52
Patent #:
7379836
Issue Dt:
05/27/2008
Application #:
11300789
Filing Dt:
12/14/2005
Publication #:
US20070136023
Pub Dt:
06/14/2007
Title:
METHOD OF USING AUTOMATED TEST EQUIPMENT TO SCREEN FOR LEAKAGE INDUCING DEFECTS AFTER CALIBRATION TO INTRINSIC LEAKAGE
53
Patent #:
7551414
Issue Dt:
06/23/2009
Application #:
11300938
Filing Dt:
12/15/2005
Publication #:
US20070138973
Pub Dt:
06/21/2007
Title:
ELECTROSTATIC DISCHARGE SERIES PROTECTION
54
Patent #:
8001374
Issue Dt:
08/16/2011
Application #:
11303506
Filing Dt:
12/16/2005
Publication #:
US20070140477
Pub Dt:
06/21/2007
Title:
MEMORY ENCRYPTION FOR DIGITAL VIDEO
55
Patent #:
7498664
Issue Dt:
03/03/2009
Application #:
11304862
Filing Dt:
12/14/2005
Publication #:
US20070132083
Pub Dt:
06/14/2007
Title:
SEMICONDUCTOR PACKAGE HAVING INCREASED RESISTANCE TO ELECTROSTATIC DISCHARGE
56
Patent #:
7617391
Issue Dt:
11/10/2009
Application #:
11305180
Filing Dt:
12/15/2005
Publication #:
US20070143589
Pub Dt:
06/21/2007
Title:
METHOD AND APPARATUS FOR DYNAMICALLY SELECTING ONE OF MULTIPLE FIRMWARE IMAGES FOR BOOTING AN I/O CONTROLLER
57
Patent #:
7406675
Issue Dt:
07/29/2008
Application #:
11305542
Filing Dt:
12/16/2005
Publication #:
US20070143734
Pub Dt:
06/21/2007
Title:
METHOD AND SYSTEM FOR IMPROVING AERIAL IMAGE SIMULATION SPEEDS
58
Patent #:
7489154
Issue Dt:
02/10/2009
Application #:
11305749
Filing Dt:
12/16/2005
Publication #:
US20070139065
Pub Dt:
06/21/2007
Title:
TESTING HIGH FREQUENCY SIGNALS ON A TRACE
59
Patent #:
7652962
Issue Dt:
01/26/2010
Application #:
11305764
Filing Dt:
12/16/2005
Publication #:
US20070143771
Pub Dt:
06/21/2007
Title:
USING PRML READ CHANNEL ADC FOR BLANK/DEFECT AND RIPPLE DETECTION
60
Patent #:
7415686
Issue Dt:
08/19/2008
Application #:
11311388
Filing Dt:
12/19/2005
Publication #:
US20070143648
Pub Dt:
06/21/2007
Title:
MEMORY TIMING MODEL WITH BACK-ANNOTATING
61
Patent #:
7546568
Issue Dt:
06/09/2009
Application #:
11311515
Filing Dt:
12/19/2005
Publication #:
US20070143725
Pub Dt:
06/21/2007
Title:
AUTOMATION OF TIE CELL INSERTION, OPTIMIZATION AND REPLACEMENT BY SCAN FLIP-FLOPS TO INCREASE FAULT COVERAGE
62
Patent #:
7418550
Issue Dt:
08/26/2008
Application #:
11311523
Filing Dt:
12/19/2005
Publication #:
US20070028044
Pub Dt:
02/01/2007
Title:
METHODS AND STRUCTURE FOR IMPROVED IMPORT/EXPORT OF RAID LEVEL 6 VOLUMES
63
Patent #:
8176217
Issue Dt:
05/08/2012
Application #:
11312080
Filing Dt:
12/20/2005
Publication #:
US20070162636
Pub Dt:
07/12/2007
Title:
SYSTEM AND METHOD FOR IMPLEMENTING A STORAGE PROTOCOL WITH INITIATOR CONTROLLED DATA TRANSFER
64
Patent #:
7705913
Issue Dt:
04/27/2010
Application #:
11314631
Filing Dt:
12/20/2005
Publication #:
US20070139552
Pub Dt:
06/21/2007
Title:
UNIFIED APPROACH TO FILM MODE DETECTION
65
Patent #:
8018805
Issue Dt:
09/13/2011
Application #:
11314883
Filing Dt:
12/21/2005
Publication #:
US20070140074
Pub Dt:
06/21/2007
Title:
MEDIA TYPE DETECTION USING A LOCK INDICATOR
66
Patent #:
7720556
Issue Dt:
05/18/2010
Application #:
11315959
Filing Dt:
12/21/2005
Publication #:
US20070142930
Pub Dt:
06/21/2007
Title:
WEB-ENABLED SOLUTIONS FOR MEMORY COMPILATION TO SUPPORT PRE-SALES ESTIMATION OF MEMORY SIZE, PERFORMANCE AND POWER DATA FOR MEMORY COMPONENTS
67
Patent #:
7288947
Issue Dt:
10/30/2007
Application #:
11316011
Filing Dt:
12/19/2005
Publication #:
US20070139031
Pub Dt:
06/21/2007
Title:
METHOD FOR SIMULATING RESISTOR CHARACTERISTICS AT HIGH ELECTRIC FIELDS
68
Patent #:
7599008
Issue Dt:
10/06/2009
Application #:
11318231
Filing Dt:
12/23/2005
Publication #:
US20070121013
Pub Dt:
05/31/2007
Title:
METHOD AND/OR APPARATUS FOR CROSS-COLOR AND CROSS-LUMINANCE SUPPRESSION USING SHIMMER DETECTION
69
Patent #:
7566923
Issue Dt:
07/28/2009
Application #:
11318332
Filing Dt:
12/23/2005
Publication #:
US20070145413
Pub Dt:
06/28/2007
Title:
ISOLATED POWER DOMAIN CORE REGIONS IN PLATFORM ASICS
70
Patent #:
7480878
Issue Dt:
01/20/2009
Application #:
11321260
Filing Dt:
12/29/2005
Publication #:
US20070157140
Pub Dt:
07/05/2007
Title:
METHOD AND SYSTEM FOR LAYOUT VERSUS SCHEMATIC VALIDATION OF INTEGRATED CIRCUIT DESIGNS
71
Patent #:
7129690
Issue Dt:
10/31/2006
Application #:
11321747
Filing Dt:
12/29/2005
Title:
AT-SPEED ON-CHIP SHORT CLOCK CYCLE MONITORING SYSTEM AND METHOD
72
Patent #:
7436040
Issue Dt:
10/14/2008
Application #:
11323398
Filing Dt:
12/29/2005
Publication #:
US20070259518
Pub Dt:
11/08/2007
Title:
METHOD AND APPARATUS FOR DIVERTING VOID DIFFUSION IN INTEGRATED CIRCUIT CONDUCTORS
73
Patent #:
7361965
Issue Dt:
04/22/2008
Application #:
11323400
Filing Dt:
12/29/2005
Publication #:
US20070155160
Pub Dt:
07/05/2007
Title:
METHOD AND APPARATUS FOR REDIRECTING VOID DIFFUSION AWAY FROM VIAS IN AN INTEGRATED CIRCUIT DESIGN
74
Patent #:
7434198
Issue Dt:
10/07/2008
Application #:
11323401
Filing Dt:
12/29/2005
Publication #:
US20070157152
Pub Dt:
07/05/2007
Title:
METHOD AND COMPUTER PROGRAM PRODUCT FOR DETECTING POTENTIAL FAILURES IN AN INTEGRATED CIRCUIT DESIGN AFTER OPTICAL PROXIMITY CORRECTION
75
Patent #:
7429733
Issue Dt:
09/30/2008
Application #:
11323405
Filing Dt:
12/29/2005
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Title:
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Assignor
1
LSI CORPORATION
Exec Dt:
08/14/2014
Assignee
1
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
1 YISHUN AVENUE 7
SINGAPORE, SINGAPORE 768923
Correspondence name and address
LATHAM & WATKINS LLP
650 TOWN CENTER DRIVE, SUITE 2000
COSTA MESA, CA 92626

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