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Reel/Frame:024946/0388   Pages: 4
Recorded: 09/03/2010
Attorney Dkt #:920.0161.S1(US)
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 7
1
Patent #:
Issue Dt:
10/22/2002
Application #:
09458185
Filing Dt:
12/08/1999
Title:
SEMICONDUCTOR YIELD MANAGEMENT SYSTEM AND METHOD
2
Patent #:
Issue Dt:
07/27/2004
Application #:
09952848
Filing Dt:
09/14/2001
Publication #:
Pub Dt:
03/20/2003
Title:
SYSTEM AND METHOD FOR ANALYZING ERROR INFORMATION FROM A SEMICONDUCTOR FABRICATION PROCESS
3
Patent #:
Issue Dt:
06/21/2011
Application #:
10972115
Filing Dt:
10/22/2004
Title:
SEMICONDUCTOR YIELD MANAGEMENT SYSTEM AND METHOD
4
Patent #:
Issue Dt:
03/23/2010
Application #:
11166960
Filing Dt:
06/23/2005
Publication #:
Pub Dt:
01/11/2007
Title:
BITMAP CLUSTER ANALYSIS OF DEFECTS IN INTEGRATED CIRCUITS
5
Patent #:
Issue Dt:
05/31/2011
Application #:
11701700
Filing Dt:
02/02/2007
Publication #:
Pub Dt:
08/07/2008
Title:
ANALYSIS TECHNIQUES FOR MULTI-LEVEL MEMORY
6
Patent #:
Issue Dt:
02/19/2013
Application #:
12150676
Filing Dt:
04/29/2008
Publication #:
Pub Dt:
11/13/2008
Title:
Semiconductor yield management system and method
7
Patent #:
Issue Dt:
05/29/2012
Application #:
12728629
Filing Dt:
03/22/2010
Publication #:
Pub Dt:
09/16/2010
Title:
BITMAP CLUSTER ANALYSIS OF DEFECTS IN INTEGRATED CIRCUITS
Assignor
1
Exec Dt:
08/11/2010
Assignee
1
ONE RUDOLPH ROAD
FLANDERS, NEW JERSEY 07836
Correspondence name and address
MARK F. HARRINGTON
HARRINGTON & SMITH
ATTORNEYS AT LAW, LLC
4 RESEARCH DRIVE, SUITE 202
SHELTON, CONNECTICUT 06484-6212

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