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Reel/Frame:	023774/0399			Pages:	386
		Recorded:	01/13/2010
Attorney Dkt #:	609612800100
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 37

Patent #:	6693318	Issue Dt:	02/17/2004	Application #:	09216372	Filing Dt:	12/18/1998
Title:	REDUCED DIFFUSION OF A MOBILE SPECIE FROM A METAL OXIDE CERAMIC

Patent #:	6323067	Issue Dt:	11/27/2001	Application #:	09238543	Filing Dt:	01/28/1999
Title:	LIGHT ABSORPTION LAYER FOR LASER BLOWN FUSES

Patent #:	6184091	Issue Dt:	02/06/2001	Application #:	09241756	Filing Dt:	02/01/1999
Title:	FORMATION OF CONTROLLED TRENCH TOP ISOLATION LAYERS FOR VERTICAL TRANSISTORS

Patent #:	6094395	Issue Dt:	07/25/2000	Application #:	09253996	Filing Dt:	02/22/1999
Title:	ARRANGEMENT FOR CONTROLLING VOLTAGE GENERATORS IN MULTI VOLTAGE GENERATOR CHIPS SUCH AS DRAMS

Patent #:	6114074	Issue Dt:	09/05/2000	Application #:	09266473	Filing Dt:	03/11/1999
Title:	EXTRUSION ENHANCED MASK FOR IMPROVING WINDOW

Patent #:	6083788	Issue Dt:	07/04/2000	Application #:	09277669	Filing Dt:	03/26/1999
Title:	STACKED CAPACITOR MEMORY CELL AND METHOD OF MANUFACUTRE

Patent #:	6207573	Issue Dt:	03/27/2001	Application #:	09314358	Filing Dt:	05/19/1999
Title:	DIFFERENTIAL TRENCH OPEN PROCESS

Patent #:	6218696	Issue Dt:	04/17/2001	Application #:	09326889	Filing Dt:	06/07/1999
Title:	LAYOUT AND WIRING SCHEME FOR MEMORY CELLS WITH VERTICAL TRANSISTORS

Patent #:	6034390	Issue Dt:	03/07/2000	Application #:	09340095	Filing Dt:	06/25/1999
Title:	MULTI-BIT TRENCH CAPACITOR

Patent #:	6066527	Issue Dt:	05/23/2000	Application #:	09361055	Filing Dt:	07/26/1999
Title:	BURIED STRAP POLY ETCH BACK (BSPE) PROCESS

Patent #:	6235651	Issue Dt:	05/22/2001	Application #:	09395952	Filing Dt:	09/14/1999
Title:	PROCESS FOR IMPROVING THE THICKNESS UNIFORMITY OF A THIN LAYER IN SEMICONCUCTOR WAFER FABRICATION

Patent #:	6320780	Issue Dt:	11/20/2001	Application #:	09406892	Filing Dt:	09/28/1999
Title:	REDUCED IMPACT FROM COUPLING NOISE IN DIAGONAL BITLINE ARCHITECTURES

Patent #:	6159874	Issue Dt:	12/12/2000	Application #:	09427991	Filing Dt:	10/27/1999
Title:	INTEGRATED CIRCUIT FABRICATION

Patent #:	6207513	Issue Dt:	03/27/2001	Application #:	09432063	Filing Dt:	11/02/1999
Title:	SPACER PROCESS TO ELIMINATE CORNER TRANSISTOR DEVICE

Patent #:	6285619	Issue Dt:	09/04/2001	Application #:	09442982	Filing Dt:	11/18/1999
Title:	MEMORY CELL

Patent #:	6177698	Issue Dt:	01/23/2001	Application #:	09461599	Filing Dt:	12/15/1999
Title:	FORMATION OF CONTROLLED TRENCH TOP ISOLATION LAYERS FOR VERTICLE TRANSISTORS

Patent #:	6359299	Issue Dt:	03/19/2002	Application #:	09503992	Filing Dt:	02/14/2000
Title:	Apparatus and method for forming controlled deep trench top isolation layers

Patent #:	6141284	Issue Dt:	10/31/2000	Application #:	09534103	Filing Dt:	03/23/2000
Title:	Method and apparatus for an improved reset and power-on arrangement for a dram generator controller

Patent #:	6181639	Issue Dt:	01/30/2001	Application #:	09534104	Filing Dt:	03/23/2000
Title:	Method and apparatus for a flexible controller for a dram generator system

Patent #:	6294940	Issue Dt:	09/25/2001	Application #:	09598349	Filing Dt:	06/21/2000
Title:	Symmetric clock receiver for differential input signals

Patent #:	6537926	Issue Dt:	03/25/2003	Application #:	09638309	Filing Dt:	08/14/2000
Title:	PROCESS FOR IMPROVING THE THICKNESS UNIFORMITY OF A THIN OXIDE LAYER IN SEMICONDUCTOR WAFER FABRICATION

Patent #:	6593240	Issue Dt:	07/15/2003	Application #:	09723802	Filing Dt:	11/28/2000
Title:	TWO STEP CHEMICAL MECHANICAL POLISHING PROCESS

Patent #:	6440753	Issue Dt:	08/27/2002	Application #:	09824596	Filing Dt:	04/02/2001
Publication #:	US20020098676	Pub Dt:	07/25/2002
Title:	METAL HARD MASK FOR ILD RIE PROCESSING OF SEMICONDUCTOR MEMORY DEVICES TO PREVENT OXIDATION OF CONDUCTIVE LINES

Patent #:	6426907	Issue Dt:	07/30/2002	Application #:	09836817	Filing Dt:	04/17/2001
Title:	REFERENCE FOR MRAM CELL

Patent #:	6620699	Issue Dt:	09/16/2003	Application #:	09967226	Filing Dt:	09/28/2001
Publication #:	US20030062557	Pub Dt:	04/03/2003
Title:	METHOD FOR FORMING INSIDE NITRIDE SPACER FOR DEEP TRENCH DEVICE DRAM CELL

Patent #:	6490194	Issue Dt:	12/03/2002	Application #:	09967662	Filing Dt:	09/27/2001
Publication #:	US20020097598	Pub Dt:	07/25/2002
Title:	SERIAL MRAM DEVICE

Patent #:	6594191	Issue Dt:	07/15/2003	Application #:	10016859	Filing Dt:	12/13/2001
Publication #:	US20030112654	Pub Dt:	06/19/2003
Title:	SEGMENTED WRITE LINE ARCHITECTURE

Patent #:	6713884	Issue Dt:	03/30/2004	Application #:	10026347	Filing Dt:	12/20/2001
Publication #:	US20030119274	Pub Dt:	06/26/2003
Title:	METHOD OF FORMING AN ALIGNMENT MARK STRUCTURE USING STANDARD PROCESS STEPS FOR FORMING VERTICAL GATE TRANSISTORS

Patent #:	6608783	Issue Dt:	08/19/2003	Application #:	10034625	Filing Dt:	12/27/2001
Publication #:	US20030133320	Pub Dt:	07/17/2003
Title:	TWISTED BIT-LINE COMPENSATION

Patent #:	6579768	Issue Dt:	06/17/2003	Application #:	10066184	Filing Dt:	01/31/2002
Publication #:	US20020094650	Pub Dt:	07/18/2002
Title:	FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION

Patent #:	6602745	Issue Dt:	08/05/2003	Application #:	10066206	Filing Dt:	01/31/2002
Publication #:	US20020094618	Pub Dt:	07/18/2002
Title:	FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION

Patent #:	6537885	Issue Dt:	03/25/2003	Application #:	10142537	Filing Dt:	05/09/2002
Title:	TRANSISTOR AND METHOD OF MANUFACTURING A TRANSISTOR HAVING A SHALLOW JUNCTION FORMATION USING A TWO STEP EPI LAYER

Patent #:	6713236	Issue Dt:	03/30/2004	Application #:	10188532	Filing Dt:	07/03/2002
Publication #:	US20040005516	Pub Dt:	01/08/2004
Title:	LITHOGRAPHY METHOD FOR PREVENTING LITHOGRAPHIC EXPOSURE OF PERIPHERAL REGION OF SEMICONDUCTOR WAFER

Patent #:	6847571	Issue Dt:	01/25/2005	Application #:	10406320	Filing Dt:	04/04/2003
Publication #:	US20040196702	Pub Dt:	10/07/2004
Title:	USE OF REDUNDANT MEMORY CELLS TO MANUFACTURE COST EFFICIENT DRAMS WITH REDUCED SELF REFRESH CURRENT CAPABILITY

Patent #:	6674684	Issue Dt:	01/06/2004	Application #:	10460791	Filing Dt:	06/11/2003
Title:	MULTI-BANK CHIP COMPATIBLE WITH A CONTROLLER DESIGNED FOR A LESSER NUMBER OF BANKS AND METHOD OF OPERATING

Patent #:	6825096	Issue Dt:	11/30/2004	Application #:	10762973	Filing Dt:	01/22/2004
Publication #:	US20040152270	Pub Dt:	08/05/2004
Title:	METHOD OF FORMING AN ALIGNMENT MARK STRUCTURE USING STANDARD PROCESS STEPS FOR FORMING VERTICAL GATE TRANSISTORS

Patent #:	7420399	Issue Dt:	09/02/2008	Application #:	11271015	Filing Dt:	11/10/2005
Publication #:	US20070103216	Pub Dt:	05/10/2007
Title:	DUTY CYCLE CORRECTOR

Assignor

INFINEON TECHNOLOGIES NORTH AMERICA CORP

Exec Dt:

04/25/2006

Assignee

QIMONDA AG

GUSTAV-HEINEMANN-RING 212

MUNICH, GERMANY 81739

Correspondence name and address
	BARRY E. BRETSCHNEIDER
	C/O MORRISON & FOERSTER LLP
	1650 TYSONS BOULEVARD SUITE 400
	MCLEAN, VA 22102

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