Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 036174/0403 | |
| Pages: | 6 |
| | Recorded: | 07/24/2015 | | |
| Attorney Dkt #: | RA442.CIP2D1C1C.B49 +3 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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03/23/2010
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Application #:
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12424442
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Filing Dt:
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04/15/2009
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Publication #:
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Pub Dt:
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08/06/2009
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Title:
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MEMORY SYSTEM TOPOLOGIES INCLUDING A BUFFER DEVICE AND AN INTEGRATED CIRCUIT MEMORY DEVICE
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Patent #:
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Issue Dt:
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01/31/2012
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Application #:
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12703521
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Filing Dt:
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02/10/2010
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Publication #:
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Pub Dt:
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06/10/2010
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Title:
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MEMORY SYSTEM TOPOLOGIES INCLUDING A BUFFER DEVICE AND AN INTEGRATED CIRCUIT MEMORY DEVICE
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Patent #:
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Issue Dt:
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08/25/2015
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Application #:
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14015648
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Filing Dt:
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08/30/2013
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Publication #:
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Pub Dt:
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08/07/2014
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Title:
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MEMORY SYSTEM TOPOLOGIES INCLUDING A BUFFER DEVICE AND AN INTEGRATED CIRCUIT MEMORY DEVICE
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Patent #:
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Issue Dt:
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02/07/2017
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Application #:
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14801723
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Filing Dt:
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07/16/2015
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Publication #:
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Pub Dt:
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06/30/2016
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Title:
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Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device
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Assignee
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| 1050 ENTERPRISE WAY, SUITE 700 |
| SUNNYVALE, CALIFORNIA 94089 |
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Correspondence name and address
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TARISA WAIN
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1050 ENTERPRISE WAY #700
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SUNNYVALE, CA 94089
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