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Patent #:
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Issue Dt:
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04/18/2000
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Application #:
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09008792
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Filing Dt:
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01/20/1998
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Title:
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MICROPROCESSOR WITH PIPELINE SYNCHRONIZATION
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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09070145
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Filing Dt:
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04/30/1998
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Title:
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PROGRAMMABLE HARDWARE EVENT MONITORING METHOD
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09228314
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Filing Dt:
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01/11/1999
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Title:
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SELECTIVE ROUTING OF DATA IN A MULTI-LEVEL MEMORY ARCHITECTURE BASED ON SOURCE IDENTIFICATION INFORMATION
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09228884
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Filing Dt:
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01/11/1999
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Title:
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SYSTEM AND METHOD FOR POWER OPTIMIZATION IN PARALLEL UNITS
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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09266133
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Filing Dt:
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03/10/1999
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Title:
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INSTRUCTION CACHE FOR MULTITHREADED PROCESSOR
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09340075
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Filing Dt:
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06/25/1999
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Title:
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LAYERED LOCAL CACHE WITH IMPRECISE RELOAD MECHANISM
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09340076
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Filing Dt:
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06/25/1999
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Title:
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LAYERED LOCAL CACHE MECHANISM WITH SPLIT REGISTER LOAD BUS AND CACHE LOAD BUS
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09383736
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Filing Dt:
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08/26/1999
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Title:
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TRANSFER OF DATA BETWEEN PROCESSORS IN A MULTI-PROCESSOR SYSTEM
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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09387220
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Filing Dt:
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08/31/1999
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Title:
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METHOD AND APPARATUS FOR IMPLEMENTING EXECUTION PREDICATES IN A COMPUTER PROCESSING SYSTEM
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09394965
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Filing Dt:
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09/10/1999
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Title:
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METHOD AND APPARATUS FOR ALLOCATING DATA AND INSTRUCTIONS WITHIN A SHARED CACHE
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09432044
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Filing Dt:
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11/01/1999
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Title:
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METHOD, SYSTEM, AND PROGRAM FOR MANAGING REQUESTS TO A CACHE USING FLAGS TO QUEUE AND DEQUEUE DATA IN A BUFFER
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Patent #:
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Issue Dt:
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12/13/2005
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Application #:
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09435070
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Filing Dt:
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11/04/1999
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Title:
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CIRCUITS, SYSTEMS AND METHODS FOR PERFORMING BRANCH PREDICTIONS BY SELECTIVELY ACCESSING BIMODAL AND FETCH-BASED HISTORY TABLES
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09435865
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Filing Dt:
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11/08/1999
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Title:
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SYSTEM AND METHOD FOR PREFETCHING DATA TO MULTIPLE LEVELS OF CACHE INCLUDING SELECTIVELY USING A SOFTWARE HINT TO OVERRIDE A HARDWARE PREFETCH MECHANISM
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Patent #:
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Issue Dt:
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05/31/2005
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Application #:
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09435868
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Filing Dt:
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11/08/1999
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Title:
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TLB PARITY ERROR RECOVERY
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Patent #:
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Issue Dt:
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01/27/2004
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Application #:
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09436202
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Filing Dt:
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11/08/1999
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Title:
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METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR CONTROLLING DATA TRANSFER
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09436203
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Filing Dt:
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11/08/1999
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Title:
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METHOD AND APPARATUS TO ELIMINATE FAILED SNOOPS OF TRANSACTIONS CAUSED BY BUS TIMING CONFLICTS IN A DISTRIBUTED SYMMETRIC MULTIPROCESSOR SYSTEM
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09437176
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Filing Dt:
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11/09/1999
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Title:
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CACHE COHERENCY PROTOCOL IN WHICH A LOAD INSTRUCTION HINT BIT IS EMPLOYED TO INDICATE DEALLOCATION OF A MODIFIED CACHE LINE SUPPLIED BY INTERVENTION
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Patent #:
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Issue Dt:
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02/05/2002
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Application #:
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09437177
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Filing Dt:
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11/09/1999
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Title:
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CACHE COHERERENCY PROTOCOL EMPLOYING A READ OPERATION INCLUDING PROGRAMMABLE FLAG TO INDICATE DEALLOCATION OF AN INTERVENED CACHE LINE
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Patent #:
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Issue Dt:
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02/05/2002
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Application #:
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09437178
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Filing Dt:
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11/09/1999
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Title:
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MULTIPROCESSOR SYSTEM BUS PROTOCOL INCLUDING READ REQUEST HAVING FLAG INDICATING DEALLOCATION UPON SOURCING A REQUESTED MODIFIED VALUE
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09437179
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Filing Dt:
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11/09/1999
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Title:
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HIGH PERFORMANCE MULTIPROCESSOR SYSTEM WITH MODIFIED-UNSOLICITED CACHE STATE
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Patent #:
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Issue Dt:
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02/19/2002
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Application #:
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09437180
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Filing Dt:
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11/09/1999
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Title:
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CACHE COHERENCY PROTOCOL THAT PROVIDES A FLAG FROM AN INTERVENING CACHE TO INDICATE DEALLOCATION OF A MODIFIED CACHE LINE
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Patent #:
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Issue Dt:
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02/05/2002
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Application #:
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09437181
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Filing Dt:
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11/09/1999
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Title:
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CACHE ALLOCATION MECHANISM FOR MODIFIED UNSOLICITED CACHE STATE THAT MODIFIES VICTIMIZATION PRIORITY BITS
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Patent #:
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Issue Dt:
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10/21/2008
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Application #:
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09458883
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Filing Dt:
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12/10/1999
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Title:
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PREFETCHING USING FUTURE BRANCH PATH INFORMATION DERIVED FROM BRANCH PREDICTION*
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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09478311
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Filing Dt:
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01/06/2000
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Title:
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MICROPROCESSOR WITH PRIMARY AND SECONDARY ISSUE QUEUE
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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09504610
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Filing Dt:
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02/15/2000
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Title:
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SYSTEM AND METHOD FOR DYNAMICALLY ALLOCATING COMPUTER MEMORY BASED ON BLOCK SIZE
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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09514630
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Filing Dt:
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02/28/2000
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Title:
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COMPOSITE UNIPROCESSOR
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Patent #:
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Issue Dt:
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08/15/2006
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Application #:
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09542189
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Filing Dt:
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04/04/2000
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Title:
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NETWORK PROCESSOR WHICH MAKES THREAD EXECUTION CONTROL DECISIONS BASED ON LATENCY EVENT LENGTHS
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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09542206
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Filing Dt:
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04/04/2000
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Title:
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CONTROLLER FOR MULTIPLE INSTRUCTION THREAD PROCESSORS
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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09597769
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Filing Dt:
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06/20/2000
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Title:
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DUAL MASTER DEVICE FOR IMPROVED UTILIZATION OF A PROCESSOR LOCAL BUS
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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09598434
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Filing Dt:
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06/22/2000
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Title:
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PROCESSOR AND METHOD OF EXECUTING LOAD INSTRUCTIONS OUT-OF-ORDER HAVING REDUCED HAZARD PENALTY
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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09598435
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Filing Dt:
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06/22/2000
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Title:
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PROCESSOR AND METHOD HAVING A LOAD REORDER QUEUE THAT SUPPORTS RESERVATIONS
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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09626247
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Filing Dt:
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07/26/2000
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Title:
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BRANCH TARGET CACHE AND METHOD FOR EFFICIENTLY OBTAINING TARGET PATH INSTRUCTIONS FOR TIGHT PROGRAM LOOPS
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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09645081
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Filing Dt:
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08/24/2000
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Title:
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METHOD FOR IMPLEMENTING A VARIABLE-PARTITIONED QUEUE FOR SIMULTANEOUS MULTITHREADED PROCESSORS
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Patent #:
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Issue Dt:
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03/29/2005
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Application #:
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09740440
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Filing Dt:
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12/19/2000
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Publication #:
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Pub Dt:
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06/20/2002
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Title:
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EMPLOYING A DATA MOVER TO COMMUNICATE BETWEEN DYNAMICALLY SELECTED ZONES OF A CENTRAL PROCESSING COMPLEX
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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09765163
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Filing Dt:
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01/19/2001
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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PREFETCHING INSTRUCTIONS IN MIS-PREDICTED PATH FOR LOW CONFIDENCE BRANCHES
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09832064
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Filing Dt:
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04/10/2001
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Publication #:
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Pub Dt:
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01/03/2002
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Title:
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SYSTEM AND METHOD FOR POWER OPTIMIZATION IN PARALLEL UNITS
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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09855831
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Filing Dt:
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05/15/2001
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Publication #:
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Pub Dt:
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05/23/2002
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Title:
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MULTI-MASTER COMPUTER SYSTEM WITH OVERLAPPED READ AND WRITE OPERATIONS AND SCALABLE ADDRESS PIPELINING
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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09859247
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Filing Dt:
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05/17/2001
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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COMPRESSION OF EXECUTION PATH HISTORY TO IMPROVE BRANCH PREDICTION ACCURACY
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Patent #:
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Issue Dt:
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01/10/2006
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Application #:
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09864590
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Filing Dt:
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05/24/2001
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Publication #:
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Pub Dt:
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02/21/2002
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Title:
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UNIVERSAL LOAD ADDRESS/VALUE PREDICTION USING STRIDE-BASED PATTERN HISTORY AND LAST-VALUE PREDICTION IN A TWO-LEVEL TABLE SCHEME
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Patent #:
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Issue Dt:
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11/15/2005
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Application #:
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09895227
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Filing Dt:
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06/29/2001
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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MULTITHREADED PROCESSOR EFFICIENCY BY PREFETCHING INSTRUCTIONS FOR A SCHEDULED THREAD
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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09895888
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Filing Dt:
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06/29/2001
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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SYMMETRIC MULTIPROCESSOR COHERENCE MECHANISM
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Patent #:
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Issue Dt:
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01/04/2005
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Application #:
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09929805
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Filing Dt:
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08/14/2001
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Publication #:
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Pub Dt:
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02/20/2003
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Title:
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SIMD DATAPATH COUPLED TO SCALAR/VECTOR/ADDRESS/CONDITIONAL DATA REGISTER FILE WITH SELECTIVE SUBPATH SCALAR PROCESSING MODE
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Patent #:
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Issue Dt:
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05/23/2006
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Application #:
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09940911
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Filing Dt:
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08/28/2001
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Publication #:
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Pub Dt:
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03/20/2003
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Title:
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METHOD AND APPARATUS FOR ALIGNING MEMORY WRITE DATA IN A MICROPROCESSOR
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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10005426
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Filing Dt:
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11/07/2001
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Publication #:
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Pub Dt:
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10/24/2002
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Title:
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PARTITIONED CACHE OF MULTIPLE LOGICAL LEVELS WITH ADAPTIVE RECONFIGURATION BASED ON MULTIPLE CRITERIA
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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10045821
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Filing Dt:
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01/09/2002
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Publication #:
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Pub Dt:
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07/10/2003
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Title:
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MULTI-LEVEL CLASSIFICATION METHOD FOR TRANSACTION ADDRESS CONFLICTS FOR ENSURING EFFICIENT ORDERING IN A TWO-LEVEL SNOOPY CACHE ARCHITETURE
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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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10083579
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Filing Dt:
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02/27/2002
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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METHOD AND APPARATUS FOR FAULT-TOLERANCE VIA DUAL THREAD CROSSCHECKING
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Issue Dt:
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12/27/2005
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Application #:
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10105125
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03/21/2002
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Publication #:
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Pub Dt:
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09/25/2003
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Title:
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CRITICAL DATAPATH ERROR HANDLING IN A MULTIPROCESSOR ARCHITECTURE
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Patent #:
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Issue Dt:
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03/27/2007
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Application #:
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10122875
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Filing Dt:
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04/11/2002
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Publication #:
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Pub Dt:
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10/16/2003
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Title:
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METHOD AND APPARATUS FOR MANAGING LOW POWER PROCESSOR STATES
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10126239
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Filing Dt:
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04/19/2002
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Publication #:
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Pub Dt:
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10/24/2002
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Title:
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METHOD FOR SHARING A TRANSLATION LOOKASIDE BUFFER BETWEEN CPUS
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Patent #:
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Issue Dt:
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04/28/2009
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Application #:
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10202722
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07/25/2002
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Publication #:
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Pub Dt:
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01/29/2004
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Title:
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DATA PATH MASTER/SLAVE DATA PROCESSING DEVICE APPARATUS AND METHOD
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Issue Dt:
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12/13/2005
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10249304
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03/28/2003
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Pub Dt:
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09/30/2004
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Title:
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REDUCING LATENCY OF A SNOOP TENURE
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Issue Dt:
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02/01/2005
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Application #:
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10261886
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09/30/2002
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02/06/2003
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SYSTEM AND METHOD FOR PERSISTENT AND ROBUST STORAGE ALLOCATION
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04/25/2006
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10264170
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10/03/2002
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Pub Dt:
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04/08/2004
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Title:
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RE-ORDERING A FIRST REQUEST WITHIN A FIFO REQUEST QUEUE TO A DIFFERENT QUEUE POSITION WHEN THE FIRST REQUEST RECEIVES A RETRY RESPONSE FROM THE TARGET
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Issue Dt:
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02/07/2006
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10295507
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11/14/2002
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Publication #:
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Pub Dt:
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05/20/2004
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Title:
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SYSTEM AND METHOD FOR IMPLEMENTING AN ADAPTIVE REPLACEMENT CACHE POLICY
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10322127
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Filing Dt:
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12/17/2002
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Publication #:
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Pub Dt:
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06/17/2004
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Title:
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ON-CHIP DATA TRANSFER IN MULTI-PROCESSOR SYSTEM
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Patent #:
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Issue Dt:
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08/22/2006
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Application #:
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10346293
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Filing Dt:
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01/16/2003
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Publication #:
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Pub Dt:
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07/22/2004
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Title:
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SENDER TO RECEIVER REQUEST RETRY METHOD AND APPARATUS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10401411
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Filing Dt:
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03/27/2003
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Publication #:
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Pub Dt:
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09/30/2004
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Title:
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DMA prefetch
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Patent #:
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Issue Dt:
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10/09/2007
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Application #:
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10422513
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Filing Dt:
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04/24/2003
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Publication #:
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Pub Dt:
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10/28/2004
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Title:
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VIRTUALIZATION OF A GLOBAL INTERRUPT QUEUE
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10422662
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04/24/2003
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Publication #:
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Pub Dt:
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10/28/2004
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Title:
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METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR DYNAMICALLY MINIMIZING TRANSLATION LOOKASIDE BUFFER ENTRIES ACROSS CONTIGUOUS MEMORY
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Patent #:
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Issue Dt:
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03/20/2007
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Application #:
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10422677
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Filing Dt:
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04/24/2003
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04/14/2005
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07/14/2005
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07/14/2005
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07/21/2005
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07/28/2005
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08/23/2011
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01/27/2005
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12/11/2007
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07/06/2006
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06/30/2005
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05/27/2008
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10/05/2006
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10/05/2006
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01/23/2007
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10/18/2007
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10/18/2007
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NOVEL SNOOP FILTER FOR FILTERING SNOOP REQUESTS
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