|
Total properties:
80
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|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
13149628
|
Filing Dt:
|
05/31/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming EWLB Semiconductor Package with Vertical Interconnect Structure and Cavity Region
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/17/2015
|
Application #:
|
13163026
|
Filing Dt:
|
06/17/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming RF FEM and RF Transceiver in Semiconductor Package
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2013
|
Application #:
|
13167566
|
Filing Dt:
|
06/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE COATING OVER INTERCONNECT STRUCTURE TO INHIBIT SURFACE OXIDATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2016
|
Application #:
|
13195636
|
Filing Dt:
|
08/01/2011
|
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming POP With Stacked Semiconductor Die and Bumps Formed Directly on the Lower Die
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2015
|
Application #:
|
13208027
|
Filing Dt:
|
08/11/2011
|
|
Publication #:
|
|
Pub Dt:
|
02/14/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming a Stackable Semiconductor Package with Vertically-Oriented Discrete Electrical Devices as Interconnect Structures
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13218388
|
Filing Dt:
|
08/25/2011
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming TIM Within Recesses of MUF Material
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
08/20/2019
|
Application #:
|
13225683
|
Filing Dt:
|
09/06/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
|
Title:
|
Semiconductor device and method of forming FO-WLCSP with recessed interconnect area in peripheral region of semiconductor die
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2018
|
Application #:
|
13226767
|
Filing Dt:
|
09/07/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming a Low Profile Dual-Purpose Shield and Heat-Dissipation Structure
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2016
|
Application #:
|
13234366
|
Filing Dt:
|
09/16/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Conductive Protrusions Over Conductive Pillars or Bond Pads as Fixed Offset Vertical Interconnect Structure
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2015
|
Application #:
|
13234535
|
Filing Dt:
|
09/16/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A RECONFIGURED STACKABLE WAFER LEVEL PACKAGE WITH VERTICAL INTERCONNECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2016
|
Application #:
|
13236952
|
Filing Dt:
|
09/20/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR PACKAGE USING PANEL FORM CARRIER
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/01/2016
|
Application #:
|
13239080
|
Filing Dt:
|
09/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTION AND SUPPORT STRUCTURE FOR CONDUCTIVE INTERCONNECT STRUCTURE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13242656
|
Filing Dt:
|
09/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/22/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED UNDER-FILL AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2017
|
Application #:
|
13243214
|
Filing Dt:
|
09/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Interconnect Substrate for FO-WLCSP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2016
|
Application #:
|
13243558
|
Filing Dt:
|
09/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2015
|
Application #:
|
13287006
|
Filing Dt:
|
11/01/2011
|
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DIE AND METHOD OF FORMING SLOPED SURFACE IN PHOTORESIST LAYER TO ENHANCE FLOW OF UNDERFILL MATERIAL BETWEEN SEMICONDUCTOR DIE AND SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2016
|
Application #:
|
13287035
|
Filing Dt:
|
11/01/2011
|
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THERMAL INTERFACE MATERIAL AND HEAT SPREADER OVER SEMICONDUCTOR DIE
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13289811
|
Filing Dt:
|
11/04/2011
|
|
Publication #:
|
|
Pub Dt:
|
05/09/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Sloped Surface in Patterning Layer to Separate Bumps of Semiconductor Die from Patterning Layer
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2015
|
Application #:
|
13303019
|
Filing Dt:
|
11/22/2011
|
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH CONDUCTIVE LAYER OVER SUBSTRATE WITH VENTS TO CHANNEL BUMP MATERIAL AND REDUCE INTERCONNECT VOIDS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
13307849
|
Filing Dt:
|
11/30/2011
|
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RDL UNDER BUMP FOR ELECTRICAL CONNECTION TO ENCLOSED BUMP
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/24/2015
|
Application #:
|
13312730
|
Filing Dt:
|
12/06/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
13314984
|
Filing Dt:
|
12/08/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MAKING SINGLE LAYER SUBSTRATE WITH ASYMMETRICAL FIBERS AND REDUCED WARPAGE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/17/2013
|
Application #:
|
13315010
|
Filing Dt:
|
12/08/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THICK ENCAPSULANT FOR STIFFNESS WITH RECESSES FOR STRESS RELIEF IN FO-WLCSP
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13315033
|
Filing Dt:
|
12/08/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING GUARD RING AROUND CONDUCTIVE TSV THROUGH SEMICONDUCTOR WAFER
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|
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|
Patent #:
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|
Issue Dt:
|
06/03/2014
|
Application #:
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13324349
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Filing Dt:
|
12/13/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Conductive Pillars Having Recesses or Protrusions to Detect Interconnect Continuity Between Semiconductor Die and Substrate
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|
|
|
|
Patent #:
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|
Issue Dt:
|
06/20/2017
|
Application #:
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13324397
|
Filing Dt:
|
12/13/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Recesses in Conductive Layer to Detect Continuity for Interconnect Between Semiconductor Die and Substrate
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/19/2014
|
Application #:
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13324446
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Filing Dt:
|
12/13/2011
|
|
Publication #:
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|
Pub Dt:
|
06/13/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING UBM STRUCTURE ON BACK SURFACE OF TSV SEMICONDUCTOR WAFER
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|
|
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|
Patent #:
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|
Issue Dt:
|
11/26/2013
|
Application #:
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13326128
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Filing Dt:
|
12/14/2011
|
|
Publication #:
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|
Pub Dt:
|
06/20/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT STRUCTURE WITH CONDUCTIVE MICRO VIA ARRAY FOR 3-D FO-WLCSP
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|
Patent #:
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|
Issue Dt:
|
06/03/2014
|
Application #:
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13333395
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Filing Dt:
|
12/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
|
Title:
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Semiconductor Device and Method of Forming Insulating Layer in Notches Around Conductive TSV for Stress Relief
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/01/2016
|
Application #:
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13336860
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Filing Dt:
|
12/23/2011
|
|
Publication #:
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|
Pub Dt:
|
06/27/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING EXTENDED SEMICONDUCTOR DEVICE WITH FAN-OUT INTERCONNECT STRUCTURE TO REDUCE COMPLEXITY OF SUBSTRATE
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Patent #:
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|
Issue Dt:
|
09/03/2013
|
Application #:
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13366008
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Filing Dt:
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02/03/2012
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|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Reconstituted Wafer with Larger Carrier to Achieve More EWLB Packages per Wafer with Encapsulant Deposited Under Temperature and Pressure
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|
Patent #:
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|
Issue Dt:
|
02/04/2014
|
Application #:
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13417034
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Filing Dt:
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03/09/2012
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|
Publication #:
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|
Pub Dt:
|
09/12/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING NON-LINEAR INTERCONNECT LAYER WITH EXTENDED LENGTH FOR JOINT RELIABILITY
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|
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|
Patent #:
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|
Issue Dt:
|
11/21/2017
|
Application #:
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13468981
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Filing Dt:
|
05/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLAR HAVING AN EXPANDED BASE
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|
|
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|
Patent #:
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|
Issue Dt:
|
07/14/2015
|
Application #:
|
13478008
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Filing Dt:
|
05/22/2012
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|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTION AND SUPPORT STRUCTURE FOR CONDUCTIVE INTERCONNECT STRUCTURE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/07/2017
|
Application #:
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13545887
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Filing Dt:
|
07/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
|
Title:
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Semiconductor Device and Method of Forming Semiconductor Die with Active Region Responsive to External Stimulus
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|
Patent #:
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|
Issue Dt:
|
02/02/2016
|
Application #:
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13566872
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Filing Dt:
|
08/03/2012
|
|
Publication #:
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|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF STACKING SEMICONDUCTOR DIE IN MOLD LASER PACKAGE INTERCONNECTED BY BUMPS AND CONDUCTIVE VIAS
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|
Patent #:
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|
Issue Dt:
|
08/27/2013
|
Application #:
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13570979
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Filing Dt:
|
08/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
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Semiconductor Device and Method of Forming WLCSP Structure using Protruded MLP
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|
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|
Patent #:
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|
Issue Dt:
|
07/14/2015
|
Application #:
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13572517
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Filing Dt:
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08/10/2012
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|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
Semicinductor Device with Cross-Talk Isolation Using M-CAP
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|
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|
Patent #:
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|
Issue Dt:
|
02/02/2016
|
Application #:
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13604539
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Filing Dt:
|
09/05/2012
|
|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming a Conductive Via-in-Via Structure
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/16/2016
|
Application #:
|
13607204
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Filing Dt:
|
09/07/2012
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|
Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming FO-WLCSP with Discrete Semiconductor Components Mounted Under and Over Semiconductor Die
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13609003
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Filing Dt:
|
09/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
|
Title:
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Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump
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|
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|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13609050
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Filing Dt:
|
09/10/2012
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|
Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
|
Title:
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Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor Die
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|
Patent #:
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|
Issue Dt:
|
01/19/2016
|
Application #:
|
13621804
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Filing Dt:
|
09/17/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/17/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH SOLDER BUMP FORMED ON HIGH TOPOGRAPHY PLATED CU PADS
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|
Patent #:
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|
Issue Dt:
|
11/03/2015
|
Application #:
|
13621810
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Filing Dt:
|
09/17/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/17/2013
| | | | |
|
Title:
|
SOLDER BUMP WITH INNER CORE PILLAR IN SEMICONDUCTOR PACKAGE
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|
|
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|
Patent #:
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|
Issue Dt:
|
05/10/2016
|
Application #:
|
13622280
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Filing Dt:
|
09/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/17/2013
| | | | |
|
Title:
|
Method of Forming an Inductor on a Semiconductor Wafer
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/22/2015
|
Application #:
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13622297
|
Filing Dt:
|
09/18/2012
|
|
Publication #:
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|
Pub Dt:
|
01/17/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE SUBSTRATE WITH CAVITIES FORMED THROUGH ETCH-RESISTANT CONDUCTIVE LAYER FOR BUMP LOCKING
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|
Patent #:
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|
Issue Dt:
|
12/12/2017
|
Application #:
|
13645385
|
Filing Dt:
|
10/04/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/31/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT IN FO-WLCSP USING LEADFRAME DISPOSED BETWEEN SEMICONDUCTOR DIE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
10/13/2015
|
Application #:
|
13645397
|
Filing Dt:
|
10/04/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/31/2013
| | | | |
|
Title:
|
FLIP CHIP INTERCONNECTION HAVING NARROW INTERCONNECTION SITES ON THE SUBSTRATE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
07/11/2017
|
Application #:
|
13678134
|
Filing Dt:
|
11/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RF FEM WITH LC FILTER AND IPD FILTER OVER SUBSTRATE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/06/2016
|
Application #:
|
13682281
|
Filing Dt:
|
11/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
|
Title:
|
SEMICONDUCTOR PACKAGE AND METHOD OF FORMING Z-DIRECTION CONDUCTIVE POSTS EMBEDDED IN STRUCTURALLY PROTECTIVE ENCAPSULANT
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|
Patent #:
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|
Issue Dt:
|
08/16/2016
|
Application #:
|
13682510
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Filing Dt:
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11/20/2012
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Publication #:
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Pub Dt:
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03/28/2013
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Title:
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Semiconductor Device and Method of Forming Insulating Layer on Conductive Traces for Electrical Isolation in Fine Pitch Bonding
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Patent #:
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Issue Dt:
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08/04/2015
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Application #:
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13683884
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Filing Dt:
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11/21/2012
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Publication #:
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Pub Dt:
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03/28/2013
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS EMBEDDED IN PHOTOSENSITIVE ENCAPSULANT
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Patent #:
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Issue Dt:
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06/23/2015
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Application #:
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13683946
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Filing Dt:
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11/21/2012
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Publication #:
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Pub Dt:
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05/02/2013
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS AND HEAT SINK OVER SEMICONDUCTOR DIE USING LEADFRAME
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Patent #:
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Issue Dt:
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10/06/2015
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Application #:
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13691464
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
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04/11/2013
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED MULTI-DIE LEADFRAME FOR ELECTRICAL INTERCONNECT OF STACKED SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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01/19/2016
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Application #:
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13715424
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Filing Dt:
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12/14/2012
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Publication #:
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Pub Dt:
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11/06/2014
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Title:
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Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect
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Patent #:
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Issue Dt:
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11/01/2016
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Application #:
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13716799
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Filing Dt:
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12/17/2012
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Publication #:
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Pub Dt:
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04/25/2013
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Title:
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Semiconductor Device and Method of Forming Directional RF Coupler with IPD for Additional RF Signal Processing
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Patent #:
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Issue Dt:
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10/04/2016
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Application #:
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13720516
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Filing Dt:
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12/19/2012
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Publication #:
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Pub Dt:
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07/11/2013
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Title:
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Semiconductor Device and Method of Forming Reduced Surface Roughness in Molded Underfill for Improved C-SAM Inspection
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Patent #:
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Issue Dt:
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09/04/2018
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Application #:
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13726467
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Filing Dt:
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12/24/2012
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Publication #:
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Pub Dt:
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06/06/2013
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING CAVITY IN BUILD-UP INTERCONNECT STRUCTURE FOR SHORT SIGNAL PATH BETWEEN DIE
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Patent #:
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Issue Dt:
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06/03/2014
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Application #:
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13727116
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Filing Dt:
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12/26/2012
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Publication #:
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Pub Dt:
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05/30/2013
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Title:
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SEMICONDUCTOR DEVICE HAVING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
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Patent #:
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Issue Dt:
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12/13/2016
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Application #:
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13728012
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Filing Dt:
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12/27/2012
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Publication #:
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Pub Dt:
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06/06/2013
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Title:
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SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SEMICONDUCTOR PACKAGE HAVING BUILD-UP INTERCONNECT STRUCTURE OVER SEMICONDUCTOR DIE WITH DIFFERENT CTE INSULATING LAYERS
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Patent #:
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Issue Dt:
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12/30/2014
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Application #:
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13732150
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Filing Dt:
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12/31/2012
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Publication #:
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Pub Dt:
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05/16/2013
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Title:
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Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected through Conductive Vias Formed in Encapsulant Around Die
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Patent #:
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Issue Dt:
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05/12/2015
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Application #:
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13760187
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Filing Dt:
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02/06/2013
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Publication #:
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Pub Dt:
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06/13/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADJACENT CHANNEL AND DAM MATERIAL AROUND DIE ATTACH AREA OF SUBSTRATE TO CONTROL OUTWARD FLOW OF UNDERFILL MATERIAL
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Patent #:
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Issue Dt:
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04/22/2014
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Application #:
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13765478
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Filing Dt:
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02/12/2013
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Publication #:
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Pub Dt:
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07/04/2013
| | | | |
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Title:
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Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)
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Patent #:
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Issue Dt:
|
01/12/2016
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Application #:
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13765594
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Filing Dt:
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02/12/2013
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Publication #:
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Pub Dt:
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06/20/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECT STRUCTURE ON LEADFRAME
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|
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Patent #:
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Issue Dt:
|
11/04/2014
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Application #:
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13766493
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Filing Dt:
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02/13/2013
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Publication #:
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Pub Dt:
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06/13/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER AROUND SEMICONDUCTOR DIE
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|
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Patent #:
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Issue Dt:
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10/21/2014
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Application #:
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13766646
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Filing Dt:
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02/13/2013
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Publication #:
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Pub Dt:
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06/20/2013
| | | | |
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Title:
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LEADFRAME INTERPOSER OVER SEMICONDUCTOR DIE AND TSV SUBSTRATE FOR VERTICAL ELECTRICAL INTERCONNECT
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|
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Patent #:
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Issue Dt:
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04/29/2014
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Application #:
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13768862
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Filing Dt:
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02/15/2013
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Publication #:
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Pub Dt:
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06/20/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES
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Patent #:
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Issue Dt:
|
09/16/2014
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Application #:
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13769302
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Filing Dt:
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02/16/2013
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Publication #:
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Pub Dt:
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08/08/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PRE-MOLDED SUBSTRATE TO REDUCE WARPAGE DURING DIE MOLDING
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Patent #:
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Issue Dt:
|
01/30/2018
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Application #:
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13771825
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Filing Dt:
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02/20/2013
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Publication #:
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Pub Dt:
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09/12/2013
| | | | |
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Title:
|
Thin 3D Fan-Out Embedded Wafer Level Package (EWLB) for Application Processor and Memory Integration
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Patent #:
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Issue Dt:
|
03/22/2016
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Application #:
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13772683
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Filing Dt:
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02/21/2013
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Publication #:
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Pub Dt:
|
09/05/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD FOR FORMING A LOW PROFILE EMBEDDED WAFER LEVEL BALL GRID ARRAY MOLDED LASER PACKAGE (EWLB-MLP)
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|
|
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Patent #:
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|
Issue Dt:
|
06/24/2014
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Application #:
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13782618
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF
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|
|
|
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Patent #:
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|
Issue Dt:
|
09/20/2016
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Application #:
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13782939
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Filing Dt:
|
03/01/2013
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Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
|
Title:
|
Integrated Passive Devices
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|
|
|
|
Patent #:
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|
Issue Dt:
|
06/23/2015
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Application #:
|
13832333
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Filing Dt:
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03/15/2013
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Publication #:
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Pub Dt:
|
08/08/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING A VERTICAL INTERCONNECT STRUCTURE FOR 3-D FO-WLCSP
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|
|
|
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Patent #:
|
|
Issue Dt:
|
07/29/2014
|
Application #:
|
13845329
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Filing Dt:
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03/18/2013
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Publication #:
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Pub Dt:
|
08/15/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-up Interconnect Structure
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|
|
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Patent #:
|
|
Issue Dt:
|
12/20/2016
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Application #:
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13845409
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Filing Dt:
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03/18/2013
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Publication #:
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Pub Dt:
|
08/22/2013
| | | | |
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Title:
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PACKAGE-IN-PACKAGE USING THROUGH-HOLE VIA DIE ON SAW STREETS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
06/13/2017
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Application #:
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13845542
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Filing Dt:
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03/18/2013
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Publication #:
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Pub Dt:
|
08/22/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Bond-on-Lead Interconnection for Mounting Semiconductor Die in FO-WLCSP
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|
|
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Patent #:
|
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Issue Dt:
|
03/07/2017
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Application #:
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13846014
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Filing Dt:
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03/18/2013
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Publication #:
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Pub Dt:
|
08/22/2013
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE LEADS FROM BASE SUBSTRATE AS STANDOFF FOR STACKING SEMICONDUCTOR DIE
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|
|
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Patent #:
|
|
Issue Dt:
|
12/16/2014
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Application #:
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13846742
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Filing Dt:
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03/18/2013
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Publication #:
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Pub Dt:
|
09/05/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE COATING OVER INTERCONNECT STRUCTURE TO INHIBIT SURFACE OXIDATION
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|
|
|
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Patent #:
|
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Issue Dt:
|
01/24/2017
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Application #:
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13853969
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Filing Dt:
|
03/29/2013
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|
Publication #:
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Pub Dt:
|
08/29/2013
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR DIE WITH ACTIVE REGION RESPONSIVE TO EXTERNAL STIMULUS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/25/2014
|
Application #:
|
13870928
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Filing Dt:
|
04/25/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/12/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Vertically Offset Conductive Pillars Over First Substrate Aligned to Vertically Offset BOT Interconnect Sites Formed Over Second Substrate
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|
