|
Total properties:
62
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|
|
|
Patent #:
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|
Issue Dt:
|
04/13/1999
|
Application #:
|
07769185
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Filing Dt:
|
09/30/1991
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Title:
|
INTEGRATED CIRCUIT DEVICE STRUCTURE HAVING HALO REGIONS
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Patent #:
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|
Issue Dt:
|
11/10/1998
|
Application #:
|
08172854
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Filing Dt:
|
12/22/1993
|
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Title:
|
STRESS TEST MODE
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|
|
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|
Patent #:
|
|
Issue Dt:
|
02/23/1999
|
Application #:
|
08182809
|
Filing Dt:
|
01/14/1994
|
|
Title:
|
MOSFET ISOLATION STRUCTURE WITH PLANAR SURFACE
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|
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|
Patent #:
|
|
Issue Dt:
|
02/09/1999
|
Application #:
|
08407767
|
Filing Dt:
|
03/21/1995
|
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Title:
|
METHOD OF GETTERING USING DOPED SOG AND A PLANARIZATION TECHNIQUE
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|
Patent #:
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|
Issue Dt:
|
01/05/1999
|
Application #:
|
08434179
|
Filing Dt:
|
05/03/1995
|
|
Title:
|
METHOD OF FORMING A FIELD PROGRAMMABLE DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/1998
|
Application #:
|
08436165
|
Filing Dt:
|
05/08/1995
|
|
Title:
|
CONTACTS FOR SEMICONDUCTOR DEVICES
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/09/1999
|
Application #:
|
08441778
|
Filing Dt:
|
05/16/1995
|
|
Title:
|
INTEGRATED CIRCUIT STRUCTURE HAVING TWO PHOTORESIST LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/1998
|
Application #:
|
08448703
|
Filing Dt:
|
05/24/1995
|
|
Title:
|
SEMICONDUCTOR CONTACT VIA STRUCTURE AND METHOD
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/1998
|
Application #:
|
08477283
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
INPUT BUFFER CIRCUIT IMMUNE TO COMMON MODE POWER SUPPLY FLUCTUATIONS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/1998
|
Application #:
|
08488398
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
INVERTED FIELD-EFFECT DEVICE WITH POLYCRYSTALLINE SILICON/GERMANIUM CHANNEL
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|
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|
Patent #:
|
|
Issue Dt:
|
02/09/1999
|
Application #:
|
08552383
|
Filing Dt:
|
11/03/1995
|
|
Title:
|
STRUCTURE AND PROCESS FOR REDUCING THE ON-RESISTANCE OF MOS-GATED POWER DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/1998
|
Application #:
|
08552440
|
Filing Dt:
|
11/03/1995
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH BACK TO BACK DIODE ELEMENT
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|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/1998
|
Application #:
|
08574659
|
Filing Dt:
|
12/19/1995
|
|
Title:
|
SUBMICRON CONTACTS AND VIAS IN AN INTEGRATED CIRCUIT
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|
|
|
Patent #:
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|
Issue Dt:
|
11/07/2000
|
Application #:
|
08587709
|
Filing Dt:
|
01/19/1996
|
|
Title:
|
TEST MODE ACTIVATION AND DATA OVERRIDE
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|
|
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|
Patent #:
|
|
Issue Dt:
|
01/26/1999
|
Application #:
|
08587711
|
Filing Dt:
|
01/19/1996
|
|
Title:
|
CIRCUIT AND METHOD FOR SETTING THE TIME DURATION OF A WRITE TO A MEMORY CELL
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|
Patent #:
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|
Issue Dt:
|
12/01/1998
|
Application #:
|
08588762
|
Filing Dt:
|
01/19/1996
|
|
Title:
|
DATA-INPUT DEVICE FOR GENERATING TEST SIGNALS ON BIT AND BIT-COMPLEMENT LINES
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/24/1998
|
Application #:
|
08626540
|
Filing Dt:
|
04/02/1996
|
|
Title:
|
TESTING AND REPAIR OF EMBEDDED MEMORY
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|
Patent #:
|
|
Issue Dt:
|
09/08/1998
|
Application #:
|
08644078
|
Filing Dt:
|
05/09/1996
|
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Title:
|
METHOD OF MAKING SPACER-TYPE THIN-FILM POLYSILICON TRANSISTOR FOR LOW-POWER MEMORY DEVICES
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|
Patent #:
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|
Issue Dt:
|
11/24/1998
|
Application #:
|
08647222
|
Filing Dt:
|
05/09/1996
|
|
Title:
|
APPARATUS FOR TESTING SIGNAL TIMING AND PROGRAMMING DELAY
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/03/1998
|
Application #:
|
08679138
|
Filing Dt:
|
07/12/1996
|
|
Title:
|
PROCESS MONITOR TEST CHIP AND METHODOLOGY
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|
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|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08690738
|
Filing Dt:
|
07/31/1996
|
|
Title:
|
METHOD OF FORMING AN IMPROVED PLANAR ISOLATION STRUCTURE IN AN INTEGRATED CIRCUIT
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|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/1998
|
Application #:
|
08698129
|
Filing Dt:
|
08/15/1996
|
|
Title:
|
INVERTED FIELD-EFFECT DEVICE WITH POLYCRYSTALLINE SILICON/GERMANIUM CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/1998
|
Application #:
|
08702911
|
Filing Dt:
|
08/26/1996
|
|
Title:
|
VIDEO AND/OR AUDIO DECOMPRESSION AND/OR COMPRESSION DEVICE THAT SHARES A MEMORY INTERFACE
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|
|
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|
Patent #:
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|
Issue Dt:
|
10/13/1998
|
Application #:
|
08704153
|
Filing Dt:
|
08/28/1996
|
|
Title:
|
ISOLATION BY ACTIVE TRANSISTORS WITH GROUNDED GATES
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|
|
|
Patent #:
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|
Issue Dt:
|
01/19/1999
|
Application #:
|
08710356
|
Filing Dt:
|
09/17/1996
|
|
Title:
|
INTEGRATED-CIRCUIT DIE SUITABLE FOR WAFER-LEVEL TESTING AND METHOD FOR FORMING THE SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/1998
|
Application #:
|
08712808
|
Filing Dt:
|
09/12/1996
|
|
Title:
|
STRUCTURE FOR TRANSISTOR DEVICES IN AN SRAM CELL
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/15/1998
|
Application #:
|
08720686
|
Filing Dt:
|
10/02/1996
|
|
Title:
|
PLASTIC PIN GRID ARRAY PACKAGE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
01/12/1999
|
Application #:
|
08723713
|
Filing Dt:
|
09/27/1996
|
|
Title:
|
MOTOR WITH INPUT-CONTROLLED HIGH SIDE DRIVER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/1998
|
Application #:
|
08736524
|
Filing Dt:
|
10/24/1996
|
|
Title:
|
DRIVER CIRCUIT INCLUDING SLEW RATE CONTROL SYSTEM WITH IMPROVED VOLTAGE RAMP GENERATOR
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|
|
|
Patent #:
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|
Issue Dt:
|
12/08/1998
|
Application #:
|
08738040
|
Filing Dt:
|
10/24/1996
|
|
Title:
|
STRUCTURE AND METHOD OF FORMING VIAS
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|
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|
Patent #:
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|
Issue Dt:
|
10/27/1998
|
Application #:
|
08740129
|
Filing Dt:
|
10/24/1996
|
|
Title:
|
DRIVER CIRCUIT INCLUDING AMPLIFIER OPERATED IN A SWITCHING MODE
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Patent #:
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|
Issue Dt:
|
01/05/1999
|
Application #:
|
08743380
|
Filing Dt:
|
11/04/1996
|
|
Title:
|
VIAS AND CONTACT PLUGS WITH AN ASPECT RATIO LOWER THAN THE ASPECT RATIO OF THE STRUCTURE IN WHICH THEY ARE FORMED
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/08/1998
|
Application #:
|
08756460
|
Filing Dt:
|
11/26/1996
|
|
Title:
|
LOW-PROFILE SOCKETED PACKAGING SYSTEM WITH LAND-GRID ARRAY AND THERMALLY CONDUCTIVE SLUG
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|
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|
|
Patent #:
|
|
Issue Dt:
|
10/27/1998
|
Application #:
|
08758340
|
Filing Dt:
|
12/03/1996
|
|
Title:
|
NETHOD OF FORMING A LANDING PAD STRUCTURE IN AN INTEGRATED CIRCUIT
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|
|
Patent #:
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|
Issue Dt:
|
02/16/1999
|
Application #:
|
08758723
|
Filing Dt:
|
12/30/1996
|
|
Title:
|
TRUCTURE AND METHOD OF FORMING AN ENLARGED HEAD ON A PLUG TO ELIMINATE THE ENCLOSURE REQUIREMENT
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|
Patent #:
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|
Issue Dt:
|
09/14/1999
|
Application #:
|
08762608
|
Filing Dt:
|
12/09/1996
|
|
Title:
|
SYNCHRONIZING AN AUDIO-VISUAL STREAM SYNCHRONIZED TO A CLOCK WITH A VIDEO DISPLAY THAT IS SYNCHRONIZED TO A DIFFERENT CLOCK
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|
|
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|
Patent #:
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|
Issue Dt:
|
11/03/1998
|
Application #:
|
08766404
|
Filing Dt:
|
12/12/1996
|
|
Title:
|
SRAM MEMORY CELL DESIGN HAVING COMPLEMENTARY DUAL PASS GATES
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|
|
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|
Patent #:
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|
Issue Dt:
|
09/22/1998
|
Application #:
|
08767343
|
Filing Dt:
|
12/16/1996
|
|
Title:
|
AN IMPROVED DIELECTRIC IN AN INTEGRATED CIRCUIT
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|
Patent #:
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|
Issue Dt:
|
11/10/1998
|
Application #:
|
08770548
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Filing Dt:
|
12/08/1996
|
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Title:
|
INTEGRATED CIRCUIT SENSING AND DIGITALLY BIASING THE THRESHOLD VOLTAGE OF TRANSISTORS AND RELATED METHODS
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|
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|
Patent #:
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|
Issue Dt:
|
02/15/2000
|
Application #:
|
08771670
|
Filing Dt:
|
12/23/1996
|
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Title:
|
ESD PROTECTION CIRCUITS
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Patent #:
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|
Issue Dt:
|
09/08/1998
|
Application #:
|
08773068
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Filing Dt:
|
12/26/1996
|
|
Title:
|
METHOD AND APPARATUS FOR TESTING HIGH-FREQUENCY INTEGRATED CIRCUITS USING A LOWER-FREQUENCY TESTER
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|
Patent #:
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|
Issue Dt:
|
02/09/1999
|
Application #:
|
08774911
|
Filing Dt:
|
12/27/1996
|
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Title:
|
METHOD OF MAKING AND STRUCTURE OF SRAM STORAGE CELL WITH N CHANNEL THIN FILM TRANSISTOR LOAD DEVICES
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|
Patent #:
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|
Issue Dt:
|
02/02/1999
|
Application #:
|
08775643
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Filing Dt:
|
12/31/1996
|
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Title:
|
LIQUID LEVEL GAUGE INTERFACE SYSTEM HAVING DYNAMIC OFFSET
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Patent #:
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|
Issue Dt:
|
11/10/1998
|
Application #:
|
08777635
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Filing Dt:
|
12/31/1996
|
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Title:
|
METHOD OF MAKING MULTIPLE-BOND SHELF PLASTIC PACKAGE
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|
Patent #:
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|
Issue Dt:
|
03/02/1999
|
Application #:
|
08782524
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Filing Dt:
|
01/10/1997
|
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Title:
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AMPLIFIER OUTPUT CLAMPING SCHEME
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Patent #:
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|
Issue Dt:
|
12/15/1998
|
Application #:
|
08808455
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Filing Dt:
|
02/28/1997
|
|
Title:
|
LOAD POLE STABILIZED VOLTAGE REGULATOR CIRCUIT
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Patent #:
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|
Issue Dt:
|
08/24/1999
|
Application #:
|
08814332
|
Filing Dt:
|
03/11/1997
|
|
Title:
|
METHOD AND APPARATUS FOR REDUCING A NOISE DIFFERENTIAL IN AN ELECTRONIC CIRCUIT
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|
Patent #:
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|
Issue Dt:
|
02/09/1999
|
Application #:
|
08814932
|
Filing Dt:
|
02/27/1997
|
|
Title:
|
PWM CONTROL OF MOTOR DRIVER
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|
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|
Patent #:
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|
Issue Dt:
|
10/06/1998
|
Application #:
|
08819597
|
Filing Dt:
|
03/17/1997
|
|
Title:
|
VOICE COIL MOTOR FEEDBACK CONTROL CIRCUIT
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|
|
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|
Patent #:
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|
Issue Dt:
|
01/05/1999
|
Application #:
|
08820406
|
Filing Dt:
|
03/12/1997
|
|
Title:
|
FIELD EFFECT TRANSISTOR HAVING DIELECTRICALLY ISOLATED SOURCES AND DRAINS
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|
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|
Patent #:
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|
Issue Dt:
|
11/10/1998
|
Application #:
|
08853143
|
Filing Dt:
|
05/08/1997
|
|
Title:
|
PROTECTION AGAINST ADVERSE PARASITIC EFFECTS IN JUNCTION-ISOLATED INTEGRATED CIRCUITS
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|
Patent #:
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Issue Dt:
|
10/20/1998
|
Application #:
|
08858788
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Filing Dt:
|
05/19/1997
|
|
Title:
|
CIRCUIT AND METHOD FOR TERMINATING A WRITE TO A MEMORY CELL
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/16/1999
|
Application #:
|
08862969
|
Filing Dt:
|
05/23/1997
|
|
Title:
|
METHOD OF STRESS TESTING INTEGRATED CIRCUIT HAVING MEMORY AND INTEGRATED CIRCUIT HAVING STRESS TESTER FOR MEMORY THEREOF
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
03/16/1999
|
Application #:
|
08886324
|
Filing Dt:
|
07/01/1997
|
|
Title:
|
BEMF RECTIFICATION DURING POWER OFF TO PREVENT PARASITIC EFFECT
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|
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|
Patent #:
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|
Issue Dt:
|
12/22/1998
|
Application #:
|
08889816
|
Filing Dt:
|
07/08/1997
|
|
Title:
|
VOLTAGE REGULATOR WITH LOAD POLE STABILIZATION
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/02/1999
|
Application #:
|
08905918
|
Filing Dt:
|
08/04/1997
|
|
Title:
|
CONTACT STRUCTURE FOR IMPROVING PHOTORESIST ADHESION ON A DIELECTRIC LAYER
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|
Patent #:
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|
Issue Dt:
|
12/29/1998
|
Application #:
|
08918859
|
Filing Dt:
|
08/26/1997
|
|
Title:
|
ELECTROLUMINESCENT LAMP DRIVER CIRCUIT WITH SIGNAL TRACKING
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/08/1998
|
Application #:
|
08926833
|
Filing Dt:
|
09/10/1997
|
|
Title:
|
MEMORY-ROW SELECTOR HAVING A TEST FUNCTION
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|
Patent #:
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|
Issue Dt:
|
10/27/1998
|
Application #:
|
08944649
|
Filing Dt:
|
10/06/1997
|
|
Title:
|
CLOCKED SENSE AMPLIFIER WITH WORDLINE TRACKING
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Patent #:
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|
Issue Dt:
|
02/02/1999
|
Application #:
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08957088
|
Filing Dt:
|
10/24/1997
|
|
Title:
|
CIRCUIT FOR IMPROVING BACK EMF DETECTION IN PULSE WIDTH MODULATION MODE
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Patent #:
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|
Issue Dt:
|
09/28/1999
|
Application #:
|
08966042
|
Filing Dt:
|
11/07/1997
|
|
Title:
|
STRUCTURE FOR DESELECTIVE BROKEN SELECT LINES IN MEMORY ARRAYS
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|
Patent #:
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|
Issue Dt:
|
11/17/1998
|
Application #:
|
08976760
|
Filing Dt:
|
11/24/1997
|
|
Title:
|
ENHANCED PLANARIZATION TECHNIQUE FOR AN INTEGRATED CIRCUIT
|
|
