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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:038378/0442   Pages: 8
Recorded: 04/07/2016
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 74
1
Patent #:
NONE
Issue Dt:
Application #:
10908254
Filing Dt:
05/04/2005
Publication #:
US20050242446
Pub Dt:
11/03/2005
Title:
INTEGRATED CIRCUIT PACKAGE WITH DIFFERENT HARDNESS BUMP PAD AND BUMP AND MANUFACTURING METHOD THEREFOR
2
Patent #:
NONE
Issue Dt:
Application #:
10934835
Filing Dt:
09/02/2004
Publication #:
US20060043612
Pub Dt:
03/02/2006
Title:
Wire sweep resistant semiconductor package and manufacturing method thereof
3
Patent #:
NONE
Issue Dt:
Application #:
11035637
Filing Dt:
01/14/2005
Publication #:
US20060160267
Pub Dt:
07/20/2006
Title:
Under bump metallurgy in integrated circuits
4
Patent #:
NONE
Issue Dt:
Application #:
11162828
Filing Dt:
09/24/2005
Publication #:
US20060103008
Pub Dt:
05/18/2006
Title:
HYPER THERMALLY ENHANCED SEMICONDUCTOR PACKAGE SYSTEM
5
Patent #:
NONE
Issue Dt:
Application #:
11162971
Filing Dt:
09/29/2005
Publication #:
US20070071583
Pub Dt:
03/29/2007
Title:
SUBSTRATE INDEXING SYSTEM
6
Patent #:
NONE
Issue Dt:
Application #:
11163313
Filing Dt:
10/13/2005
Publication #:
US20070085184
Pub Dt:
04/19/2007
Title:
STACKED DIE PACKAGING SYSTEM
7
Patent #:
NONE
Issue Dt:
Application #:
11163547
Filing Dt:
10/21/2005
Publication #:
US20070093000
Pub Dt:
04/26/2007
Title:
PRE-MOLDED LEADFRAME AND METHOD THEREFOR
8
Patent #:
NONE
Issue Dt:
Application #:
11163556
Filing Dt:
10/22/2005
Publication #:
US20060175688
Pub Dt:
08/10/2006
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED INTERLOCKING LEADFRAME
9
Patent #:
7626277
Issue Dt:
12/01/2009
Application #:
11164329
Filing Dt:
11/18/2005
Publication #:
US20060055009
Pub Dt:
03/16/2006
Title:
INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE
10
Patent #:
NONE
Issue Dt:
Application #:
11276947
Filing Dt:
03/17/2006
Publication #:
US20070108635
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
11
Patent #:
NONE
Issue Dt:
Application #:
11278002
Filing Dt:
03/30/2006
Publication #:
US20070235878
Pub Dt:
10/11/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH POST-PASSIVATION INTERCONNECTION AND INTEGRATION
12
Patent #:
NONE
Issue Dt:
Application #:
11279741
Filing Dt:
04/13/2006
Publication #:
US20070111376
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
13
Patent #:
NONE
Issue Dt:
Application #:
11307317
Filing Dt:
01/31/2006
Publication #:
US20070178666
Pub Dt:
08/02/2007
Title:
INTEGRATED CIRCUIT SYSTEM WITH WAFERSCALE SPACER SYSTEM
14
Patent #:
NONE
Issue Dt:
Application #:
11307349
Filing Dt:
02/01/2006
Publication #:
US20070176271
Pub Dt:
08/02/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING DIE-ATTACH PAD WITH ELEVATED BONDLINE THICKNESS
15
Patent #:
NONE
Issue Dt:
Application #:
11307498
Filing Dt:
02/09/2006
Publication #:
US20070109756
Pub Dt:
05/17/2007
Title:
STACKED INTEGRATED CIRCUITS PACKAGE SYSTEM
16
Patent #:
7420269
Issue Dt:
09/02/2008
Application #:
11379097
Filing Dt:
04/18/2006
Publication #:
US20070241442
Pub Dt:
10/18/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
17
Patent #:
7339258
Issue Dt:
03/04/2008
Application #:
11379740
Filing Dt:
04/21/2006
Publication #:
US20060186515
Pub Dt:
08/24/2006
Title:
DUAL ROW LEADFRAME AND FABRICATION METHOD
18
Patent #:
NONE
Issue Dt:
Application #:
11380587
Filing Dt:
04/27/2006
Publication #:
US20070109750
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
19
Patent #:
NONE
Issue Dt:
Application #:
11383802
Filing Dt:
05/17/2006
Publication #:
US20070268660
Pub Dt:
11/22/2007
Title:
SPACERLESS SEMICONDUCTOR PACKAGE CHIP STACKING SYSTEM
20
Patent #:
NONE
Issue Dt:
Application #:
11388755
Filing Dt:
03/24/2006
Publication #:
US20060216860
Pub Dt:
09/28/2006
Title:
Flip chip interconnection having narrow interconnection sites on the substrate
21
Patent #:
NONE
Issue Dt:
Application #:
11397018
Filing Dt:
04/03/2006
Publication #:
US20070024197
Pub Dt:
02/01/2007
Title:
Plasma display panel device with fluorescent layer protector
22
Patent #:
9129826
Issue Dt:
09/08/2015
Application #:
11420853
Filing Dt:
05/30/2006
Publication #:
US20060267609
Pub Dt:
11/30/2006
Title:
Epoxy Bump for Overhang Die
23
Patent #:
NONE
Issue Dt:
Application #:
11435555
Filing Dt:
05/16/2006
Publication #:
US20060255473
Pub Dt:
11/16/2006
Title:
Flip chip interconnect solder mask
24
Patent #:
NONE
Issue Dt:
Application #:
11458065
Filing Dt:
07/17/2006
Publication #:
US20070108583
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
25
Patent #:
NONE
Issue Dt:
Application #:
11469307
Filing Dt:
08/31/2006
Publication #:
US20070001296
Pub Dt:
01/04/2007
Title:
BUMP FOR OVERHANG DEVICE
26
Patent #:
NONE
Issue Dt:
Application #:
11532508
Filing Dt:
09/15/2006
Publication #:
US20080067639
Pub Dt:
03/20/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
27
Patent #:
7700404
Issue Dt:
04/20/2010
Application #:
11536544
Filing Dt:
09/28/2006
Publication #:
US20070018290
Pub Dt:
01/25/2007
Title:
LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR
28
Patent #:
NONE
Issue Dt:
Application #:
11672910
Filing Dt:
02/08/2007
Publication #:
US20080191367
Pub Dt:
08/14/2008
Title:
SEMICONDUCTOR PACKAGE WIRE BONDING
29
Patent #:
NONE
Issue Dt:
Application #:
11749712
Filing Dt:
05/16/2007
Publication #:
US20080284038
Pub Dt:
11/20/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PERIMETER PADDLE
30
Patent #:
NONE
Issue Dt:
Application #:
11767820
Filing Dt:
06/25/2007
Publication #:
US20080315406
Pub Dt:
12/25/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CAVITY SUBSTRATE
31
Patent #:
7692279
Issue Dt:
04/06/2010
Application #:
11772776
Filing Dt:
07/02/2007
Publication #:
US20070278658
Pub Dt:
12/06/2007
Title:
SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING DIE AND INVERTED LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
32
Patent #:
9330945
Issue Dt:
05/03/2016
Application #:
11857188
Filing Dt:
09/18/2007
Publication #:
US20090072375
Pub Dt:
03/19/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTI-CHIP MODULE
33
Patent #:
10074553
Issue Dt:
09/11/2018
Application #:
11949282
Filing Dt:
12/03/2007
Publication #:
US20090140442
Pub Dt:
06/04/2009
Title:
Wafer Level Package Integration and Method
34
Patent #:
NONE
Issue Dt:
Application #:
11964397
Filing Dt:
12/26/2007
Publication #:
US20090170241
Pub Dt:
07/02/2009
Title:
Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
35
Patent #:
9466577
Issue Dt:
10/11/2016
Application #:
12035843
Filing Dt:
02/22/2008
Publication #:
US20090212441
Pub Dt:
08/27/2009
Title:
Semiconductor Interconnect Structure with Stacked Vias Separated by Signal Line and Method Therefor
36
Patent #:
NONE
Issue Dt:
Application #:
12046761
Filing Dt:
03/12/2008
Publication #:
US20090233436
Pub Dt:
09/17/2009
Title:
Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP Coating
37
Patent #:
NONE
Issue Dt:
Application #:
12055612
Filing Dt:
03/26/2008
Publication #:
US20090243069
Pub Dt:
10/01/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION
38
Patent #:
9236319
Issue Dt:
01/12/2016
Application #:
12056402
Filing Dt:
03/27/2008
Publication #:
US20090243072
Pub Dt:
10/01/2009
Title:
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
39
Patent #:
NONE
Issue Dt:
Application #:
12062403
Filing Dt:
04/03/2008
Publication #:
US20090250814
Pub Dt:
10/08/2009
Title:
Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof
40
Patent #:
NONE
Issue Dt:
Application #:
12122639
Filing Dt:
05/16/2008
Publication #:
US20090283889
Pub Dt:
11/19/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
41
Patent #:
9123663
Issue Dt:
09/01/2015
Application #:
12136682
Filing Dt:
06/10/2008
Publication #:
US20090302436
Pub Dt:
12/10/2009
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER GROUNDED THROUGH METAL PILLARS FORMED IN PERIPHERAL REGION OF THE SEMICONDUCTOR
42
Patent #:
9293385
Issue Dt:
03/22/2016
Application #:
12182132
Filing Dt:
07/30/2008
Publication #:
US20100025833
Pub Dt:
02/04/2010
Title:
RDL PATTERNING WITH PACKAGE ON PACKAGE SYSTEM
43
Patent #:
7691681
Issue Dt:
04/06/2010
Application #:
12191542
Filing Dt:
08/14/2008
Publication #:
US20080299705
Pub Dt:
12/04/2008
Title:
CHIP SCALE PACKAGE HAVING FLIP CHIP INTERCONNECT ON DIE PADDLE
44
Patent #:
9324700
Issue Dt:
04/26/2016
Application #:
12205727
Filing Dt:
09/05/2008
Publication #:
US20100059853
Pub Dt:
03/11/2010
Title:
Semiconductor Device and Method of Forming Shielding Layer over Integrated Passive Device Using Conductive Channels
45
Patent #:
8263437
Issue Dt:
09/11/2012
Application #:
12205755
Filing Dt:
09/05/2008
Publication #:
US20100059854
Pub Dt:
03/11/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN IPD OVER A HIGH-RESISTIVITY ENCAPSULANT SEPARATED FROM OTHER IPDS AND BASEBAND CIRCUIT
46
Patent #:
9559046
Issue Dt:
01/31/2017
Application #:
12209838
Filing Dt:
09/12/2008
Publication #:
US20100065948
Pub Dt:
03/18/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A FAN-IN PACKAGE-ON-PACKAGE STRUCTURE USING THROUGH-SILICON VIAS
47
Patent #:
9293350
Issue Dt:
03/22/2016
Application #:
12260089
Filing Dt:
10/28/2008
Publication #:
US20100102458
Pub Dt:
04/29/2010
Title:
SEMICONDUCTOR PACKAGE SYSTEM WITH CAVITY SUBSTRATE AND MANUFACTURING METHOD THEREFOR
48
Patent #:
9257356
Issue Dt:
02/09/2016
Application #:
12332253
Filing Dt:
12/10/2008
Publication #:
US20100140780
Pub Dt:
06/10/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN IPD BENEATH A SEMICONDUCTOR DIE WITH DIRECT CONNECTION TO EXTERNAL DEVICES
49
Patent #:
NONE
Issue Dt:
Application #:
12407949
Filing Dt:
03/20/2009
Publication #:
US20100237500
Pub Dt:
09/23/2010
Title:
Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site
50
Patent #:
NONE
Issue Dt:
Application #:
12408641
Filing Dt:
03/20/2009
Publication #:
US20100237481
Pub Dt:
09/23/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF
51
Patent #:
NONE
Issue Dt:
Application #:
12412886
Filing Dt:
03/27/2009
Publication #:
US20100244212
Pub Dt:
09/30/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POST TYPE INTERCONNECTOR AND METHOD OF MANUFACTURE THEREOF
52
Patent #:
9355962
Issue Dt:
05/31/2016
Application #:
12483548
Filing Dt:
06/12/2009
Publication #:
US20100314741
Pub Dt:
12/16/2010
Title:
INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH REDISTRIBUTION AND METHOD OF MANUFACTURE THEREOF
53
Patent #:
NONE
Issue Dt:
Application #:
12493049
Filing Dt:
06/26/2009
Publication #:
US20100327406
Pub Dt:
12/30/2010
Title:
Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In Substrate
54
Patent #:
9230898
Issue Dt:
01/05/2016
Application #:
12542097
Filing Dt:
08/17/2009
Publication #:
US20110037157
Pub Dt:
02/17/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
55
Patent #:
NONE
Issue Dt:
Application #:
12563368
Filing Dt:
09/21/2009
Publication #:
US20100244223
Pub Dt:
09/30/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STRUCTURE AND METHOD OF MANUFACTURE THEREOF
56
Patent #:
9343429
Issue Dt:
05/17/2016
Application #:
12683008
Filing Dt:
01/06/2010
Publication #:
US20100102456
Pub Dt:
04/29/2010
Title:
Semiconductor Device and Method of Forming Double-Sided Through Vias in Saw Streets
57
Patent #:
NONE
Issue Dt:
Application #:
12688124
Filing Dt:
01/15/2010
Publication #:
US20100117230
Pub Dt:
05/13/2010
Title:
Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof
58
Patent #:
9299648
Issue Dt:
03/29/2016
Application #:
12714291
Filing Dt:
02/26/2010
Publication #:
US20100224974
Pub Dt:
09/09/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PATTERNED SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
59
Patent #:
9847253
Issue Dt:
12/19/2017
Application #:
12757750
Filing Dt:
04/09/2010
Publication #:
US20120199963
Pub Dt:
08/09/2012
Title:
PACKAGE-ON-PACKAGE USING THROUGH-HOLE VIA DIE ON SAW STREETS
60
Patent #:
NONE
Issue Dt:
Application #:
12763378
Filing Dt:
04/20/2010
Publication #:
US20120211881
Pub Dt:
08/23/2012
Title:
Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process
61
Patent #:
NONE
Issue Dt:
Application #:
12777615
Filing Dt:
05/11/2010
Publication #:
US20100289142
Pub Dt:
11/18/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COIN BONDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
62
Patent #:
9125332
Issue Dt:
09/01/2015
Application #:
12813335
Filing Dt:
06/10/2010
Publication #:
US20100244245
Pub Dt:
09/30/2010
Title:
Filp Chip Interconnection Structure with Bump on Partial Pad and Method Thereof
63
Patent #:
NONE
Issue Dt:
Application #:
12819162
Filing Dt:
06/18/2010
Publication #:
US20110309481
Pub Dt:
12/22/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIP CHIP MOUNTING AND METHOD OF MANUFACTURE THEREOF
64
Patent #:
NONE
Issue Dt:
Application #:
13038384
Filing Dt:
03/01/2011
Publication #:
US20120223435
Pub Dt:
09/06/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
65
Patent #:
NONE
Issue Dt:
Application #:
13039309
Filing Dt:
03/02/2011
Publication #:
US20120224332
Pub Dt:
09/06/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMP BONDED DIES AND METHOD OF MANUFACTURE THEREOF
66
Patent #:
9184103
Issue Dt:
11/10/2015
Application #:
13048771
Filing Dt:
03/15/2011
Publication #:
US20110163414
Pub Dt:
07/07/2011
Title:
Semiconductor Device Having Embedded Integrated Passive Devices Electrically Interconnected Using Conductive Pillars
67
Patent #:
NONE
Issue Dt:
Application #:
13209837
Filing Dt:
08/15/2011
Publication #:
US20110298113
Pub Dt:
12/08/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INCREASED CONNECTIVITY AND METHOD OF MANUFACTURE THEREOF
68
Patent #:
9318403
Issue Dt:
04/19/2016
Application #:
13211303
Filing Dt:
08/16/2011
Publication #:
US20110298106
Pub Dt:
12/08/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MAGNETIC FILM AND METHOD OF MANUFACTURE THEREOF
69
Patent #:
NONE
Issue Dt:
Application #:
14341578
Filing Dt:
07/25/2014
Publication #:
US20140335655
Pub Dt:
11/13/2014
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING STRUCTURE
70
Patent #:
NONE
Issue Dt:
Application #:
14565731
Filing Dt:
12/10/2014
Publication #:
US20150137322
Pub Dt:
05/21/2015
Title:
Semiconductor Device and Method of Forming WLCSP Using Wafer Sections Containing Multiple Die
71
Patent #:
9401347
Issue Dt:
07/26/2016
Application #:
14600825
Filing Dt:
01/20/2015
Publication #:
US20150137334
Pub Dt:
05/21/2015
Title:
Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die Disposed in a Cavity of an Interconnect Structure and Grounded Through the Die TSV
72
Patent #:
9824975
Issue Dt:
11/21/2017
Application #:
14612075
Filing Dt:
02/02/2015
Publication #:
US20150145128
Pub Dt:
05/28/2015
Title:
Semiconductor Device and Method of Forming Stepped Interconnect Layer for Stacked Semiconductor Die
73
Patent #:
10083916
Issue Dt:
09/25/2018
Application #:
14637054
Filing Dt:
03/03/2015
Publication #:
US20150179587
Pub Dt:
06/25/2015
Title:
Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure
74
Patent #:
9379084
Issue Dt:
06/28/2016
Application #:
14682914
Filing Dt:
04/09/2015
Publication #:
US20150214182
Pub Dt:
07/30/2015
Title:
Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask
Assignor
1
STATS CHIPPAC LD.
Exec Dt:
03/29/2016
Assignee
1
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 23
SINGAPORE, SINGAPORE
Correspondence name and address
EDWARD J. MAYLE
18590 K STREET, N.W.
WASHINGTON, DC 20006

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