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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09561473
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Filing Dt:
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04/27/2000
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Title:
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Circuit for suppressing a common mode component in a signal from a can communication bus
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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09571191
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Filing Dt:
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05/16/2000
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Title:
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SHARED BUS INTERFACE FOR DIGITAL SIGNAL PROCESSOR
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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09593448
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Filing Dt:
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06/13/2000
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Title:
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MULTI-CHANNEL AND MULTI-MODAL DIRECT MEMORY ACCESS CONTROLLER FOR OPTIMIZING PERFORMANCE OF HOST BUS
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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09606337
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Filing Dt:
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06/29/2000
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Title:
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DATABUS TRANSMITTER
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09624640
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Filing Dt:
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07/25/2000
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Title:
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BIDIRECTIONAL INTERFACE
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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09629672
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Filing Dt:
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08/01/2000
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Title:
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CAN MICROCONTROLLER THAT PERMITS CONCURRENT ACCESS TO DIFFERENT SEGMENTS OF A COMMON MEMORY BY BOTH THE PROCESSOR CORE AND THE DMA ENGINE THEREOF
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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09630288
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Filing Dt:
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08/01/2000
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Title:
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END-OF-MESSAGE HANDLING AND INTERRUPT GENERATION IN A CAN MODULE PROVIDING HARDWARE ASSEMBLY OF MULTI-FRAME CAN MESSAGES
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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09630289
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Filing Dt:
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08/01/2000
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Title:
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MESSAGE BUFFER FULL HANDLING IN A CAN DEVICE THAT EMPLOYS RECONFIGURABLE MESSAGE BUFFERS
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09630290
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Filing Dt:
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08/01/2000
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Title:
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USE OF BUFFER-SIZE MASK IN CONJUNCTION WITH ADDRESS POINTER TO DETECT BUFFER-FULL AND BUFFER-ROLLOVER CONDITIONS IN A CAN DEVICE THAT EMPLOYS RECONFIGURABLE MESSAGE BUFFERS
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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09630360
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Filing Dt:
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08/01/2000
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Title:
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CAN MICROCONTROLLER THAT EMPLOYS RECONFIGURABLE MESSAGE BUFFERS
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09630642
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Filing Dt:
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08/01/2000
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Title:
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TRANSMIT PRE-ARBITRATION SCHEME FOR A CAN DEVICE AND A CAN DIVICE THAT IMPLEMENTS THIS SCHEME
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09630665
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Filing Dt:
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08/01/2000
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Title:
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CAN MICROCONTROLLER THAT UTILIZES A DEDICATED RAM MEMORY SPACE TO STORE MESSAGE-OBJECT CONFIGURATION INFORMATION
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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09630666
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Filing Dt:
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08/01/2000
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Title:
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CAN DEVICE FEATURING ADVANCED CAN FILTERING AND MESSAGE ACCEPTANCE
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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09640732
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Filing Dt:
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08/17/2000
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Title:
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ARRANGEMENT WITH A PLURALITY OF PROCESSORS SHARING A COLLECTIVE MEMORY
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09641177
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Filing Dt:
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08/17/2000
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Title:
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MULTIPLE PORT I2C HUB
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09641179
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Filing Dt:
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08/17/2000
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Title:
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Bidirectional repeater using high and low threshold detection
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09660915
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Filing Dt:
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09/13/2000
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Title:
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NETWORK FOR DATA AND ENERGY TRANSFER
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Patent #:
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Issue Dt:
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08/29/2006
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Application #:
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09663594
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Filing Dt:
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09/18/2000
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Title:
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NETWORK COMPRISING A PLURALITY OF NETWORK NODES AND AT LEAST ONE STAR NODE
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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09733747
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Filing Dt:
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12/08/2000
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Publication #:
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Pub Dt:
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06/13/2002
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Title:
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OUTPUT DRIVER CIRCUIT WITH CURRENT DETECTION
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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09745856
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Filing Dt:
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12/22/2000
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Publication #:
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Pub Dt:
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08/30/2001
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Title:
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EMULATION OF A DISCONNECT OF A DEVICE
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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09778653
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Filing Dt:
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02/07/2001
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Title:
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ACCELERATED GRAPHICS PORT (APG) CONTROLLER SUPPORTING FAST WRITE TRANSACTIONS
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Patent #:
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Issue Dt:
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08/12/2003
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Application #:
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09850740
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Filing Dt:
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07/02/2001
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Title:
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CUTTING FLUID COMPOSITION
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Patent #:
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Issue Dt:
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02/07/2006
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Application #:
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09868376
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Filing Dt:
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06/18/2001
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Title:
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NETWORK COMPRISING A PLURALITY OF NETWORK NODES FOR MEDIA ACCESS CHECKS
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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09870917
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Filing Dt:
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05/31/2001
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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AUTOMATIC UPGRADEABLE UART CIRCUIT ARRANGEMENT
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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09871117
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Filing Dt:
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05/31/2001
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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PARALLEL DATA COMMUNICATION HAVING MULTIPLE SYNC CODES
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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09871160
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Filing Dt:
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05/31/2001
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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PARALLEL DATA COMMUNICATION CONSUMING LOW POWER
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09871197
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Filing Dt:
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05/31/2001
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Publication #:
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Pub Dt:
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05/08/2003
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Title:
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PARALLEL COMMUNICATION BASED ON BALANCED DATA-BIT ENCODING
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Patent #:
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Issue Dt:
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11/30/2004
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Application #:
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09888458
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Filing Dt:
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06/25/2001
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Publication #:
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Pub Dt:
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04/04/2002
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Title:
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MICROCONTROLLER WITH MEMORY CONTENT DEPENDENT CONDITIONAL COMMAND DECODER FOR ACCESSING DIFFERENT MEMORY TYPES
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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09891428
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Filing Dt:
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06/26/2001
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Publication #:
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Pub Dt:
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01/31/2002
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Title:
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INTEGRATED CIRCUIT WITH FLASH MEMORY
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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09895921
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Filing Dt:
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06/29/2001
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Title:
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GENERALIZED I2C SLAVE TRANSMITTER/RECEIVER STATE MACHINE
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Patent #:
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Issue Dt:
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01/31/2006
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Application #:
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09912134
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Filing Dt:
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07/24/2001
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Publication #:
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Pub Dt:
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05/09/2002
| | | | |
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Title:
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STATION AND METHOD FOR OPERATING A CAN COMMUNICATION LINE
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09922420
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Filing Dt:
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08/02/2001
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Publication #:
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Pub Dt:
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02/06/2003
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Title:
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UNIVERSAL PECL/LVDS OUTPUT STRUCTURE
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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09923609
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Filing Dt:
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08/07/2001
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Publication #:
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Pub Dt:
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04/25/2002
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Title:
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ACTIVITY DETECTION IN A STAR NODE WITH A PLURALITY OF COUPLED NETWORK NODES
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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09966297
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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PARALLEL DATA COMMUNICATION REALIGNMENT OF DATA SENT IN MULTIPLE GROUPS
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Patent #:
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Issue Dt:
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02/07/2006
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Application #:
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09997609
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Filing Dt:
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11/29/2001
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Publication #:
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Pub Dt:
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05/29/2003
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Title:
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HIGH-SPEED INTERCHIP INTERFACE PROTOCOL
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Patent #:
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Issue Dt:
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02/10/2004
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Application #:
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09998052
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Filing Dt:
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11/29/2001
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Publication #:
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Pub Dt:
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07/04/2002
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Title:
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CIRCUIT ARRANGEMENT FOR ERROR RECOGNITION OF A TWO-WIRE DATA BUS
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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10016731
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Filing Dt:
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12/11/2001
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Publication #:
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Pub Dt:
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10/30/2003
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Title:
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METHOD AND ARRANGEMENT FOR RAPID SILICON PROTOTYPING
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Patent #:
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Issue Dt:
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02/15/2005
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Application #:
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10022380
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Filing Dt:
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11/30/2001
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Publication #:
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Pub Dt:
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10/31/2002
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Title:
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EXTENSION FOR THE ADVANCED MICROCONTROLLER BUS ARCHITECTURE (AMBA)
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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10022381
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Filing Dt:
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10/30/2001
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Publication #:
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Pub Dt:
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08/08/2002
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Title:
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LINE DRIVER FOR SUPPLYING SYMMETRICAL OUTPUT SIGNALS TO A TWO-WIRE COMMUNICATION BUS
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Patent #:
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Issue Dt:
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02/18/2003
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Application #:
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10027672
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Filing Dt:
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12/19/2001
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Publication #:
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Pub Dt:
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05/09/2002
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Title:
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BIDIRECTIONAL REPEATER USING HIGH AND LOW THRESHOLD DETECTION
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Patent #:
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Issue Dt:
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05/16/2006
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Application #:
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10055387
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01/23/2002
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07/25/2002
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Title:
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TRANSCEIVER WITH MEANS FOR ERROR MANAGEMENT
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Patent #:
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Issue Dt:
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09/27/2005
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Application #:
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10095348
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Filing Dt:
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03/11/2002
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Publication #:
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Pub Dt:
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10/24/2002
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Title:
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LINE DRIVER WITH CURRENT SOURCE OUTPUT AND HIGH IMMUNITY TO RF SIGNALS
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07/06/2004
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Application #:
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10100357
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03/14/2002
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Publication #:
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Pub Dt:
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09/18/2003
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Title:
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I/O CIRCUIT WITH MIXED SUPPLY VOLTAGE CAPABILITY
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Patent #:
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Issue Dt:
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05/31/2005
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Application #:
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10120682
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Filing Dt:
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04/11/2002
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Publication #:
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Pub Dt:
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11/07/2002
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Title:
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DEVICE FOR PROCESSING DATA BY MEANS OF A PLURALITY OF PROCESSORS
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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10125963
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Filing Dt:
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04/18/2002
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Publication #:
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Pub Dt:
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10/23/2003
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Title:
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DIFFERENTIAL OUTPUT STRUCTURE WITH REDUCED SKEW FOR A SINGLE INPUT
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Issue Dt:
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10/28/2003
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10176209
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06/20/2002
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10/24/2002
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Title:
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CLOCK SYSTEM FOR MULTIPLE COMPONENT SYSTEM
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Patent #:
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Issue Dt:
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06/22/2010
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10183716
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06/27/2002
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01/01/2004
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Title:
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SECURITY PROCESSOR WITH BUS CONFIGURATION
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06/09/2009
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10221718
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09/13/2002
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01/22/2004
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Title:
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BUS SYSTEM WITH LINE CONTROL DURING THE LOW-POWER PHASE
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05/16/2006
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10224992
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08/21/2002
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02/26/2004
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Title:
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ENTROPY ESTIMATION AND DECIMATION FOR IMPROVING THE RANDOMNESS OF TRUE RANDOM NUMBER GENERATION
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12/16/2008
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10227363
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08/23/2002
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02/26/2004
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Title:
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EMBEDDED DATA SET PROCESSING
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09/01/2009
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10236179
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09/06/2002
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04/10/2003
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COMMUNICATIONS NETWORK AND METHOD OF CONTROLLING THE COMMUNICATION NETWORK
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05/09/2006
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10253260
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09/24/2002
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05/29/2003
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BUS SYSTEM AND BUS INTERFACE
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03/09/2010
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10480130
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12/09/2003
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11/25/2004
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Title:
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DISTRIBUTION OF STATUS INFORMATION FROM SEVERAL VIRTUAL OUTPUT QUEUS OVER A PLURALITY OF SWITCH CARDS OF A PACKET SWITCHING DEVICE
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10/18/2005
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10496481
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05/24/2004
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02/24/2005
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Title:
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OUTPUT DRIVER COMPRISING AN IMPROVED CONTROL CIRCUIT
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06/06/2006
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10498304
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06/09/2004
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01/20/2005
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Title:
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WIRELESS PERIPHERAL INTERFACE WITH UNIVERSAL SERIAL BUS PORT
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09/09/2008
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10499401
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06/17/2004
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Publication #:
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Pub Dt:
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02/03/2005
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Title:
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COMMUNICATION BUS SYSTEM OPERABLE IN A SLEEP MODE AND A NORMAL MODE
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Patent #:
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Issue Dt:
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03/23/2010
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10514850
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07/19/2005
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07/13/2006
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Title:
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METHOD FOR EFFECTING THE CONTROLLED SHUTDOWN OF DATA PROCESSING UNITS
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06/03/2008
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10517513
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12/09/2004
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09/29/2005
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Title:
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BUS SYSTEM, STATION FOR USE IN A BUS SYSTEM, AND BUS INTERFACE
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04/03/2007
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10520198
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07/20/2005
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03/23/2006
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Title:
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ELECTRONIC CIRCUIT WITH TEST UNIT
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Issue Dt:
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08/18/2009
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10525488
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02/23/2005
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Pub Dt:
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06/08/2006
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Title:
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METHOD FOR REDUCING POWER CONSUMPTION IN A STATE RETAINING CIRCUIT, STATE RETAINING CIRCUIT AND ELECTRONIC DEVICE
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Issue Dt:
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07/06/2010
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10528474
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Filing Dt:
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03/21/2005
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11/10/2005
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Title:
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INTERFACE INTEGRATED CIRCUIT DEVICE FOR A USB CONNECTION
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08/21/2007
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10535554
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Filing Dt:
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05/18/2005
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Publication #:
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Pub Dt:
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12/29/2005
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Title:
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INTEGRATED FLOATING POWER TRANSFER DEVICE WITH LOGIC LEVEL CONTROL AND METHOD
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Issue Dt:
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08/31/2010
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10538458
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Filing Dt:
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06/10/2005
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Publication #:
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Pub Dt:
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06/08/2006
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Title:
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ENCAPSULATED HARDWARE CONFIGURATION/CONTROL
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Patent #:
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Issue Dt:
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03/17/2009
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10545050
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08/10/2005
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07/06/2006
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Title:
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ARRANGEMENT FOR COMPENSATION OF GROUND OFFSET IN A DATA BUS SYSTEM
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11/17/2009
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10545051
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08/10/2005
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06/22/2006
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Title:
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METHOD OF MONITORING THE COMMUNICATION IN A NETWORK
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Patent #:
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Issue Dt:
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05/29/2007
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10556250
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11/10/2005
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Publication #:
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01/25/2007
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Title:
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LINE DRIVER WITH REDUCED INTERFERENCE
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01/13/2009
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10557679
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11/22/2005
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Pub Dt:
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04/05/2007
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Title:
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SIGNAL INTEGRITY SELF-TEST ARCHITECTURE
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Patent #:
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Issue Dt:
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05/26/2009
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10561627
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Filing Dt:
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12/19/2005
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Publication #:
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Pub Dt:
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07/27/2006
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Title:
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REGISTER FILE GATING TO REDUCE MICROPROCESSOR POWER DISSIPATION
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Patent #:
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Issue Dt:
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05/05/2009
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Application #:
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10569185
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02/22/2006
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01/04/2007
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Title:
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CIRCUIT ARRANGEMENT AND METHOD FOR SUPPORTING AND MONITORING A MICROCONTROLLER
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Issue Dt:
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09/15/2009
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10588889
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08/09/2006
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06/14/2007
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Title:
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DIGITAL SIGNAL PROCESSING INTEGRATED CIRCUIT WITH IO CONNECTIONS
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06/30/2009
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10590388
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08/16/2007
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10/23/2008
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09/06/2011
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10592190
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10/24/2008
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Pub Dt:
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02/12/2009
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Title:
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COMMUNICATIONS DEVICE AND METHOD FOR CONFIGURING A COMMUNICATION PORT DEPENDING ON A DIRECTION CONDITION OF A REMOTE DEVICE COMMUNICATIVELY COUPLED TO THE COMMUNICATIONS PORT
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Issue Dt:
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07/19/2011
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10592191
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01/18/2008
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Pub Dt:
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10/16/2008
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Title:
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SIMULATION CIRCUIT OF PCI EXPRESS ENDPOINT AND DOWNSTREAM PORT FOR A PCI EXPRESS SWITCH
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Patent #:
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Issue Dt:
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10/19/2004
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10621002
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Filing Dt:
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07/16/2003
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03/25/2004
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Title:
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CIRCUIT WITH INTERCONNECT TEST UNIT
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01/23/2007
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10678625
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10/03/2003
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04/21/2005
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Title:
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DATA PROCESSING SYSTEM AND METHOD
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Issue Dt:
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12/28/2004
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10678937
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10/03/2003
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Pub Dt:
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04/08/2004
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Title:
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DIFFERENTIAL OUTPUT STRUCTURE WITH REDUCED SKEW FOR A SINGLE INPUT
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Patent #:
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Issue Dt:
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10/28/2008
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10797790
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03/10/2004
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Pub Dt:
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09/02/2004
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Title:
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CAN DEVICE FEATURING ADVANCED CAN FILTERING AND MESSAGE ACCEPTANCE
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02/17/2009
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10850327
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05/19/2004
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Title:
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USB HOST PROTOCOL
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Patent #:
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Issue Dt:
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03/03/2009
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Application #:
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10919756
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Filing Dt:
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08/17/2004
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Pub Dt:
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03/24/2005
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Title:
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EMULATION OF A DISCONNECT OF A DEVICE
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Patent #:
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Issue Dt:
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04/19/2011
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11576142
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03/27/2007
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08/13/2009
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Title:
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INTEGRATED CIRCUIT WITH INPUT AND/OR OUTPUT BOLTON PADS WITH INTEGRATED LOGIC
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12/13/2011
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11576345
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05/30/2008
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10/30/2008
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Title:
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TWO-PHASE DATA-TRANSFER PROTOCOL
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06/28/2011
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11577179
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10/03/2007
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02/28/2008
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Title:
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SWITCH DEVICE AND COMMUNICATION NETWORK COMPRISING SUCH SWITCH DEVICE AS WELL AS METHOD FOR TRANSMITING DATA WITHIN AT LEAST ONE VIRTUAL CHANNEL
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07/13/2010
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11577704
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04/16/2008
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11/06/2008
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Title:
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SLAVE BUS SUBSCRIBER FOR A SERIAL DATA BUS
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01/27/2009
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11628129
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11/28/2006
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10/18/2007
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Title:
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BUS CONNECTION DEVICE
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05/12/2009
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11632031
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02/06/2008
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10/30/2008
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Title:
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RECEIVER FOR A DIFFERENTIAL DATA BUS
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03/29/2011
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11719532
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05/16/2007
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06/04/2009
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Title:
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PERFORMANCE BASED PACKET ORDERING IN A PCI EXPRESS BUS
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06/08/2010
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11816710
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09/18/2008
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03/12/2009
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Title:
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EDGE RATE CONTROL FOR I2C BUS APPLICATIONS
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06/14/2011
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11817323
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10/24/2008
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08/27/2009
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Title:
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ROUTER, NETWORK COMPRISING A ROUTER, METHOD FOR ROUTING DATA IN A NETWORK
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11/23/2010
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11817706
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05/21/2008
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10/23/2008
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Title:
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10/20/2009
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11913057
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10/29/2007
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08/07/2008
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Title:
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12C SLAVE DEVICE WITH PROGRAMMABLE WRITE-TRANSACTION CYCLES
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07/20/2010
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11913061
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10/29/2007
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09/04/2008
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SLAVE DEVICE WITH LATCHED REQUEST FOR SERVICE
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06/29/2010
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11913063
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10/29/2007
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09/04/2008
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Title:
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SIMULTANEOUS CONTROL OF MULTIPLE I/O BANKS IN AN 12C SLAVE DEVICE
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08/10/2010
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11913064
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10/30/2007
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08/21/2008
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Title:
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DEVICE IDENTIFICATION CODING OF INTER-INTEGRATED CIRCUIT SLAVE DEVICES
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05/04/2010
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11913065
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10/29/2007
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08/14/2008
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Title:
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PROGRAMMING PARALLEL I2C SLAVE DEVICES FROM A SINGLE I2C DATA STREAM
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07/14/2009
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11913067
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10/29/2007
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Pub Dt:
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08/14/2008
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Title:
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I2C SLAVE/MASTER INTERFACE ENHANCEMENT USING STATE MACHINES
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08/31/2010
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11913069
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10/29/2007
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06/19/2008
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Title:
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DYNAMIC 12C SLAVE DEVICE ADDRESS DECODER
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Issue Dt:
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05/10/2011
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11913211
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10/31/2007
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08/28/2008
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Title:
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RECEIVER WITH ADAPTIVE STROBE OFFSET ADJUSTMENT
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Issue Dt:
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10/11/2011
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11917018
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12/10/2007
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Pub Dt:
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08/21/2008
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Title:
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MEMORY CONTROLLER AND METHOD FOR COUPLING A NETWORK AND A MEMORY
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Patent #:
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Issue Dt:
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11/22/2011
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Application #:
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11917020
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Filing Dt:
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09/22/2008
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Pub Dt:
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03/26/2009
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Title:
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MEMORY CONTROLLER AND METHOD FOR COUPLING A NETWORK AND A MEMORY
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Issue Dt:
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02/14/2012
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11917106
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Filing Dt:
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07/14/2010
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Pub Dt:
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01/06/2011
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Title:
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METHOD FOR PARALLEL DATA INTEGRITY CHECKING OF PCI EXPRESS DEVICES
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