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Reel/Frame:039514/0451   Pages: 11
Recorded: 07/26/2016
Attorney Dkt #:70027
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED ON REEL 038378 FRAME 0442. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME.
Total properties: 42
1
Patent #:
NONE
Issue Dt:
Application #:
10908254
Filing Dt:
05/04/2005
Publication #:
Pub Dt:
11/03/2005
Title:
INTEGRATED CIRCUIT PACKAGE WITH DIFFERENT HARDNESS BUMP PAD AND BUMP AND MANUFACTURING METHOD THEREFOR
2
Patent #:
NONE
Issue Dt:
Application #:
10934835
Filing Dt:
09/02/2004
Publication #:
Pub Dt:
03/02/2006
Title:
Wire sweep resistant semiconductor package and manufacturing method thereof
3
Patent #:
NONE
Issue Dt:
Application #:
11035637
Filing Dt:
01/14/2005
Publication #:
Pub Dt:
07/20/2006
Title:
Under bump metallurgy in integrated circuits
4
Patent #:
NONE
Issue Dt:
Application #:
11162828
Filing Dt:
09/24/2005
Publication #:
Pub Dt:
05/18/2006
Title:
HYPER THERMALLY ENHANCED SEMICONDUCTOR PACKAGE SYSTEM
5
Patent #:
NONE
Issue Dt:
Application #:
11162971
Filing Dt:
09/29/2005
Publication #:
Pub Dt:
03/29/2007
Title:
SUBSTRATE INDEXING SYSTEM
6
Patent #:
NONE
Issue Dt:
Application #:
11163313
Filing Dt:
10/13/2005
Publication #:
Pub Dt:
04/19/2007
Title:
STACKED DIE PACKAGING SYSTEM
7
Patent #:
NONE
Issue Dt:
Application #:
11163547
Filing Dt:
10/21/2005
Publication #:
Pub Dt:
04/26/2007
Title:
PRE-MOLDED LEADFRAME AND METHOD THEREFOR
8
Patent #:
NONE
Issue Dt:
Application #:
11276947
Filing Dt:
03/17/2006
Publication #:
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
9
Patent #:
NONE
Issue Dt:
Application #:
11278002
Filing Dt:
03/30/2006
Publication #:
Pub Dt:
10/11/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH POST-PASSIVATION INTERCONNECTION AND INTEGRATION
10
Patent #:
NONE
Issue Dt:
Application #:
11279741
Filing Dt:
04/13/2006
Publication #:
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
11
Patent #:
NONE
Issue Dt:
Application #:
11307317
Filing Dt:
01/31/2006
Publication #:
Pub Dt:
08/02/2007
Title:
INTEGRATED CIRCUIT SYSTEM WITH WAFERSCALE SPACER SYSTEM
12
Patent #:
NONE
Issue Dt:
Application #:
11307349
Filing Dt:
02/01/2006
Publication #:
Pub Dt:
08/02/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING DIE-ATTACH PAD WITH ELEVATED BONDLINE THICKNESS
13
Patent #:
NONE
Issue Dt:
Application #:
11307498
Filing Dt:
02/09/2006
Publication #:
Pub Dt:
05/17/2007
Title:
STACKED INTEGRATED CIRCUITS PACKAGE SYSTEM
14
Patent #:
NONE
Issue Dt:
Application #:
11379018
Filing Dt:
04/17/2006
Publication #:
Pub Dt:
10/18/2007
Title:
MULTICHIP PACKAGE SYSTEM
15
Patent #:
NONE
Issue Dt:
Application #:
11380587
Filing Dt:
04/27/2006
Publication #:
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
16
Patent #:
NONE
Issue Dt:
Application #:
11383802
Filing Dt:
05/17/2006
Publication #:
Pub Dt:
11/22/2007
Title:
SPACERLESS SEMICONDUCTOR PACKAGE CHIP STACKING SYSTEM
17
Patent #:
Issue Dt:
09/08/2015
Application #:
11420853
Filing Dt:
05/30/2006
Publication #:
Pub Dt:
11/30/2006
Title:
Epoxy Bump for Overhang Die
18
Patent #:
NONE
Issue Dt:
Application #:
11458065
Filing Dt:
07/17/2006
Publication #:
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
19
Patent #:
NONE
Issue Dt:
Application #:
11469307
Filing Dt:
08/31/2006
Publication #:
Pub Dt:
01/04/2007
Title:
BUMP FOR OVERHANG DEVICE
20
Patent #:
NONE
Issue Dt:
Application #:
11532508
Filing Dt:
09/15/2006
Publication #:
Pub Dt:
03/20/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
21
Patent #:
NONE
Issue Dt:
Application #:
11672910
Filing Dt:
02/08/2007
Publication #:
Pub Dt:
08/14/2008
Title:
SEMICONDUCTOR PACKAGE WIRE BONDING
22
Patent #:
NONE
Issue Dt:
Application #:
11749712
Filing Dt:
05/16/2007
Publication #:
Pub Dt:
11/20/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PERIMETER PADDLE
23
Patent #:
NONE
Issue Dt:
Application #:
11767820
Filing Dt:
06/25/2007
Publication #:
Pub Dt:
12/25/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CAVITY SUBSTRATE
24
Patent #:
Issue Dt:
05/03/2016
Application #:
11857188
Filing Dt:
09/18/2007
Publication #:
Pub Dt:
03/19/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTI-CHIP MODULE
25
Patent #:
NONE
Issue Dt:
Application #:
12055612
Filing Dt:
03/26/2008
Publication #:
Pub Dt:
10/01/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION
26
Patent #:
Issue Dt:
01/12/2016
Application #:
12056402
Filing Dt:
03/27/2008
Publication #:
Pub Dt:
10/01/2009
Title:
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
27
Patent #:
NONE
Issue Dt:
Application #:
12122639
Filing Dt:
05/16/2008
Publication #:
Pub Dt:
11/19/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
28
Patent #:
Issue Dt:
03/22/2016
Application #:
12182132
Filing Dt:
07/30/2008
Publication #:
Pub Dt:
02/04/2010
Title:
RDL PATTERNING WITH PACKAGE ON PACKAGE SYSTEM
29
Patent #:
Issue Dt:
03/22/2016
Application #:
12260089
Filing Dt:
10/28/2008
Publication #:
Pub Dt:
04/29/2010
Title:
SEMICONDUCTOR PACKAGE SYSTEM WITH CAVITY SUBSTRATE AND MANUFACTURING METHOD THEREFOR
30
Patent #:
NONE
Issue Dt:
Application #:
12408641
Filing Dt:
03/20/2009
Publication #:
Pub Dt:
09/23/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF
31
Patent #:
NONE
Issue Dt:
Application #:
12412886
Filing Dt:
03/27/2009
Publication #:
Pub Dt:
09/30/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POST TYPE INTERCONNECTOR AND METHOD OF MANUFACTURE THEREOF
32
Patent #:
Issue Dt:
05/31/2016
Application #:
12483548
Filing Dt:
06/12/2009
Publication #:
Pub Dt:
12/16/2010
Title:
INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH REDISTRIBUTION AND METHOD OF MANUFACTURE THEREOF
33
Patent #:
Issue Dt:
01/05/2016
Application #:
12542097
Filing Dt:
08/17/2009
Publication #:
Pub Dt:
02/17/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
34
Patent #:
NONE
Issue Dt:
Application #:
12563368
Filing Dt:
09/21/2009
Publication #:
Pub Dt:
09/30/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STRUCTURE AND METHOD OF MANUFACTURE THEREOF
35
Patent #:
Issue Dt:
03/29/2016
Application #:
12714291
Filing Dt:
02/26/2010
Publication #:
Pub Dt:
09/09/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PATTERNED SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
36
Patent #:
NONE
Issue Dt:
Application #:
12777615
Filing Dt:
05/11/2010
Publication #:
Pub Dt:
11/18/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COIN BONDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
37
Patent #:
NONE
Issue Dt:
Application #:
12819162
Filing Dt:
06/18/2010
Publication #:
Pub Dt:
12/22/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIP CHIP MOUNTING AND METHOD OF MANUFACTURE THEREOF
38
Patent #:
NONE
Issue Dt:
Application #:
13038384
Filing Dt:
03/01/2011
Publication #:
Pub Dt:
09/06/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
39
Patent #:
NONE
Issue Dt:
Application #:
13039309
Filing Dt:
03/02/2011
Publication #:
Pub Dt:
09/06/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMP BONDED DIES AND METHOD OF MANUFACTURE THEREOF
40
Patent #:
NONE
Issue Dt:
Application #:
13209837
Filing Dt:
08/15/2011
Publication #:
Pub Dt:
12/08/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INCREASED CONNECTIVITY AND METHOD OF MANUFACTURE THEREOF
41
Patent #:
Issue Dt:
04/19/2016
Application #:
13211303
Filing Dt:
08/16/2011
Publication #:
Pub Dt:
12/08/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MAGNETIC FILM AND METHOD OF MANUFACTURE THEREOF
42
Patent #:
NONE
Issue Dt:
Application #:
14341578
Filing Dt:
07/25/2014
Publication #:
Pub Dt:
11/13/2014
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING STRUCTURE
Assignor
1
Exec Dt:
03/29/2016
Assignee
1
5 YISHUN STREET 23
SINGAPORE, SINGAPORE 569059
Correspondence name and address
WONG & REES LLP
4677 OLD IRONSIDES DRIVE
SUITE 370
SANTA CLARA, CA 95054

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