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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:019047/0482   Pages: 6
Recorded: 03/22/2007
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 35
1
Patent #:
Issue Dt:
07/11/2000
Application #:
09379479
Filing Dt:
08/23/1999
Title:
FLASH MEMORY ARCHITECTURE EMPLOYING THREE LAYER METAL INTERCONNECT FOR WORD LINE DECODING
2
Patent #:
Issue Dt:
09/12/2000
Application #:
09417731
Filing Dt:
10/14/1999
Title:
DISTRIBUTING CFI DEVICES IN EXISTING DECODERS
3
Patent #:
Issue Dt:
11/07/2000
Application #:
09417732
Filing Dt:
10/14/1999
Title:
METHOD AND SYSTEM FOR BI-DIRECTIONAL VOLTAGE REGULATION DETECTION
4
Patent #:
Issue Dt:
09/12/2000
Application #:
09421151
Filing Dt:
10/19/1999
Title:
SOURCE BIAS COMPENSATION FOR PAGE MODE READ OPERATION IN A FLASH MEMORY DEVICE
5
Patent #:
Issue Dt:
05/29/2001
Application #:
09427406
Filing Dt:
10/25/1999
Title:
METHOD OF BITLINE SHIELDING IN CONJUNCTION WITH A PRECHARGING SCHEME FOR NAND-BASED FLASH MEMORY DEVICES
6
Patent #:
Issue Dt:
01/16/2001
Application #:
09433187
Filing Dt:
10/25/1999
Title:
PRECHARGING MECHANISM AND METHOD FOR NAND-BASED FLASH MEMORY DEVICES
7
Patent #:
Issue Dt:
03/20/2001
Application #:
09504558
Filing Dt:
02/15/2000
Title:
System and method for detecting flash memory threshold voltages
8
Patent #:
Issue Dt:
07/24/2001
Application #:
09504695
Filing Dt:
02/16/2000
Title:
Method of erasing non-volatile memory cells
9
Patent #:
Issue Dt:
04/10/2001
Application #:
09504696
Filing Dt:
02/16/2000
Title:
Method of maintaining constant erasing speeds for non-volatile memory cells
10
Patent #:
Issue Dt:
06/05/2001
Application #:
09505259
Filing Dt:
02/16/2000
Title:
Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cell
11
Patent #:
Issue Dt:
09/04/2001
Application #:
09523816
Filing Dt:
03/13/2000
Title:
Wordline voltage protection
12
Patent #:
Issue Dt:
08/06/2002
Application #:
09547660
Filing Dt:
04/12/2000
Title:
TRIMMING METHOD AND SYSTEM FOR WORDLINE BOOSTER TO MINIMIZE PROCESS VARIATION OF BOOSTED WORDLINE VOLTAGE
13
Patent #:
Issue Dt:
07/31/2001
Application #:
09547747
Filing Dt:
04/12/2000
Title:
Charge sharing to help boost the wordlines during apde verify
14
Patent #:
Issue Dt:
04/24/2001
Application #:
09557832
Filing Dt:
04/26/2000
Title:
Auto adjusting window placement scheme for an NROM virtual ground array
15
Patent #:
Issue Dt:
03/19/2002
Application #:
09592474
Filing Dt:
06/09/2000
Title:
Activation of wordline decoders to transfer a high voltage supply
16
Patent #:
Issue Dt:
04/03/2001
Application #:
09602095
Filing Dt:
06/22/2000
Title:
Voltage protection of write protect cams
17
Patent #:
Issue Dt:
08/07/2001
Application #:
09602328
Filing Dt:
06/23/2000
Title:
Apparatus and method of direct current sensing from source side in a virtual ground array
18
Patent #:
Issue Dt:
05/04/2004
Application #:
09664819
Filing Dt:
09/19/2000
Title:
INTEGRATION OF EMBEDDED AND TEST MODE TIMER
19
Patent #:
Issue Dt:
04/09/2002
Application #:
09667347
Filing Dt:
09/22/2000
Title:
Serial sequencing of automatic program disturb erase verify during a fast erase mode
20
Patent #:
Issue Dt:
11/05/2002
Application #:
09686685
Filing Dt:
10/11/2000
Title:
SELECT TRANSISTOR ARCHITECTURE FOR A VIRTUAL GROUND NON-VOLATILE MEMORY CELL ARRAY
21
Patent #:
Issue Dt:
07/31/2001
Application #:
09694729
Filing Dt:
10/23/2000
Title:
Method of programming a non-volatile memory cell using a current limiter
22
Patent #:
Issue Dt:
12/18/2001
Application #:
09697810
Filing Dt:
10/26/2000
Title:
Positive gate erasure for non-volatile memory cells
23
Patent #:
Issue Dt:
12/18/2001
Application #:
09697813
Filing Dt:
10/26/2000
Title:
Intelligent ramped gate and ramped drain erasure for non-volatile memory cells
24
Patent #:
Issue Dt:
12/03/2002
Application #:
09697814
Filing Dt:
10/26/2000
Title:
METHOD OF ERASING A NON-VOLATILE MEMORY CELL USING A SUBSTRATE BIAS
25
Patent #:
Issue Dt:
07/15/2003
Application #:
09718771
Filing Dt:
11/22/2000
Title:
STAGGERED BITLINE STRAPPING OF A NON-VOLATILE MEMORY CELL
26
Patent #:
Issue Dt:
10/29/2002
Application #:
09718986
Filing Dt:
11/22/2000
Title:
METHOD AND SYSTEM FOR TESTING A SEMICONDUCTOR MEMORY DEVICE
27
Patent #:
Issue Dt:
03/25/2003
Application #:
09721031
Filing Dt:
11/22/2000
Title:
STAGGERED BITLINE STRAPPING OF A NON-VOLATILE MEMORY CELL
28
Patent #:
Issue Dt:
07/09/2002
Application #:
09721066
Filing Dt:
11/22/2000
Title:
PROCESS FOR REDUCTION OF CAPACITANCE OF A BITLINE FOR A NON-VOLATILE MEMORY CELL
29
Patent #:
Issue Dt:
10/01/2002
Application #:
09767341
Filing Dt:
01/23/2001
Title:
THREE METAL PROCESS FOR OPTIMIZING LAYOUT DENSITY
30
Patent #:
Issue Dt:
09/09/2003
Application #:
09880366
Filing Dt:
06/13/2001
Title:
METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A BAKING PROCESS
31
Patent #:
Issue Dt:
09/24/2002
Application #:
09884402
Filing Dt:
06/19/2001
Title:
METHOD OF DRAIN AVALANCHE PROGRAMMING OF A NON-VOLATILE MEMORY CELL
32
Patent #:
Issue Dt:
09/24/2002
Application #:
09884409
Filing Dt:
06/19/2001
Title:
METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A SUBSTRATE BIAS
33
Patent #:
Issue Dt:
10/24/2006
Application #:
09885426
Filing Dt:
06/19/2001
Title:
SILICIDED BURIED BITLINE PROCESS FOR A NON-VOLATILE MEMORY CELL
34
Patent #:
Issue Dt:
11/26/2002
Application #:
09899721
Filing Dt:
07/05/2001
Title:
METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A VERTICAL ELECTRIC FIELD
35
Patent #:
Issue Dt:
06/15/2004
Application #:
10199793
Filing Dt:
07/19/2002
Title:
NONVOLATILE MEMORY CELL WITH A NITRIDATED OXIDE LAYER
Assignor
1
Exec Dt:
01/31/2007
Assignee
1
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CALIFORNIA 94088-3453
Correspondence name and address
RAYMOND E. FRITZ
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CA 94088-3453

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