Total properties:
35
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Patent #:
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Issue Dt:
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07/11/2000
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Application #:
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09379479
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Filing Dt:
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08/23/1999
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Title:
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FLASH MEMORY ARCHITECTURE EMPLOYING THREE LAYER METAL INTERCONNECT FOR WORD LINE DECODING
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09417731
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Filing Dt:
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10/14/1999
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Title:
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DISTRIBUTING CFI DEVICES IN EXISTING DECODERS
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09417732
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Filing Dt:
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10/14/1999
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Title:
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METHOD AND SYSTEM FOR BI-DIRECTIONAL VOLTAGE REGULATION DETECTION
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09421151
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Filing Dt:
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10/19/1999
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Title:
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SOURCE BIAS COMPENSATION FOR PAGE MODE READ OPERATION IN A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09427406
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Filing Dt:
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10/25/1999
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Title:
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METHOD OF BITLINE SHIELDING IN CONJUNCTION WITH A PRECHARGING SCHEME FOR NAND-BASED FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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01/16/2001
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Application #:
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09433187
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Filing Dt:
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10/25/1999
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Title:
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PRECHARGING MECHANISM AND METHOD FOR NAND-BASED FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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09504558
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Filing Dt:
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02/15/2000
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Title:
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System and method for detecting flash memory threshold voltages
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09504695
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Filing Dt:
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02/16/2000
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Title:
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Method of erasing non-volatile memory cells
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09504696
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Filing Dt:
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02/16/2000
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Title:
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Method of maintaining constant erasing speeds for non-volatile memory cells
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09505259
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Filing Dt:
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02/16/2000
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Title:
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Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cell
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09523816
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Filing Dt:
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03/13/2000
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Title:
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Wordline voltage protection
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09547660
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Filing Dt:
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04/12/2000
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Title:
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TRIMMING METHOD AND SYSTEM FOR WORDLINE BOOSTER TO MINIMIZE PROCESS VARIATION OF BOOSTED WORDLINE VOLTAGE
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09547747
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Filing Dt:
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04/12/2000
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Title:
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Charge sharing to help boost the wordlines during apde verify
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09557832
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Filing Dt:
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04/26/2000
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Title:
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Auto adjusting window placement scheme for an NROM virtual ground array
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Patent #:
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Issue Dt:
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03/19/2002
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Application #:
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09592474
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Filing Dt:
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06/09/2000
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Title:
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Activation of wordline decoders to transfer a high voltage supply
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09602095
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Filing Dt:
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06/22/2000
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Title:
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Voltage protection of write protect cams
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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09602328
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Filing Dt:
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06/23/2000
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Title:
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Apparatus and method of direct current sensing from source side in a virtual ground array
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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09664819
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Filing Dt:
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09/19/2000
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Title:
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INTEGRATION OF EMBEDDED AND TEST MODE TIMER
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09667347
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Filing Dt:
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09/22/2000
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Title:
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Serial sequencing of automatic program disturb erase verify during a fast erase mode
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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09686685
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Filing Dt:
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10/11/2000
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Title:
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SELECT TRANSISTOR ARCHITECTURE FOR A VIRTUAL GROUND NON-VOLATILE MEMORY CELL ARRAY
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09694729
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Filing Dt:
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10/23/2000
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Title:
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Method of programming a non-volatile memory cell using a current limiter
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Patent #:
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Issue Dt:
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12/18/2001
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Application #:
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09697810
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Filing Dt:
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10/26/2000
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Title:
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Positive gate erasure for non-volatile memory cells
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Patent #:
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Issue Dt:
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12/18/2001
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Application #:
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09697813
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Filing Dt:
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10/26/2000
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Title:
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Intelligent ramped gate and ramped drain erasure for non-volatile memory cells
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Patent #:
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Issue Dt:
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12/03/2002
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Application #:
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09697814
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Filing Dt:
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10/26/2000
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Title:
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METHOD OF ERASING A NON-VOLATILE MEMORY CELL USING A SUBSTRATE BIAS
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Patent #:
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|
Issue Dt:
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07/15/2003
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Application #:
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09718771
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Filing Dt:
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11/22/2000
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Title:
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STAGGERED BITLINE STRAPPING OF A NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09718986
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Filing Dt:
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11/22/2000
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Title:
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METHOD AND SYSTEM FOR TESTING A SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09721031
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Filing Dt:
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11/22/2000
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Title:
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STAGGERED BITLINE STRAPPING OF A NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09721066
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Filing Dt:
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11/22/2000
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Title:
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PROCESS FOR REDUCTION OF CAPACITANCE OF A BITLINE FOR A NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09767341
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Filing Dt:
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01/23/2001
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Title:
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THREE METAL PROCESS FOR OPTIMIZING LAYOUT DENSITY
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09880366
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Filing Dt:
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06/13/2001
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Title:
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METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A BAKING PROCESS
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09884402
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Filing Dt:
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06/19/2001
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Title:
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METHOD OF DRAIN AVALANCHE PROGRAMMING OF A NON-VOLATILE MEMORY CELL
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|
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09884409
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Filing Dt:
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06/19/2001
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Title:
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METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A SUBSTRATE BIAS
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|
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Patent #:
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Issue Dt:
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10/24/2006
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Application #:
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09885426
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Filing Dt:
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06/19/2001
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Title:
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SILICIDED BURIED BITLINE PROCESS FOR A NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09899721
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Filing Dt:
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07/05/2001
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Title:
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METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A VERTICAL ELECTRIC FIELD
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Patent #:
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|
Issue Dt:
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06/15/2004
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Application #:
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10199793
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Filing Dt:
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07/19/2002
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Title:
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NONVOLATILE MEMORY CELL WITH A NITRIDATED OXIDE LAYER
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