Total properties:
27
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Patent #:
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Issue Dt:
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01/09/2007
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Application #:
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09945393
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Filing Dt:
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08/30/2001
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Publication #:
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Pub Dt:
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03/06/2003
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Title:
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DIELECTRIC MATERIAL FORMING METHODS AND ENHANCED DIELECTRIC MATERIALS
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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09997073
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Filing Dt:
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11/28/2001
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Publication #:
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Pub Dt:
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05/29/2003
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Title:
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CVD OF PTRH WITH GOOD ADHESION AND MORPHOLOGY
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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10092829
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Filing Dt:
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03/06/2002
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Title:
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NANOTUBE SEMICONDUCTOR DEVICES AND METHODS FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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10/24/2006
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Application #:
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10932771
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Filing Dt:
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09/02/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
Title:
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REDUCING ASYMMETRICALLY DEPOSITED FILM INDUCED REGISTRATION ERROR
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10940231
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Filing Dt:
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09/14/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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TEMPERATURE-DEPENDENT DRAM SELF-REFRESH CIRCUIT
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Patent #:
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Issue Dt:
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04/15/2008
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Application #:
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11481022
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Filing Dt:
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07/06/2006
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Publication #:
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Pub Dt:
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01/10/2008
| | | | |
Title:
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METHODS FOR PROGRAMMING AND READING NAND FLASH MEMORY DEVICE AND PAGE BUFFER PERFORMING THE SAME
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Patent #:
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Issue Dt:
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05/29/2012
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Application #:
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11610573
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Filing Dt:
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12/14/2006
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Publication #:
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Pub Dt:
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06/19/2008
| | | | |
Title:
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WORD LINE DRIVER IN A HIERARCHICAL NOR FLASH MEMORY
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Patent #:
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Issue Dt:
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12/08/2009
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Application #:
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11932451
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Filing Dt:
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10/31/2007
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Publication #:
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Pub Dt:
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04/30/2009
| | | | |
Title:
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TEMPERATURE DETECTOR IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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12/10/2013
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Application #:
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12773340
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Filing Dt:
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05/04/2010
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Publication #:
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Pub Dt:
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04/21/2011
| | | | |
Title:
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RECONFIGURING THROUGH SILICON VIAS IN STACKED MULTI-DIE PACKAGES
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Patent #:
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Issue Dt:
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02/24/2015
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Application #:
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12967918
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Filing Dt:
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12/14/2010
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Publication #:
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Pub Dt:
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08/25/2011
| | | | |
Title:
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SEMICONDUCTOR MEMORY DEVICE WITH PLURAL MEMORY DIE AND CONTROLLER DIE
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Patent #:
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Issue Dt:
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08/04/2015
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Application #:
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13038461
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Filing Dt:
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03/02/2011
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Publication #:
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Pub Dt:
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09/22/2011
| | | | |
Title:
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COMPOSITE SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION
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Patent #:
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Issue Dt:
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06/11/2013
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Application #:
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13040324
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Filing Dt:
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03/04/2011
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Publication #:
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Pub Dt:
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12/15/2011
| | | | |
Title:
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SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION
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|
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Patent #:
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|
Issue Dt:
|
08/06/2013
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Application #:
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13042571
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Filing Dt:
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03/08/2011
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Publication #:
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Pub Dt:
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03/08/2012
| | | | |
Title:
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MULTI-CHIP PACKAGE WITH OFFSET DIE STACKING
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Patent #:
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Issue Dt:
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11/19/2013
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Application #:
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13090427
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Filing Dt:
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04/20/2011
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Publication #:
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Pub Dt:
|
01/05/2012
| | | | |
Title:
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MULTI-CHIP PACKAGE WITH THERMAL FRAME AND METHOD OF ASSEMBLING
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Patent #:
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Issue Dt:
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10/21/2014
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Application #:
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13094613
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Filing Dt:
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04/26/2011
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Publication #:
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Pub Dt:
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12/22/2011
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH CONFIGURABLE THROUGH-SILICON VIAS
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Patent #:
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Issue Dt:
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05/12/2015
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Application #:
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13094619
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Filing Dt:
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04/26/2011
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Publication #:
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Pub Dt:
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12/22/2011
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH THROUGH-SILICON VIAS
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Patent #:
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|
Issue Dt:
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09/03/2013
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Application #:
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13110399
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Filing Dt:
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05/18/2011
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Publication #:
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Pub Dt:
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12/29/2011
| | | | |
Title:
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PHASE CHANGE MEMORY WORD LINE DRIVER
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Patent #:
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Issue Dt:
|
06/04/2013
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Application #:
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13477431
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Filing Dt:
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05/22/2012
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Publication #:
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|
Pub Dt:
|
09/13/2012
| | | | |
Title:
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Method for Erasing Memory Cells in a Flash Memory Device Using a Positive Well Bias Voltage and a Negative Word Line Voltage
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Patent #:
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Issue Dt:
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07/15/2014
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Application #:
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13860724
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Filing Dt:
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04/11/2013
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Publication #:
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Pub Dt:
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08/22/2013
| | | | |
Title:
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PHASE-CHANGE MEMORY WITH MULTIPLE POLARITY BITS HAVING ENHANCED ENDURANCE AND ERROR TOLERANCE
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Patent #:
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Issue Dt:
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12/15/2015
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Application #:
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13895591
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Filing Dt:
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05/16/2013
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Publication #:
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Pub Dt:
|
09/26/2013
| | | | |
Title:
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METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE
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Patent #:
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|
Issue Dt:
|
07/15/2014
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Application #:
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13912650
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Filing Dt:
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06/07/2013
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Publication #:
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Pub Dt:
|
10/10/2013
| | | | |
Title:
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SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION
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|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
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Application #:
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13973600
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Filing Dt:
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08/22/2013
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Publication #:
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Pub Dt:
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12/19/2013
| | | | |
Title:
|
PHASE CHANGE MEMORY WORD LINE DRIVER
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|
|
Patent #:
|
|
Issue Dt:
|
08/25/2015
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Application #:
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14101507
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Filing Dt:
|
12/10/2013
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Publication #:
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Pub Dt:
|
04/10/2014
| | | | |
Title:
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RECONFIGURING THROUGH SILICON VIAS IN STACKED MULTI-DIE PACKAGES
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|
|
Patent #:
|
|
Issue Dt:
|
05/24/2016
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Application #:
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14625858
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Filing Dt:
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02/19/2015
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Publication #:
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|
Pub Dt:
|
06/11/2015
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH PLURAL MEMORY DIE AND CONTROLLER DIE
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|
|
Patent #:
|
|
Issue Dt:
|
08/09/2016
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Application #:
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14795114
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Filing Dt:
|
07/09/2015
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Publication #:
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|
Pub Dt:
|
10/29/2015
| | | | |
Title:
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COMPOSITE SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2019
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Application #:
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14933264
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Filing Dt:
|
11/05/2015
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Publication #:
|
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Pub Dt:
|
05/19/2016
| | | | |
Title:
|
METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE
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|
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Patent #:
|
|
Issue Dt:
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02/16/2021
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Application #:
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16583352
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Filing Dt:
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09/26/2019
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Publication #:
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Pub Dt:
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03/19/2020
| | | | |
Title:
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METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE
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|