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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:058297/0486   Pages: 4
Recorded: 10/19/2021
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 27
1
Patent #:
Issue Dt:
01/09/2007
Application #:
09945393
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
DIELECTRIC MATERIAL FORMING METHODS AND ENHANCED DIELECTRIC MATERIALS
2
Patent #:
Issue Dt:
07/19/2005
Application #:
09997073
Filing Dt:
11/28/2001
Publication #:
Pub Dt:
05/29/2003
Title:
CVD OF PTRH WITH GOOD ADHESION AND MORPHOLOGY
3
Patent #:
Issue Dt:
02/04/2003
Application #:
10092829
Filing Dt:
03/06/2002
Title:
NANOTUBE SEMICONDUCTOR DEVICES AND METHODS FOR MAKING THE SAME
4
Patent #:
Issue Dt:
10/24/2006
Application #:
10932771
Filing Dt:
09/02/2004
Publication #:
Pub Dt:
02/03/2005
Title:
REDUCING ASYMMETRICALLY DEPOSITED FILM INDUCED REGISTRATION ERROR
5
Patent #:
Issue Dt:
04/25/2006
Application #:
10940231
Filing Dt:
09/14/2004
Publication #:
Pub Dt:
03/02/2006
Title:
TEMPERATURE-DEPENDENT DRAM SELF-REFRESH CIRCUIT
6
Patent #:
Issue Dt:
04/15/2008
Application #:
11481022
Filing Dt:
07/06/2006
Publication #:
Pub Dt:
01/10/2008
Title:
METHODS FOR PROGRAMMING AND READING NAND FLASH MEMORY DEVICE AND PAGE BUFFER PERFORMING THE SAME
7
Patent #:
Issue Dt:
05/29/2012
Application #:
11610573
Filing Dt:
12/14/2006
Publication #:
Pub Dt:
06/19/2008
Title:
WORD LINE DRIVER IN A HIERARCHICAL NOR FLASH MEMORY
8
Patent #:
Issue Dt:
12/08/2009
Application #:
11932451
Filing Dt:
10/31/2007
Publication #:
Pub Dt:
04/30/2009
Title:
TEMPERATURE DETECTOR IN AN INTEGRATED CIRCUIT
9
Patent #:
Issue Dt:
12/10/2013
Application #:
12773340
Filing Dt:
05/04/2010
Publication #:
Pub Dt:
04/21/2011
Title:
RECONFIGURING THROUGH SILICON VIAS IN STACKED MULTI-DIE PACKAGES
10
Patent #:
Issue Dt:
02/24/2015
Application #:
12967918
Filing Dt:
12/14/2010
Publication #:
Pub Dt:
08/25/2011
Title:
SEMICONDUCTOR MEMORY DEVICE WITH PLURAL MEMORY DIE AND CONTROLLER DIE
11
Patent #:
Issue Dt:
08/04/2015
Application #:
13038461
Filing Dt:
03/02/2011
Publication #:
Pub Dt:
09/22/2011
Title:
COMPOSITE SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION
12
Patent #:
Issue Dt:
06/11/2013
Application #:
13040324
Filing Dt:
03/04/2011
Publication #:
Pub Dt:
12/15/2011
Title:
SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION
13
Patent #:
Issue Dt:
08/06/2013
Application #:
13042571
Filing Dt:
03/08/2011
Publication #:
Pub Dt:
03/08/2012
Title:
MULTI-CHIP PACKAGE WITH OFFSET DIE STACKING
14
Patent #:
Issue Dt:
11/19/2013
Application #:
13090427
Filing Dt:
04/20/2011
Publication #:
Pub Dt:
01/05/2012
Title:
MULTI-CHIP PACKAGE WITH THERMAL FRAME AND METHOD OF ASSEMBLING
15
Patent #:
Issue Dt:
10/21/2014
Application #:
13094613
Filing Dt:
04/26/2011
Publication #:
Pub Dt:
12/22/2011
Title:
SEMICONDUCTOR DEVICE WITH CONFIGURABLE THROUGH-SILICON VIAS
16
Patent #:
Issue Dt:
05/12/2015
Application #:
13094619
Filing Dt:
04/26/2011
Publication #:
Pub Dt:
12/22/2011
Title:
SEMICONDUCTOR DEVICE WITH THROUGH-SILICON VIAS
17
Patent #:
Issue Dt:
09/03/2013
Application #:
13110399
Filing Dt:
05/18/2011
Publication #:
Pub Dt:
12/29/2011
Title:
PHASE CHANGE MEMORY WORD LINE DRIVER
18
Patent #:
Issue Dt:
06/04/2013
Application #:
13477431
Filing Dt:
05/22/2012
Publication #:
Pub Dt:
09/13/2012
Title:
Method for Erasing Memory Cells in a Flash Memory Device Using a Positive Well Bias Voltage and a Negative Word Line Voltage
19
Patent #:
Issue Dt:
07/15/2014
Application #:
13860724
Filing Dt:
04/11/2013
Publication #:
Pub Dt:
08/22/2013
Title:
PHASE-CHANGE MEMORY WITH MULTIPLE POLARITY BITS HAVING ENHANCED ENDURANCE AND ERROR TOLERANCE
20
Patent #:
Issue Dt:
12/15/2015
Application #:
13895591
Filing Dt:
05/16/2013
Publication #:
Pub Dt:
09/26/2013
Title:
METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE
21
Patent #:
Issue Dt:
07/15/2014
Application #:
13912650
Filing Dt:
06/07/2013
Publication #:
Pub Dt:
10/10/2013
Title:
SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMPLIFIER AND BITLINE ISOLATION
22
Patent #:
Issue Dt:
11/04/2014
Application #:
13973600
Filing Dt:
08/22/2013
Publication #:
Pub Dt:
12/19/2013
Title:
PHASE CHANGE MEMORY WORD LINE DRIVER
23
Patent #:
Issue Dt:
08/25/2015
Application #:
14101507
Filing Dt:
12/10/2013
Publication #:
Pub Dt:
04/10/2014
Title:
RECONFIGURING THROUGH SILICON VIAS IN STACKED MULTI-DIE PACKAGES
24
Patent #:
Issue Dt:
05/24/2016
Application #:
14625858
Filing Dt:
02/19/2015
Publication #:
Pub Dt:
06/11/2015
Title:
SEMICONDUCTOR MEMORY DEVICE WITH PLURAL MEMORY DIE AND CONTROLLER DIE
25
Patent #:
Issue Dt:
08/09/2016
Application #:
14795114
Filing Dt:
07/09/2015
Publication #:
Pub Dt:
10/29/2015
Title:
COMPOSITE SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION
26
Patent #:
Issue Dt:
11/05/2019
Application #:
14933264
Filing Dt:
11/05/2015
Publication #:
Pub Dt:
05/19/2016
Title:
METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE
27
Patent #:
Issue Dt:
02/16/2021
Application #:
16583352
Filing Dt:
09/26/2019
Publication #:
Pub Dt:
03/19/2020
Title:
METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE
Assignor
1
Exec Dt:
04/01/2021
Assignee
1
515 LEGGET DRIVE
SUITE 100
OTTAWA, CANADA K2K 3G4
Correspondence name and address
CONVERSANT IP MANAGEMENT CORP.
5830 GRANITE PARKWAY #100-247
SUITE 247
PLANO, TX 75024

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