Total properties:
278
Page
1
of
3
Pages:
1 2 3
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/1999
|
Application #:
|
08458479
|
Filing Dt:
|
06/02/1995
|
|
Title:
|
ADDRESS TRANSLATION METHOD AND MECHANISM USING PHYSICAL ADDRESS INFORMATION INCLUDING DURING A SEGMENTATION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/29/2000
|
Application #:
|
08678541
|
Filing Dt:
|
07/05/1996
|
|
Title:
|
COMBINING HARDWARE AND SOFTWARE TO PROVIDE AN IMPROVED MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
08685721
|
Filing Dt:
|
07/24/1996
|
|
Title:
|
HOST MICROPROCESSOR WITH APPARATUS FOR TEMPORARILY HOLDING TARGET PROCESSOR STATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/1998
|
Application #:
|
08700302
|
Filing Dt:
|
08/20/1996
|
|
Title:
|
A MEMORY CONTROLLER FOR A MICROPROCESSOR FOR DETECTING A FAILURE OF SPECULATION ON THE PHYSICAL NATURE OF A COMPONENT BEING ADDRESSED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
08702771
|
Filing Dt:
|
08/22/1996
|
|
Title:
|
TRANSLATED MEMORY PROTECTION APPARATUS FOR AN ADVANCED MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/1999
|
Application #:
|
08721698
|
Filing Dt:
|
09/26/1996
|
|
Title:
|
NETHOD AND APPARATUS FOR ALIASING MEMORY DATA IN AN ADVANCED MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2000
|
Application #:
|
08772686
|
Filing Dt:
|
12/23/1996
|
|
Title:
|
A GATED STORE BUFFER FOR AN ADVANCED MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/1999
|
Application #:
|
08807542
|
Filing Dt:
|
02/28/1997
|
|
Title:
|
METHOD AND APPARATUS FOR CORRECTING ERRORS IN COMPUTER SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
08905356
|
Filing Dt:
|
08/04/1997
|
|
Title:
|
Address translation mechanism and method in a computer system
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
08905410
|
Filing Dt:
|
08/04/1997
|
|
Title:
|
Computer address translation using fast address generator during a segmentation operation performed on a virtual address
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
09332338
|
Filing Dt:
|
06/14/1999
|
|
Title:
|
METHOD AND APPARATUS FOR ENHANCING SCHEDULING IN AN ADVANCED MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
09333178
|
Filing Dt:
|
06/14/1999
|
|
Title:
|
MEMORY ARRAY BITLINE TIMING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
09417332
|
Filing Dt:
|
10/13/1999
|
|
Title:
|
METHOD FOR SWITCHING BETWEEN INTERPRETATION AND DYNAMIC TRANSLATION IN A PROCESSOR SYSTEM BASED UPON CODE SEQUENCE EXECUTION COUNTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09417356
|
Filing Dt:
|
10/13/1999
|
|
Title:
|
FINE GRAIN TRANSLATION DISCRIMINATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
09417358
|
Filing Dt:
|
10/13/1999
|
|
Title:
|
SYSTEM FOR USING RATE OF EXCEPTION EVENT GENERATION DURING EXECUTION OF TRANSLATED INSTRUCTIONS TO CONTROL OPTIMIZATION OF THE TRANSLATED INSTRUCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2002
|
Application #:
|
09417930
|
Filing Dt:
|
10/13/1999
|
|
Title:
|
PROGRAMMABLE EVENT COUNTER SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2005
|
Application #:
|
09417979
|
Filing Dt:
|
10/13/1999
|
|
Title:
|
METHOD OF OPTIMIZING COMPILER VS INTERPRETER MODE OPERATION IN A CODE TRANSLATOR BASED UPON AMOUNT OF TIME SPENT IN EACH MODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
09417980
|
Filing Dt:
|
10/13/1999
|
|
Title:
|
METHOD FOR TRANSLATING INSTRUCTIONS IN A SPECULATIVE MICROPROCESSOR FEATURING COMMITTING STATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2002
|
Application #:
|
09417981
|
Filing Dt:
|
10/13/1999
|
|
Title:
|
METHOD AND APPARATUS FOR MAINTAINING CONTEXT WHILE EXECUTING TRANSLATED INSTRUCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
09420748
|
Filing Dt:
|
10/20/1999
|
|
Title:
|
PIPELINE REPLAY SUPPORT FOR UNALIGNED MEMORY OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
09421484
|
Filing Dt:
|
10/20/1999
|
|
Title:
|
METHOD FOR INCREASING THE SPEED OF SPECULATIVE EXECUTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09421614
|
Filing Dt:
|
10/20/1999
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2002
| | | | |
|
Title:
|
ELECTROSTATIC DISCHARGE PROTECTION FOR MOSFETS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
09421615
|
Filing Dt:
|
10/20/1999
|
|
Title:
|
USE OF ENABLE BITS TO CONTROL EXECUTION OF SELECTED INSTRUCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2003
|
Application #:
|
09421972
|
Filing Dt:
|
10/20/1999
|
|
Title:
|
PIPELINE REPLAY SUPPORT FOR MULTI-CYCLE OPERATIONS WHEREIN ALL VLIW INSTRUCTIONS ARE FLUSHED UPON DETECTION OF A MULTI-CYCLE ATOM OPERATION IN A VLIW INSTRUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2004
|
Application #:
|
09464638
|
Filing Dt:
|
12/15/1999
|
|
Title:
|
INSTRUCTION PACKING FOR AN ADVANCED MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2003
|
Application #:
|
09464644
|
Filing Dt:
|
12/15/1999
|
|
Title:
|
CHECK INSTRUCTION AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2003
|
Application #:
|
09464661
|
Filing Dt:
|
12/15/1999
|
|
Title:
|
SOFTWARE DIRECT MEMORY ACCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2005
|
Application #:
|
09471447
|
Filing Dt:
|
12/23/1999
|
|
Title:
|
INTERPAGE PROLOGUE TO PROTECT VIRTUAL ADDRESS MAPPINGS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
09484516
|
Filing Dt:
|
01/18/2000
|
|
Publication #:
|
|
Pub Dt:
|
08/22/2002
| | | | |
|
Title:
|
ADAPTIVE POWER CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2003
|
Application #:
|
09539987
|
Filing Dt:
|
03/30/2000
|
|
Title:
|
TRANSLATION CONSISTENCY CHECKING FOR MODIFIED TARGET INSTRUCTIONS BY COMPARING TO ORIGINAL COPY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
09557650
|
Filing Dt:
|
04/25/2000
|
|
Title:
|
METHOD AND APPARATUS FOR SCHEDULING TO REDUCE SPACE AND INCREASE SPEED OF MICROPROCESSOR OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2003
|
Application #:
|
09595077
|
Filing Dt:
|
06/16/2000
|
|
Title:
|
CACHE MEMORY ARRAY FOR MULTIPLE ADDRESS SPACES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2005
|
Application #:
|
09595198
|
Filing Dt:
|
06/16/2000
|
|
Title:
|
SYSTEM AND METHOD FOR PRESERVING INTERNAL PROCESSOR CONTEXT WHEN THE PROCESSOR IS POWERED DOWN AND RESTORING THE INTERNAL PROCESSOR CONTEXT WHEN PROCESSOR IS RESTORED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2004
|
Application #:
|
09595199
|
Filing Dt:
|
06/16/2000
|
|
Title:
|
METHOD AND APPARATUS FOR EMULATING A FLOATING POINT STACK IN A TRANSLATION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2003
|
Application #:
|
09596279
|
Filing Dt:
|
06/19/2000
|
|
Title:
|
FAST LOOK-UP OF INDIRECT BRANCH DESTINATION IN A DYNAMIC TRANSLATION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2003
|
Application #:
|
09596280
|
Filing Dt:
|
06/19/2000
|
|
Title:
|
LINK PIPE SYSTEM FOR STORAGE AND RETRIEVAL OF SEQUENCES OF BRANCH ADDRESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2004
|
Application #:
|
09603743
|
Filing Dt:
|
06/26/2000
|
|
Title:
|
FLOATING POINT EXCEPTION HANDLING IN PIPELINED PROCESSOR USING SPECIAL INSTRUCTION TO DETECT GENERATED EXCEPTION AND EXECUTE INSTRUCTIONS SINGLY FROM KNOWN CORRECT STATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
09694433
|
Filing Dt:
|
10/23/2000
|
|
Title:
|
SAVING POWER WHEN IN OR TRANSITIONING TO A STATIC MODE OF A PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
09699947
|
Filing Dt:
|
10/30/2000
|
|
Title:
|
TRANSLATED MEMORY PROTECTION APPARATUS FOR AN ADVANCED MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09757439
|
Filing Dt:
|
01/10/2001
|
|
Publication #:
|
|
Pub Dt:
|
09/06/2001
| | | | |
|
Title:
|
Speculative address translation for processor using segmentation and optical paging
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2004
|
Application #:
|
09822929
|
Filing Dt:
|
03/30/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/03/2002
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR ACCELERATING FAULT HANDLING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2004
|
Application #:
|
09822933
|
Filing Dt:
|
03/30/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/03/2002
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR HANDLING NESTED FAULTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2005
|
Application #:
|
09930625
|
Filing Dt:
|
08/15/2001
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2003
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR IMPROVING SEGMENTED MEMORY ADDRESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2005
|
Application #:
|
10124152
|
Filing Dt:
|
04/16/2002
|
|
Title:
|
SYSTEM AND METHOD FOR MEASURING TRANSISTOR LEAKAGE CURRENT WITH A RING OSCILLATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10166432
|
Filing Dt:
|
06/10/2002
|
|
Title:
|
SPECULATIVE ADDRESS TRANSLATION FOR PROCESSOR USING SEGMENTATION AND OPTIONAL PAGING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2008
|
Application #:
|
10273681
|
Filing Dt:
|
10/17/2002
|
|
Title:
|
APPARATUS FOR CONTROLLING SEMICONDUCTOR CHIP CHARACTERISTICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10334264
|
Filing Dt:
|
12/31/2002
|
|
Title:
|
DYNAMIC NODE KEEPER SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10334272
|
Filing Dt:
|
12/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
DIAGONAL DEEP WELL REGION FOR ROUTING BODY-BIAS VOLTAGE FOR MOSFETS IN SURFACE WELL REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
10334638
|
Filing Dt:
|
12/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
SOFTWARE CONTROLLED TRANSISTOR BODY BIAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
10334748
|
Filing Dt:
|
12/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
ADAPTIVE POWER CONTROL BASED ON PRE PACKAGE CHARACTERIZATION OF INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
10334918
|
Filing Dt:
|
12/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
ADAPTIVE POWER CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
|
Application #:
|
10334919
|
Filing Dt:
|
12/31/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
ADAPTIVE POWER CONTROL BASED ON POST PACKAGE CHARACTERIZATION OF INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
10335405
|
Filing Dt:
|
12/30/2002
|
|
Title:
|
METHOD AND SYSTEM FOR USING EXTERNAL STORAGE TO AMORTIZE CPU CYCLE UTILIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2007
|
Application #:
|
10335459
|
Filing Dt:
|
12/30/2002
|
|
Title:
|
METHOD AND SYSTEM FOR USING IDIOM RECOGNITION DURING A SOFTWARE TRANSLATION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2007
|
Application #:
|
10406022
|
Filing Dt:
|
04/02/2003
|
|
Title:
|
METHODS AND SYSTEMS EMPLOYING A FLAG FOR DEFERRING EXCEPTION HANDLING TO A COMMIT OR ROLLBACK POINT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2009
|
Application #:
|
10411168
|
Filing Dt:
|
04/09/2003
|
|
Title:
|
SYSTEM AND METHOD FOR HANDLING DIRECT MEMORY ACCESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10411955
|
Filing Dt:
|
04/10/2003
|
|
Title:
|
SYSTEM FOR ON-CHIP TEMPERATURE MEASUREMENT IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
10438158
|
Filing Dt:
|
05/13/2003
|
|
Title:
|
TRANSLATED MEMORY PROTECTION APPARATUS FOR AN ADVANCED MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2005
|
Application #:
|
10439659
|
Filing Dt:
|
05/16/2003
|
|
Title:
|
TEMPERATURE COMPENSATED INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2004
|
Application #:
|
10439665
|
Filing Dt:
|
05/16/2003
|
|
Title:
|
VOLTAGE COMPENSATED INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2006
|
Application #:
|
10463223
|
Filing Dt:
|
06/16/2003
|
|
Title:
|
PIPELINE REPLAY SUPPORT FOR UNALIGNED MEMORY OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
10463233
|
Filing Dt:
|
06/17/2003
|
|
Title:
|
FAST LOOK-UP OF INDIRECT BRANCH DESTINATION IN A DYNAMIC TRANSLATION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2010
|
Application #:
|
10463820
|
Filing Dt:
|
06/16/2003
|
|
Title:
|
PIPELINE REPLAY SUPPORT FOR MULTI-CYCLE OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10463846
|
Filing Dt:
|
06/16/2003
|
|
Title:
|
SWITCHING TO ORIGINAL MODIFIABLE INSTRUCTION COPY COMPARISON CHECK TO VALIDATE PRIOR TRANSLATION WHEN TRANSLATED SUB-AREA PROTECTION EXCEPTION SLOWS DOWN OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
10464871
|
Filing Dt:
|
06/18/2003
|
|
Title:
|
METHOD FOR INCREASING THE SPEED OF SPECULATIVE EXECUTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
10600989
|
Filing Dt:
|
06/20/2003
|
|
Title:
|
METHODS AND SYSTEMS FOR MAINTAINING INFORMATION FOR LOCATING NON-NATIVE PROCESSOR INSTRUCTIONS WHEN EXECUTING NATIVE PROCESSOR INSTRUCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10607480
|
Filing Dt:
|
06/25/2003
|
|
Title:
|
METHOD AND SYSTEM FOR IMPLEMENTING A FLOATING POINT COMPARE USING RECORDED FLAGS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
10607934
|
Filing Dt:
|
06/27/2003
|
|
Title:
|
METHOD AND SYSTEM FOR PROVIDING HARDWARE SUPPORT FOR MEMORY PROTECTION AND VIRTUAL MEMORY ADDRESS TRANSLATION FOR A VIRTUAL MACHINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
10609158
|
Filing Dt:
|
06/27/2003
|
|
Title:
|
METHOD AND SYSTEM FOR SUPPORTING INPUT/OUTPUT FOR A VIRTUAL MACHINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10613801
|
Filing Dt:
|
07/03/2003
|
|
Title:
|
METHOD AND SYSTEM FOR CACHING ATTRIBUTE DATA FOR MATCHING ATTRIBUTES WITH PHYSICAL ADDRESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2008
|
Application #:
|
10620862
|
Filing Dt:
|
07/15/2003
|
|
Title:
|
EXPLICIT CONTROL OF SPECULATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
10622028
|
Filing Dt:
|
07/16/2003
|
|
Title:
|
SUPPORTING SPECULATIVE MODIFICATION IN A DATA CACHE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10623021
|
Filing Dt:
|
07/17/2003
|
|
Title:
|
METHOD AND SYSTEM FOR ENFORCING CONSISTENT PER-PHYSICAL PAGE CACHEABILITY ATTRIBUTES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/2009
|
Application #:
|
10623101
|
Filing Dt:
|
07/18/2003
|
|
Title:
|
METHOD AND SYSTEM FOR USING ONE OR MORE ADDRESS BITS AND AN INSTRUCTION TO INCREASE AN INSTRUCTION SET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10629031
|
Filing Dt:
|
07/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR IDENTIFYING TLB ENTRIES ASSOCIATED WITH A PHYSICAL ADDRESS OF A SPECIFIED RANGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10646461
|
Filing Dt:
|
08/21/2003
|
|
Title:
|
METHOD AND SYSTEM FOR CONSERVATIVELY MANAGING STORE CAPACITY AVAILABLE TO A PROCESSOR ISSUING STORES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2010
|
Application #:
|
10672790
|
Filing Dt:
|
09/26/2003
|
|
Title:
|
SYSTEM AND METHOD OF INSTRUCTION MODIFICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10672793
|
Filing Dt:
|
09/26/2003
|
|
Title:
|
SYSTEM AND METHOD FOR MEASURING TRANSISTOR LEAKAGE CURRENT WITH A RING OSCILLATOR WITH BACKBIAS CONTROLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2010
|
Application #:
|
10672796
|
Filing Dt:
|
09/26/2003
|
|
Title:
|
SYSTEM WITH SECURE CRYPTOGRAPHIC CAPABILITIES USING A HARDWARE SPECIFIC DIGITAL SECRET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10683732
|
Filing Dt:
|
10/10/2003
|
|
Title:
|
LAYOUT PATTERNS FOR DEEP WELL REGION TO FACILITATE ROUTING BODY-BIAS VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
10683961
|
Filing Dt:
|
10/10/2003
|
|
Title:
|
METHOD AND APPARATUS FOR OPTIMIZING BODY BIAS CONNECTIONS IN CMOS CIRCUITS USING A DEEP N-WELL GRID STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2006
|
Application #:
|
10712129
|
Filing Dt:
|
11/12/2003
|
|
Title:
|
LOW RC STRUCTURES FOR ROUTING BODY-BIAS VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
10712522
|
Filing Dt:
|
11/12/2003
|
|
Title:
|
VARIABLE OUTPUT CHARGE PUMP CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2010
|
Application #:
|
10712523
|
Filing Dt:
|
11/12/2003
|
|
Title:
|
SYSTEM FOR SUBSTRATE POTENTIAL REGULATION DURING POWER-UP IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10712847
|
Filing Dt:
|
11/12/2003
|
|
Title:
|
DEVICE AGING DETERMINATION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2010
|
Application #:
|
10716320
|
Filing Dt:
|
11/17/2003
|
|
Title:
|
METHOD AND SYSTEM FOR AUTOMATICALLY CALIBRATING INTRA-CYCLE TIMING RELATIONSHIPS FOR SAMPLING SIGNALS FOR AN INTEGRATED CIRCUIT DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
10719879
|
Filing Dt:
|
11/20/2003
|
|
Title:
|
ARCHITECTURE, SYSTEM, AND METHOD FOR OPERATING ON ENCRYPTED AND /OR HIDDEN INFORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
10746539
|
Filing Dt:
|
12/23/2003
|
|
Title:
|
PRECISE CONTROL COMPONENT FOR A SUBSTRATE POTENTIAL REGULATION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
10747015
|
Filing Dt:
|
12/23/2003
|
|
Title:
|
SERVO LOOP FOR WELL BIAS VOLTAGE SOURCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2010
|
Application #:
|
10747016
|
Filing Dt:
|
12/23/2003
|
|
Title:
|
FEEDBACK-CONTROLLED BODY-BIAS VOLTAGE SOURCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10747022
|
Filing Dt:
|
12/23/2003
|
|
Title:
|
STABILIZATION COMPONENT FOR A SUBSTRATE POTENTIAL REGULATION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
10765316
|
Filing Dt:
|
01/26/2004
|
|
Title:
|
SELECTIVE COUPLING OF VOLTAGE FEEDS FOR BODY BIAS VOLTAGE IN AN INTEGRATED CIRCUIT DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
10769140
|
Filing Dt:
|
01/29/2004
|
|
Title:
|
FRACTIONAL BIASING OF SEMICONDUCTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
10771015
|
Filing Dt:
|
02/02/2004
|
|
Title:
|
SYSTEMS AND METHODS FOR ADJUSTING THRESHOLD VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2010
|
Application #:
|
10772029
|
Filing Dt:
|
02/03/2004
|
|
Title:
|
METHOD FOR GENERATING A DEEP N-WELL PATTERN FOR AN INTEGRATED CIRCUIT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2012
|
Application #:
|
10783473
|
Filing Dt:
|
02/20/2004
|
|
Title:
|
METHOD AND APPARATUS FOR ENHANCING SCHEDULING IN AN ADVANCED MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
10791099
|
Filing Dt:
|
03/01/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/01/2005
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR REDUCING TEMPERATURE VARIATION DURING BURN IN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10791241
|
Filing Dt:
|
03/01/2004
|
|
Title:
|
SYSTEM AND METHOD FOR REDUCING HEAT DISSIPATION DURING BURN-IN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2005
|
Application #:
|
10791459
|
Filing Dt:
|
03/01/2004
|
|
Title:
|
SYSTEM AND METHOD FOR CONTROLLING TEMPERATURE DURING BURN-IN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
10808225
|
Filing Dt:
|
03/23/2004
|
|
Title:
|
DEEP WELL REGIONS FOR ROUTING BODY-BIAS VOLTAGE TO MOSFETS IN SURFACE WELL REGIONS HAVING SEPARATION WELLS OF P-TYPE BETWEEN THE SEGMENTED DEEP N WELLS.
|
|
