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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:019047/0526   Pages: 6
Recorded: 03/22/2007
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 35
1
Patent #:
6530068
Issue Dt:
03/04/2003
Application #:
09366369
Filing Dt:
08/03/1999
Title:
DEVICE MODELING AND CHARACTERIZATION STRUCTURE WITH MULTIPLEXED PADS
2
Patent #:
6242790
Issue Dt:
06/05/2001
Application #:
09385550
Filing Dt:
08/30/1999
Title:
USING POLYSILICON FUSE FOR IC PROGRAMMING
3
Patent #:
6284602
Issue Dt:
09/04/2001
Application #:
09399526
Filing Dt:
09/20/1999
Title:
PROCESS TO REDUCE POST CYCLING PROGRAM VT DISPERSION FOR NAND FLASH MEMORY DEVICES
4
Patent #:
6452441
Issue Dt:
09/17/2002
Application #:
09411169
Filing Dt:
10/01/1999
Title:
LOW THRESHOLD VOLTAGE DEVICE WITH CHARGE PUMP FOR REDUCING STANDBY CURRENT IN AN INTEGRATED CIRCUIT HAVING REDUCED SUPPLY VOLTAGE
5
Patent #:
6475915
Issue Dt:
11/05/2002
Application #:
09420687
Filing Dt:
10/19/1999
Title:
ONO ETCH USING CL2/HE CHEMISTRY
6
Patent #:
6180538
Issue Dt:
01/30/2001
Application #:
09426240
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO-BIT EEPROM DEVICE USING RAPID-THERMAL-CHEMICAL-VAPOR-DEPOSITION
7
Patent #:
6207502
Issue Dt:
03/27/2001
Application #:
09426255
Filing Dt:
10/25/1999
Title:
METHOD OF USING SOURCE/DRAIN NITRIDE FOR PERIPHERY FIELD OXIDE AND BIT-LINE OXIDE
8
Patent #:
6326268
Issue Dt:
12/04/2001
Application #:
09426427
Filing Dt:
10/25/1999
Title:
METHOD OF FABRICATING A MONOS FLASH CELL USING SHALLOW TRENCH ISOLATION
9
Patent #:
6297143
Issue Dt:
10/02/2001
Application #:
09426743
Filing Dt:
10/25/1999
Title:
PROCESS FOR FORMING A BIT-LINE IN A MONOS DEVICE
10
Patent #:
6399446
Issue Dt:
06/04/2002
Application #:
09429722
Filing Dt:
10/29/1999
Title:
PROCESS FOR FABRICATING HIGH DENSITY MEMORY CELLS USING A METALLIC HARD MASK
11
Patent #:
6436766
Issue Dt:
08/20/2002
Application #:
09430493
Filing Dt:
10/29/1999
Title:
PROCESS FOR FABRICATING HIGH DENSITY MEMORY CELLS USING A POLYSILICON HARD MASK
12
Patent #:
6319775
Issue Dt:
11/20/2001
Application #:
09433037
Filing Dt:
10/25/1999
Title:
NITRIDATION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO-BIT EEPROM DEVICE
13
Patent #:
6406960
Issue Dt:
06/18/2002
Application #:
09433041
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING AN ONO STRUCTURE HAVING A SILICON-RICH SILICON NITRIDE LAYER
14
Patent #:
6458677
Issue Dt:
10/01/2002
Application #:
09433186
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING AN ONO STRUCTURE
15
Patent #:
6376308
Issue Dt:
04/23/2002
Application #:
09487073
Filing Dt:
01/19/2000
Title:
Process for fabricating an eeprom device having a pocket substrate region
16
Patent #:
6168993
Issue Dt:
01/02/2001
Application #:
09487922
Filing Dt:
01/19/2000
Title:
Process for fabricating a semiconductor device having a graded junction
17
Patent #:
6261904
Issue Dt:
07/17/2001
Application #:
09596449
Filing Dt:
06/19/2000
Title:
Dual bit isolation scheme for flash devices
18
Patent #:
6355514
Issue Dt:
03/12/2002
Application #:
09597358
Filing Dt:
06/19/2000
Title:
Dual bit isolation scheme for flash devices
19
Patent #:
6410388
Issue Dt:
06/25/2002
Application #:
09620480
Filing Dt:
07/20/2000
Title:
PROCESS FOR OPTIMIZING POCKET IMPLANT PROFILE BY RTA IMPLANT ANNEALING FOR A NON-VOLATILE SEMICONDUCTOR DEVICE
20
Patent #:
6486029
Issue Dt:
11/26/2002
Application #:
09627563
Filing Dt:
07/28/2000
Title:
INTEGRATION OF AN ION IMPLANT HARD MASK STRUCTURE INTO A PROCESS FOR FABRICATING HIGH DENSITY MEMORY CELLS
21
Patent #:
6242306
Issue Dt:
06/05/2001
Application #:
09627565
Filing Dt:
07/28/2000
Title:
Dual bit isolation scheme for flash memory devices having polysilicon floating gates
22
Patent #:
6362052
Issue Dt:
03/26/2002
Application #:
09627567
Filing Dt:
07/28/2000
Title:
Use of an etch to reduce the thickness and round the edges of a resist mask during the creation of a memory cell
23
Patent #:
6376341
Issue Dt:
04/23/2002
Application #:
09627584
Filing Dt:
07/28/2000
Title:
Optimization of thermal cycle for the formation of pocket implants
24
Patent #:
6458656
Issue Dt:
10/01/2002
Application #:
09628130
Filing Dt:
07/28/2000
Title:
PROCESS FOR CREATING A FLASH MEMORY CELL USING A PHOTORESIST FLOW OPERATION
25
Patent #:
6562683
Issue Dt:
05/13/2003
Application #:
09651704
Filing Dt:
08/31/2000
Title:
BIT-LINE OXIDATION BY REMOVING ONO OXIDE PRIOR TO BIT-LINE IMPLANT
26
Patent #:
6391730
Issue Dt:
05/21/2002
Application #:
09670229
Filing Dt:
09/25/2000
Title:
PROCESS FOR FABRICATING SHALLOW POCKET REGIONS IN A NON-VOLATILE SEMICONDUCTOR DEVICE
27
Patent #:
6366501
Issue Dt:
04/02/2002
Application #:
09686686
Filing Dt:
10/11/2000
Title:
Selective erasure of a non-volatile memory cell of a flash memory device
28
Patent #:
6349062
Issue Dt:
02/19/2002
Application #:
09686693
Filing Dt:
10/11/2000
Title:
Selective erasure of a non-volatile memory cell of a flash memory device
29
Patent #:
6537881
Issue Dt:
03/25/2003
Application #:
09688504
Filing Dt:
10/16/2000
Title:
PROCESS FOR FABRICATING A NON-VOLATILE MEMORY DEVICE
30
Patent #:
6438031
Issue Dt:
08/20/2002
Application #:
09697815
Filing Dt:
10/26/2000
Title:
METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A SUBSTRATE BIAS
31
Patent #:
7012008
Issue Dt:
03/14/2006
Application #:
09728554
Filing Dt:
12/01/2000
Title:
DUAL SPACER PROCESS FOR NON-VOLATILE MEMORY DEVICES
32
Patent #:
6627526
Issue Dt:
09/30/2003
Application #:
09805287
Filing Dt:
03/13/2001
Title:
METHOD FOR FABRICATING A CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR DEVICE
33
Patent #:
6680507
Issue Dt:
01/20/2004
Application #:
09833307
Filing Dt:
04/11/2001
Publication #:
US20020048881
Pub Dt:
04/25/2002
Title:
DUAL BIT ISOLATION SCHEME FOR FLASH MEMORY DEVICES HAVING POLYSILICON FLOATING GATES
34
Patent #:
6459618
Issue Dt:
10/01/2002
Application #:
09880367
Filing Dt:
06/13/2001
Title:
METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A DRAIN BIAS
35
Patent #:
6573151
Issue Dt:
06/03/2003
Application #:
09884204
Filing Dt:
06/19/2001
Title:
METHOD OF FORMING ZERO MARKS
Assignor
1
ADVANCED MICRO DEVICES, INC.
Exec Dt:
01/31/2007
Assignee
1
SPANSION INC.
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CALIFORNIA 94088-3453
Correspondence name and address
RAYMOND E. FRITZ
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CA 94088-3453

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