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Reel/Frame:	023788/0535			Pages:	389
		Recorded:	01/14/2010
Attorney Dkt #:	609612800100
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 122
Page 1 of 2
Pages: 1 2

Patent #:	6870263	Issue Dt:	03/22/2005	Application #:	09052688	Filing Dt:	03/31/1998
Title:	DEVICE INTERCONNECTION

Patent #:	6262615	Issue Dt:	07/17/2001	Application #:	09257304	Filing Dt:	02/25/1999
Title:	DYNAMIC LOGIC CIRCUIT

Patent #:	6668031	Issue Dt:	12/23/2003	Application #:	09377588	Filing Dt:	08/19/1999
Title:	SYNCHRONIZED DATA CAPTURING CIRCUITS USING REDUCED VOLTAGE LEVELS AND METHODS THEREFOR

Patent #:	6548414	Issue Dt:	04/15/2003	Application #:	09396178	Filing Dt:	09/14/1999
Publication #:	US20010053610	Pub Dt:	12/20/2001
Title:	METHOD OF PLASMA ETCHING THIN FILMS OF DIFFICULT TO DRY ETCH MATERIALS

Patent #:	6265279	Issue Dt:	07/24/2001	Application #:	09404906	Filing Dt:	09/24/1999
Title:	METHOD FOR FABRICATING A TRENCH CAPACITOR

Patent #:	6740555	Issue Dt:	05/25/2004	Application #:	09408248	Filing Dt:	09/29/1999
Title:	SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS

Patent #:	6529054	Issue Dt:	03/04/2003	Application #:	09425329	Filing Dt:	10/22/1999
Title:	PREFETCH ARCHITECTURES FOR DATA AND TIME SIGNALS IN AN INTEGRATED CIRCUIT AND METHODS THEREFOR

Patent #:	6404264	Issue Dt:	06/11/2002	Application #:	09455118	Filing Dt:	12/06/1999
Publication #:	US20020000867	Pub Dt:	01/03/2002
Title:	FUSE LATCH HAVING MULTIPLEXERS WITH REDUCED SIZES AND LOWER POWER CONSUMPTION

Patent #:	6294470	Issue Dt:	09/25/2001	Application #:	09469922	Filing Dt:	12/22/1999
Title:	SLURRY-LESS CHEMICAL-MECHANICAL POLISHING

Patent #:	6218279	Issue Dt:	04/17/2001	Application #:	09512648	Filing Dt:	02/24/2000
Title:	Vertical fuse and method of fabrication

Patent #:	6399434	Issue Dt:	06/04/2002	Application #:	09559880	Filing Dt:	04/26/2000
Title:	DOPED STRUCTURES CONTAINING DIFFUSION BARRIERS

Patent #:	6353248	Issue Dt:	03/05/2002	Application #:	09562220	Filing Dt:	04/28/2000
Title:	Optimized decoupling capacitor using lithographic dummy filler

Patent #:	6348394	Issue Dt:	02/19/2002	Application #:	09573375	Filing Dt:	05/18/2000
Title:	Method and device for array threshold voltage control by trapped charge in trench isolation

Patent #:	6521493	Issue Dt:	02/18/2003	Application #:	09574891	Filing Dt:	05/19/2000
Title:	SEMICONDUCTOR DEVICE WITH STI SIDEWALL IMPLANT

Patent #:	6521542	Issue Dt:	02/18/2003	Application #:	09593739	Filing Dt:	06/14/2000
Title:	METHOD FOR FORMING DUAL DAMASCENE STRUCTURE

Patent #:	6605860	Issue Dt:	08/12/2003	Application #:	09597442	Filing Dt:	06/20/2000
Title:	SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS

Patent #:	6555862	Issue Dt:	04/29/2003	Application #:	09670745	Filing Dt:	09/27/2000
Title:	SELF-ALIGNED BURIED STRAP FOR VERTICAL TRANSISTORS

Patent #:	6369606	Issue Dt:	04/09/2002	Application #:	09670945	Filing Dt:	09/27/2000
Title:	Mixed threshold voltage CMOS logic device and method of manufacture therefor

Patent #:	6509624	Issue Dt:	01/21/2003	Application #:	09675246	Filing Dt:	09/29/2000
Title:	SEMICONDUCTOR FUSES AND ANTIFUSES IN VERTICAL DRAMS

Patent #:	6794242	Issue Dt:	09/21/2004	Application #:	09675435	Filing Dt:	09/29/2000
Title:	EXTENDIBLE PROCESS FOR IMPROVED TOP OXIDE LAYER FOR DRAM ARRAY AND THE GATE INTERCONNECTS WHILE PROVIDING SELF-ALIGNED GATE CONTACTS

Patent #:	6426658	Issue Dt:	07/30/2002	Application #:	09676864	Filing Dt:	09/29/2000
Title:	BUFFERS WITH REDUCED VOLTAGE INPUT/OUTPUT SIGNALS

Patent #:	6569769	Issue Dt:	05/27/2003	Application #:	09702311	Filing Dt:	10/31/2000
Title:	SLURRY-LESS CHEMICAL-MECHANICAL POLISHING

Patent #:	6261972	Issue Dt:	07/17/2001	Application #:	09706641	Filing Dt:	11/06/2000
Title:	Dual gate oxide process for uniform oxide thickness

Patent #:	6403423	Issue Dt:	06/11/2002	Application #:	09713272	Filing Dt:	11/15/2000
Title:	MODIFIED GATE PROCESSING FOR OPTIMIZED DEFINITION OF ARRAY AND LOGIC DEVICES ON SAME CHIP

Patent #:	6350692	Issue Dt:	02/26/2002	Application #:	09737198	Filing Dt:	12/14/2000
Title:	Increased polish removal rate of dielectric layers using fixed abrasive pads

Patent #:	6821900	Issue Dt:	11/23/2004	Application #:	09757123	Filing Dt:	01/09/2001
Publication #:	US20020094690	Pub Dt:	07/18/2002
Title:	METHOD FOR DRY ETCHING DEEP TRENCHES IN A SUBSTRATE

Patent #:	6440793	Issue Dt:	08/27/2002	Application #:	09757514	Filing Dt:	01/10/2001
Publication #:	US20020090780	Pub Dt:	07/11/2002
Title:	VERTICAL MOSFET

Patent #:	6335652	Issue Dt:	01/01/2002	Application #:	09764816	Filing Dt:	01/18/2001
Publication #:	US20010002112	Pub Dt:	05/31/2001
Title:	Method and apparatus for the replacement of non-operational metal lines in DRAMS

Patent #:	6686668	Issue Dt:	02/03/2004	Application #:	09764833	Filing Dt:	01/17/2001
Publication #:	US20020093112	Pub Dt:	07/18/2002
Title:	STRUCTURE AND METHOD OF FORMING BITLINE CONTACTS FOR A VERTICAL DRAM ARRAY USING A LINE BITLINE CONTACT MASK

Patent #:	6495901	Issue Dt:	12/17/2002	Application #:	09772377	Filing Dt:	01/30/2001
Publication #:	US20020100956	Pub Dt:	08/01/2002
Title:	MULTI-LEVEL FUSE STRUCTURE

Patent #:	6370055	Issue Dt:	04/09/2002	Application #:	09795761	Filing Dt:	02/28/2001
Title:	SEMICONDUCTOR MEMORY HAVING ASYMMETRIC COLUMN ADDRESSING AND TWISTED READ WRITE DRIVE (RWD) LINE ARCHITECTURE

Patent #:	6809368	Issue Dt:	10/26/2004	Application #:	09832605	Filing Dt:	04/11/2001
Publication #:	US20020149047	Pub Dt:	10/17/2002
Title:	TTO NITRIDE LINER FOR IMPROVED COLLAR PROTECTION AND TTO RELIABILITY

Patent #:	6518616	Issue Dt:	02/11/2003	Application #:	09837799	Filing Dt:	04/18/2001
Publication #:	US20020155654	Pub Dt:	10/24/2002
Title:	VERTICAL GATE TOP ENGINEERING FOR IMPROVED GC AND CB PROCESS WINDOWS

Patent #:	6753252	Issue Dt:	06/22/2004	Application #:	09861253	Filing Dt:	05/18/2001
Publication #:	US20020173094	Pub Dt:	11/21/2002
Title:	CONTACT PLUG FORMATION FOR DEVICES WITH STACKED CAPACITORS

Patent #:	6437388	Issue Dt:	08/20/2002	Application #:	09866278	Filing Dt:	05/25/2001
Title:	COMPACT TRENCH CAPACITOR MEMORY CELL WITH BODY CONTACT

Patent #:	6743727	Issue Dt:	06/01/2004	Application #:	09874109	Filing Dt:	06/05/2001
Publication #:	US20020179570	Pub Dt:	12/05/2002
Title:	METHOD OF ETCHING HIGH ASPECT RATIO OPENINGS

Patent #:	6429068	Issue Dt:	08/06/2002	Application #:	09897868	Filing Dt:	07/02/2001
Title:	STRUCTURE AND METHOD OF FABRICATING EMBEDDED VERTICAL DRAM ARRAYS WITH SILICIDED BITLINE AND POLYSILICON INTERCONNECT

Patent #:	6570256	Issue Dt:	05/27/2003	Application #:	09910380	Filing Dt:	07/20/2001
Publication #:	US20030017642	Pub Dt:	01/23/2003
Title:	CARBON-GRADED LAYER FOR IMPROVED ADHESION OF LOW-K DIELECTRICS TO SILICON SUBSTRATES

Patent #:	6528855	Issue Dt:	03/04/2003	Application #:	09911894	Filing Dt:	07/24/2001
Publication #:	US20030020120	Pub Dt:	01/30/2003
Title:	MOSFET HAVING A LOW ASPECT RATIO BETWEEN THE GATE AND THE SOURCE/DRAIN

Patent #:	6606151	Issue Dt:	08/12/2003	Application #:	09916917	Filing Dt:	07/27/2001
Publication #:	US20030020901	Pub Dt:	01/30/2003
Title:	GRATING PATTERNS AND METHOD FOR DETERMINATION OF AZIMUTHAL AND RADIAL ABERRATION

Patent #:	6531412	Issue Dt:	03/11/2003	Application #:	09928209	Filing Dt:	08/10/2001
Publication #:	US20030032306	Pub Dt:	02/13/2003
Title:	METHOD FOR LOW TEMPERATURE CHEMICAL VAPOR DEPOSITION OF LOW-K FILMS USING SELECTED CYCLOSILOXANE AND OZONE GASES FOR SEMICONDUCTOR APPLICATIONS

Patent #:	6580655	Issue Dt:	06/17/2003	Application #:	09941911	Filing Dt:	08/29/2001
Publication #:	US20030043666	Pub Dt:	03/06/2003
Title:	PRE-CHARGE CIRCUIT AND METHOD FOR MEMORY DEVICES WITH SHARED SENSE AMPLIFIERS

Patent #:	6566219	Issue Dt:	05/20/2003	Application #:	09957937	Filing Dt:	09/21/2001
Publication #:	US20020068400	Pub Dt:	06/06/2002
Title:	METHOD OF FORMING A SELF ALIGNED TRENCH IN A SEMICONDUCTOR USING A PATTERNED SACRIFICIAL LAYER FOR DEFINING THE TRENCH OPENING

Patent #:	6680857	Issue Dt:	01/20/2004	Application #:	09964208	Filing Dt:	09/26/2001
Publication #:	US20030058028	Pub Dt:	03/27/2003
Title:	UNIT-ARCHITECTURE WITH IMPLEMENTED LIMITED BANK-COLUMN-SELECT REPAIRABILITY

Patent #:	6734097	Issue Dt:	05/11/2004	Application #:	09965094	Filing Dt:	09/28/2001
Publication #:	US20030068894	Pub Dt:	04/10/2003
Title:	LINER WITH POOR STEP COVERAGE TO IMPROVE CONTACT RESISTANCE IN W CONTACTS

Patent #:	6656798	Issue Dt:	12/02/2003	Application #:	09965919	Filing Dt:	09/28/2001
Publication #:	US20030067035	Pub Dt:	04/10/2003
Title:	GATE PROCESSING METHOD WITH REDUCED GATE OXIDE CORNER AND EDGE THINNING

Patent #:	6432725	Issue Dt:	08/13/2002	Application #:	09966496	Filing Dt:	09/28/2001
Title:	METHODS FOR CRYSTALLIZING METALLIC OXIDE DIELECTRIC FILMS AT LOW TEMPERATURE

Patent #:	6596580	Issue Dt:	07/22/2003	Application #:	09982574	Filing Dt:	10/18/2001
Publication #:	US20030077858	Pub Dt:	04/24/2003
Title:	RECESS PT STRUCTURE FOR HIGH K STACKED CAPACITOR IN DRAM AND FRAM, AND THE METHOD TO FORM THIS STRUCTURE

Patent #:	6649531	Issue Dt:	11/18/2003	Application #:	09994340	Filing Dt:	11/26/2001
Publication #:	US20030100190	Pub Dt:	05/29/2003
Title:	PROCESS FOR FORMING A DAMASCENE STRUCTURE

Patent #:	6630379	Issue Dt:	10/07/2003	Application #:	10011556	Filing Dt:	11/06/2001
Publication #:	US20020085434	Pub Dt:	07/04/2002
Title:	METHOD OF MANUFACTURING 6F2 TRENCH CAPACITOR DRAM CELL HAVING VERTICAL MOSFET AND 3F BITLINE PITCH

Patent #:	6613642	Issue Dt:	09/02/2003	Application #:	10016075	Filing Dt:	12/13/2001
Publication #:	US20030114005	Pub Dt:	06/19/2003
Title:	METHOD FOR SURFACE ROUGHNESS ENHANCEMENT IN SEMICONDUCTOR CAPACITOR MANUFACTURING

Patent #:	6566228	Issue Dt:	05/20/2003	Application #:	10083744	Filing Dt:	02/26/2002
Title:	TRENCH ISOLATION PROCESSES USING POLYSILICON-ASSISTED FILL

Patent #:	6667633	Issue Dt:	12/23/2003	Application #:	10093784	Filing Dt:	03/07/2002
Publication #:	US20030169069	Pub Dt:	09/11/2003
Title:	MULTIPLE FINGER OFF CHIP DRIVER (OCD) WITH SINGLE LEVEL TRANSLATOR

Patent #:	6821864	Issue Dt:	11/23/2004	Application #:	10093789	Filing Dt:	03/07/2002
Publication #:	US20030170951	Pub Dt:	09/11/2003
Title:	NOVEL METHOD TO ACHIEVE INCREASED TRENCH DEPTH, INDEPENDENT OF CD AS DEFINED BY LITHOGRAPHY

Patent #:	6740920	Issue Dt:	05/25/2004	Application #:	10096219	Filing Dt:	03/11/2002
Publication #:	US20030168687	Pub Dt:	09/11/2003
Title:	VERTICAL MOSFET WITH HORIZONTALLY GRADED CHANNEL DOPING

Patent #:	6690198	Issue Dt:	02/10/2004	Application #:	10114195	Filing Dt:	04/02/2002
Publication #:	US20030184342	Pub Dt:	10/02/2003
Title:	REPEATER WITH REDUCED POWER CONSUMPTION

Patent #:	6683486	Issue Dt:	01/27/2004	Application #:	10114221	Filing Dt:	04/02/2002
Publication #:	US20030184358	Pub Dt:	10/02/2003
Title:	LOW VOLTAGE LEVEL SHIFTER WITH LATCHING FUNCTION

Patent #:	6620724	Issue Dt:	09/16/2003	Application #:	10142518	Filing Dt:	05/09/2002
Title:	LOW RESISTIVITY DEEP TRENCH FILL FOR DRAM AND EDRAM APPLICATIONS

Patent #:	6740568	Issue Dt:	05/25/2004	Application #:	10206875	Filing Dt:	07/29/2002
Publication #:	US20040018680	Pub Dt:	01/29/2004
Title:	METHOD TO ENHANCE EPI-REGROWTH IN AMORPHOUS POLY CB CONTACTS

Patent #:	6960306	Issue Dt:	11/01/2005	Application #:	10207773	Filing Dt:	07/31/2002
Publication #:	US20040020891	Pub Dt:	02/05/2004
Title:	LOW CU PERCENTAGES FOR REDUCING SHORTS IN ALCU LINES

Patent #:	6723611	Issue Dt:	04/20/2004	Application #:	10241225	Filing Dt:	09/10/2002
Publication #:	US20040048441	Pub Dt:	03/11/2004
Title:	VERTICAL HARD MASK

Patent #:	6927569	Issue Dt:	08/09/2005	Application #:	10244766	Filing Dt:	09/16/2002
Publication #:	US20040051522	Pub Dt:	03/18/2004
Title:	TECHNIQUES FOR ELECTRICALLY CHARACTERIZING TUNNEL JUNCTION FILM STACKS WITH LITTLE OR NO PROCESSING

Patent #:	6960532	Issue Dt:	11/01/2005	Application #:	10248911	Filing Dt:	02/28/2003
Publication #:	US20040171267	Pub Dt:	09/02/2004
Title:	SUPPRESSING LITHOGRAPHY AT A WAFER EDGE

Patent #:	7135255	Issue Dt:	11/14/2006	Application #:	10249317	Filing Dt:	03/31/2003
Publication #:	US20040191638	Pub Dt:	09/30/2004
Title:	LAYOUT IMPACT REDUCTION WITH ANGLED PHASE SHAPES

Patent #:	6784091	Issue Dt:	08/31/2004	Application #:	10250133	Filing Dt:	06/05/2003
Title:	MASKLESS ARRAY PROTECTION PROCESS FLOW FOR FORMING INTERCONNECT VIAS IN MAGNETIC RANDOM ACCESS MEMORY DEVICES

Patent #:	6727142	Issue Dt:	04/27/2004	Application #:	10284508	Filing Dt:	10/29/2002
Publication #:	US20040082197	Pub Dt:	04/29/2004
Title:	ORIENTATION INDEPENDENT OXIDATION OF NITRIDED SILICON

Patent #:	7091103	Issue Dt:	08/15/2006	Application #:	10314865	Filing Dt:	12/09/2002
Publication #:	US20040110380	Pub Dt:	06/10/2004
Title:	TEOS ASSISTED OXIDE CMP PROCESS

Patent #:	6703274	Issue Dt:	03/09/2004	Application #:	10336988	Filing Dt:	01/03/2003
Title:	BURIED STRAP WITH LIMITED OUTDIFFUSION AND VERTICAL TRANSISTOR DRAM

Patent #:	6867472	Issue Dt:	03/15/2005	Application #:	10338517	Filing Dt:	01/08/2003
Publication #:	US20040142500	Pub Dt:	07/22/2004
Title:	REDUCED HOT CARRIER INDUCED PARASITIC SIDEWALL DEVICE ACTIVATION IN ISOLATED BURIED CHANNEL DEVICES BY CONDUCTIVE BURIED CHANNEL DEPTH OPTIMIZATION

Patent #:	6884630	Issue Dt:	04/26/2005	Application #:	10348235	Filing Dt:	01/21/2003
Publication #:	US20040087039	Pub Dt:	05/06/2004
Title:	TWO-STEP MAGNETIC TUNNEL JUNCTION STACK DEPOSITION

Patent #:	6740539	Issue Dt:	05/25/2004	Application #:	10366149	Filing Dt:	02/13/2003
Publication #:	US20030153198	Pub Dt:	08/14/2003
Title:	CARBON-GRADED LAYER FOR IMPROVED ADHESION OF LOW-K DIELECTRICS TO SILICON SUBSTRATES

Patent #:	6809005	Issue Dt:	10/26/2004	Application #:	10386880	Filing Dt:	03/12/2003
Publication #:	US20040180510	Pub Dt:	09/16/2004
Title:	METHOD TO FILL DEEP TRENCH STRUCTURES WITH VOID-FREE POLYSILICON OR SILICON

Patent #:	6890833	Issue Dt:	05/10/2005	Application #:	10397761	Filing Dt:	03/26/2003
Publication #:	US20040192009	Pub Dt:	09/30/2004
Title:	TRENCH ISOLATION EMPLOYING A DOPED OXIDE TRENCH FILL

Patent #:	6960523	Issue Dt:	11/01/2005	Application #:	10406645	Filing Dt:	04/03/2003
Publication #:	US20040195607	Pub Dt:	10/07/2004
Title:	METHOD OF REDUCING EROSION OF A NITRIDE GATE CAP LAYER DURING REACTIVE ION ETCH OF NITRIDE LINER LAYER FOR BIT LINE CONTACT OF DRAM DEVICE

Patent #:	6842222	Issue Dt:	01/11/2005	Application #:	10406888	Filing Dt:	04/04/2003
Publication #:	US20040196445	Pub Dt:	10/07/2004
Title:	METHOD OF REDUCING PITCH ON SEMICONDUCTOR WAFER

Patent #:	7270884	Issue Dt:	09/18/2007	Application #:	10408339	Filing Dt:	04/07/2003
Publication #:	US20040197576	Pub Dt:	10/07/2004
Title:	ADHESION LAYER FOR PT ON SIO2

Patent #:	7074525	Issue Dt:	07/11/2006	Application #:	10425817	Filing Dt:	04/29/2003
Publication #:	US20040219435	Pub Dt:	11/04/2004
Title:	CRITICAL DIMENSION CONTROL OF PRINTED FEATURES USING NON-PRINTING FILL PATTERNS

Patent #:	6813181	Issue Dt:	11/02/2004	Application #:	10445550	Filing Dt:	05/27/2003
Title:	CIRCUIT CONFIGURATION FOR A CURRENT SWITCH OF A BIT/WORD LINE OF A MRAM DEVICE

Patent #:	6882027	Issue Dt:	04/19/2005	Application #:	10447018	Filing Dt:	05/28/2003
Publication #:	US20040238919	Pub Dt:	12/02/2004
Title:	METHODS AND APPARATUS FOR PROVIDING AN ANTIFUSE FUNCTION

Patent #:	6974770	Issue Dt:	12/13/2005	Application #:	10600034	Filing Dt:	06/20/2003
Publication #:	US20040259358	Pub Dt:	12/23/2004
Title:	SELF-ALIGNED MASK TO REDUCE CELL LAYOUT AREA

Patent #:	NONE	Issue Dt:		Application #:	10604112	Filing Dt:	06/26/2003
Publication #:	US20050009312	Pub Dt:	01/13/2005
Title:	GATE LENGTH PROXIMITY CORRECTED DEVICE

Patent #:	NONE	Issue Dt:		Application #:	10604488	Filing Dt:	07/25/2003
Publication #:	US20050017282	Pub Dt:	01/27/2005
Title:	DRAM BURIED STRAP PROCESS WITH SILICON CARBIDE

Patent #:	6940583	Issue Dt:	09/06/2005	Application #:	10604519	Filing Dt:	07/28/2003
Publication #:	US20050024618	Pub Dt:	02/03/2005
Title:	METHOD AND APPARATUS FOR AMPLITUDE FILTERING IN THE FREQUENCY PLANE OF A LITHOGRAPHIC PROJECTION SYSTEM

Patent #:	7183130	Issue Dt:	02/27/2007	Application #:	10604533	Filing Dt:	07/29/2003
Publication #:	US20050023581	Pub Dt:	02/03/2005
Title:	MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF FABRICATING THEREOF

Patent #:	6838334	Issue Dt:	01/04/2005	Application #:	10604562	Filing Dt:	07/30/2003
Title:	METHOD OF FABRICATING A BURIED COLLAR

Patent #:	6930004	Issue Dt:	08/16/2005	Application #:	10604731	Filing Dt:	08/13/2003
Publication #:	US20050037561	Pub Dt:	02/17/2005
Title:	SELF-ALIGNED DRAIN/CHANNEL JUNCTION IN VERTICAL PASS TRANSISTOR DRAM CELL DESIGN FOR DEVICE SCALING

Patent #:	NONE	Issue Dt:		Application #:	10605087	Filing Dt:	09/08/2003
Publication #:	US20050054158	Pub Dt:	03/10/2005
Title:	BULK CONTACT MASK PROCESS

Patent #:	6972266	Issue Dt:	12/06/2005	Application #:	10605438	Filing Dt:	09/30/2003
Publication #:	US20050070108	Pub Dt:	03/31/2005
Title:	TOP OXIDE NITRIDE LINER INTEGRATION SCHEME FOR VERTICAL DRAM

Patent #:	6870211	Issue Dt:	03/22/2005	Application #:	10605590	Filing Dt:	10/10/2003
Publication #:	US20050077562	Pub Dt:	04/14/2005
Title:	SELF-ALIGNED ARRAY CONTACT FOR MEMORY CELLS

Patent #:	7243276	Issue Dt:	07/10/2007	Application #:	10605927	Filing Dt:	11/06/2003
Publication #:	US20050102590	Pub Dt:	05/12/2005
Title:	METHOD FOR PERFORMING A BURN-IN TEST

Patent #:	6812141	Issue Dt:	11/02/2004	Application #:	10610609	Filing Dt:	07/01/2003
Title:	RECESSED METAL LINES FOR PROTECTIVE ENCLOSURE IN INTEGRATED CIRCUITS

Patent #:	6890815	Issue Dt:	05/10/2005	Application #:	10655199	Filing Dt:	09/04/2003
Publication #:	US20050051839	Pub Dt:	03/10/2005
Title:	REDUCED CAP LAYER EROSION FOR BORDERLESS CONTACTS

Patent #:	6972613	Issue Dt:	12/06/2005	Application #:	10657362	Filing Dt:	09/08/2003
Publication #:	US20050052218	Pub Dt:	03/10/2005
Title:	FUSE LATCH CIRCUIT WITH NON-DISRUPTIVE RE-INTERROGATION

Patent #:	6984529	Issue Dt:	01/10/2006	Application #:	10659136	Filing Dt:	09/10/2003
Publication #:	US20050051820	Pub Dt:	03/10/2005
Title:	FABRICATION PROCESS FOR A MAGNETIC TUNNEL JUNCTION DEVICE

Patent #:	6982902	Issue Dt:	01/03/2006	Application #:	10679160	Filing Dt:	10/03/2003
Publication #:	US20050073879	Pub Dt:	04/07/2005
Title:	MRAM ARRAY HAVING A SEGMENTED BIT LINE

Patent #:	7270130	Issue Dt:	09/18/2007	Application #:	10685684	Filing Dt:	10/15/2003
Publication #:	US20050081884	Pub Dt:	04/21/2005
Title:	SEMICONDUCTOR DEVICE CLEANING EMPLOYING HETEROGENEOUS NUCLEATION FOR CONTROLLED CAVITATION

Patent #:	7125790	Issue Dt:	10/24/2006	Application #:	10689233	Filing Dt:	10/20/2003
Publication #:	US20050085096	Pub Dt:	04/21/2005
Title:	INCLUSION OF LOW-K DIELECTRIC MATERIAL BETWEEN BIT LINES

Patent #:	7473656	Issue Dt:	01/06/2009	Application #:	10690538	Filing Dt:	10/23/2003
Publication #:	US20050087519	Pub Dt:	04/28/2005
Title:	METHOD FOR FAST AND LOCAL ANNEAL OF ANTI-FERROMAGNETIC (AF) EXCHANGE-BIASED MAGNETIC STACKS

Patent #:	6998666	Issue Dt:	02/14/2006	Application #:	10707754	Filing Dt:	01/09/2004
Publication #:	US20050151181	Pub Dt:	07/14/2005
Title:	NITRIDED STI LINER OXIDE FOR REDUCED CORNER DEVICE IMPACT ON VERTICAL DEVICE PERFORMANCE

100

Patent #:	NONE	Issue Dt:		Application #:	10708035	Filing Dt:	02/04/2004
Publication #:	US20050170661	Pub Dt:	08/04/2005
Title:	Method of forming a trench structure

Assignor

INFINEON TECHNOLOGIES AG

Exec Dt:

04/25/2006

Assignee

QIMONDA AG

GUSTAV-HEINEMANN-RING 212

MUNICH, GERMANY 81739

Correspondence name and address
	JONATHAN BOCKMAN
	C/O MORRISON & FOERSTER LLP
	1650 TYSONS BOULEVARD SUITE 400
	MCLEAN, VA 22102

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