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Patent Assignment Details
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Reel/Frame:027102/0539   Pages: 5
Recorded: 10/21/2011
Attorney Dkt #:PATACQ
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 24
1
Patent #:
6081904
Issue Dt:
06/27/2000
Application #:
09070360
Filing Dt:
04/30/1998
Title:
METHOD FOR INSURING DATA INTEGRITY DURING TRANSFERS
2
Patent #:
6467032
Issue Dt:
10/15/2002
Application #:
09325817
Filing Dt:
06/04/1999
Title:
CONTROLLED REISSUE DELAY OF MEMORY REQUESTS TO REDUCE SHARED MEMORY ADDRESS CONTENTION
3
Patent #:
6463530
Issue Dt:
10/08/2002
Application #:
09329457
Filing Dt:
06/10/1999
Title:
METHOD AND APPARATUS FOR REMOTELY BOOTING A CLIENT COMPUTER FROM A NETWORK BY EMULATING REMOTE BOOT CHIPS
4
Patent #:
6725354
Issue Dt:
04/20/2004
Application #:
09594631
Filing Dt:
06/15/2000
Title:
SHARED EXECUTION UNIT IN A DUAL CORE PROCESSOR
5
Patent #:
6635909
Issue Dt:
10/21/2003
Application #:
10101807
Filing Dt:
03/19/2002
Publication #:
US20030178677
Pub Dt:
09/25/2003
Title:
STRAINED FIN FETS STRUCTURE AND METHOD
6
Patent #:
6794718
Issue Dt:
09/21/2004
Application #:
10248123
Filing Dt:
12/19/2002
Publication #:
US20040119100
Pub Dt:
06/24/2004
Title:
DENSE DUAL-PLANE DEVICES
7
Patent #:
6934181
Issue Dt:
08/23/2005
Application #:
10361200
Filing Dt:
02/06/2003
Publication #:
US20040156227
Pub Dt:
08/12/2004
Title:
REDUCING SUB-THRESHOLD LEAKAGE IN A MEMORY ARRAY
8
Patent #:
6767793
Issue Dt:
07/27/2004
Application #:
10405844
Filing Dt:
04/02/2003
Publication #:
US20030178681
Pub Dt:
09/25/2003
Title:
STRAINED FIN FETS STRUCTURE AND METHOD
9
Patent #:
6977519
Issue Dt:
12/20/2005
Application #:
10437764
Filing Dt:
05/14/2003
Publication #:
US20040227542
Pub Dt:
11/18/2004
Title:
DIGITAL LOGIC WITH REDUCED LEAKAGE
10
Patent #:
6849884
Issue Dt:
02/01/2005
Application #:
10439886
Filing Dt:
05/16/2003
Publication #:
US20030201458
Pub Dt:
10/30/2003
Title:
STRAINED FIN FETS STRUCTURE AND METHOD
11
Patent #:
7353362
Issue Dt:
04/01/2008
Application #:
10604491
Filing Dt:
07/25/2003
Publication #:
US20050021871
Pub Dt:
01/27/2005
Title:
MULTIPROCESSOR SUBSYSTEM IN SOC WITH BRIDGE BETWEEN PROCESSOR CLUSTERS INTERCONNECTION AND SOC SYSTEM BUS
12
Patent #:
6921982
Issue Dt:
07/26/2005
Application #:
10626760
Filing Dt:
07/21/2003
Publication #:
US20050017377
Pub Dt:
01/27/2005
Title:
FET CHANNEL HAVING A STRAINED LATTICE STRUCTURE ALONG MULTIPLE SURFACES
13
Patent #:
7105934
Issue Dt:
09/12/2006
Application #:
10711170
Filing Dt:
08/30/2004
Publication #:
US20060043616
Pub Dt:
03/02/2006
Title:
FINFET WITH LOW GATE CAPACITANCE AND LOW EXTRINSIC RESISTANCE
14
Patent #:
7412588
Issue Dt:
08/12/2008
Application #:
10768828
Filing Dt:
01/30/2004
Publication #:
US20050021874
Pub Dt:
01/27/2005
Title:
NETWORK PROCESSOR SYSTEM ON CHIP WITH BRIDGE COUPLING PROTOCOL CONVERTING MULTIPROCESSOR MACRO CORE LOCAL BUS TO PERIPHERAL INTERFACES COUPLED SYSTEM BUS
15
Patent #:
7237105
Issue Dt:
06/26/2007
Application #:
10841902
Filing Dt:
05/07/2004
Publication #:
US20040250057
Pub Dt:
12/09/2004
Title:
STARTUP SYSTEM AND METHOD USING BOOT CODE
16
Patent #:
7291886
Issue Dt:
11/06/2007
Application #:
10872605
Filing Dt:
06/21/2004
Publication #:
US20050280121
Pub Dt:
12/22/2005
Title:
HYBRID SUBSTRATE TECHNOLOGY FOR HIGH-MOBILITY PLANAR AND MULTIPLE-GATE MOSFETS
17
Patent #:
7087952
Issue Dt:
08/08/2006
Application #:
10978951
Filing Dt:
11/01/2004
Publication #:
US20060091450
Pub Dt:
05/04/2006
Title:
DUAL FUNCTION FINFET, FINMEMORY AND METHOD OF MANUFACTURE
18
Patent #:
7198990
Issue Dt:
04/03/2007
Application #:
11137811
Filing Dt:
05/24/2005
Publication #:
US20050218427
Pub Dt:
10/06/2005
Title:
METHOD FOR MAKING A FET CHANNEL
19
Patent #:
NONE
Issue Dt:
Application #:
11621290
Filing Dt:
01/09/2007
Publication #:
US20070111406
Pub Dt:
05/17/2007
Title:
FET Channel Having a Strained Lattice Structure Along Multiple Surfaces
20
Patent #:
7917729
Issue Dt:
03/29/2011
Application #:
11757166
Filing Dt:
06/01/2007
Publication #:
US20070239966
Pub Dt:
10/11/2007
Title:
SYSTEM ON CHIP IC WITH SUBSYSTEM OF MULTIPLE PROCESSING CORES SWITCH COUPLED TO NETWORK PROTOCOL DEVICE AND BUS BRIDGE TO LOCAL SYSTEM BUS
21
Patent #:
7485506
Issue Dt:
02/03/2009
Application #:
11866786
Filing Dt:
10/03/2007
Publication #:
US20080020521
Pub Dt:
01/24/2008
Title:
HYBRID SUBSTRATE TECHNOLOGY FOR HIGH-MOBILITY PLANAR AND MULTIPLE-GATE MOSFETS
22
Patent #:
NONE
Issue Dt:
Application #:
11969992
Filing Dt:
01/07/2008
Publication #:
US20080105898
Pub Dt:
05/08/2008
Title:
FET Channel Having a Strained Lattice Structure Along Multiple Surfaces
23
Patent #:
NONE
Issue Dt:
Application #:
11970011
Filing Dt:
01/07/2008
Publication #:
US20080105900
Pub Dt:
05/08/2008
Title:
FET Channel Having a Strained Lattice Structure Along Multiple Surfaces
24
Patent #:
8036243
Issue Dt:
10/11/2011
Application #:
12189675
Filing Dt:
08/11/2008
Publication #:
US20090059955
Pub Dt:
03/05/2009
Title:
SINGLE CHIP PROTOCOL CONVERTER
Assignor
1
INTERNATIONAL BUSINESS MACHINES CORPORATION
Exec Dt:
09/30/2011
Assignee
1
MICROSOFT CORPORATION
ONE MICROSOFT WAY
REDMOND, WASHINGTON 98052
Correspondence name and address
ERIC MATT
ONE MICROSOFT WAY
REDMOND, WA 98052

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