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Total properties:
35
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09861031
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Filing Dt:
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05/18/2001
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Title:
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METHOD OF CHANNEL HOT ELECTRON PROGRAMMING FOR SHORT CHANNEL NOR FLASH ARRAYS
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09892685
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Filing Dt:
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06/27/2001
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Title:
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HIGH DENSITY FLASH EEPROM ARRAY WITH SOURCE SIDE INJECTION
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09904736
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Filing Dt:
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07/13/2001
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Title:
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DETERMINATION OF DIELECTRIC CONSTANTS OF THIN DIELECTRIC MATERIALS IN A MOS (METAL OXIDE SEMICONDUCTOR) STACK
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09917178
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Filing Dt:
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07/30/2001
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Title:
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NOR ARRAY WITH BURIED TRENCH SOURCE LINE
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09917182
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Filing Dt:
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07/30/2001
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Publication #:
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Pub Dt:
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01/30/2003
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Title:
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LOW DEFECT DENSITY PROCESS FOR DEEP SUB-0.18UM FLASH MEMORY TECHNOLOGIES
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Patent #:
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Issue Dt:
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05/03/2005
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Application #:
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09917440
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Filing Dt:
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07/27/2001
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Title:
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N-GATE/N-SUBSTRATE OR P-GATE/P-SUBSTRATE CAPACITOR TO CHARACTERIZE POLYSILICON GATE DEPLETION EVALUATION
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09969572
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Filing Dt:
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10/01/2001
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Title:
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FLASH MEMORY DEVICE WITH INCREASE OF EFFICIENCY DURING AN APDE (AUTOMATIC PROGRAM DISTURB AFTER ERASE) PROCESS
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09969573
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Filing Dt:
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10/01/2001
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Title:
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FORMATION OF STI (SHALLOW TRENCH ISOLATION) STRUCTURES WITHIN CORE AND PERIPHERY AREAS OF FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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09973131
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Filing Dt:
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10/09/2001
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Title:
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NON SELF-ALIGNED SHALLOW TRENCH ISOLATION PROCESS WITH DISPOSABLE SPACE TO DEFINE SUB-LITHOGRAPHIC POLY SPACE
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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10017832
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Filing Dt:
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12/12/2001
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Title:
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METHOD OF DETERMINING GATE OXIDE THICKNESS OF AN OPERATIONAL MOSFET
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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10023349
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Filing Dt:
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12/20/2001
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Title:
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METHOD FOR REPAIRING DAMAGE TO CHARGE TRAPPING DIELECTRIC LAYER FROM BIT LINE IMPLANTATION
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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10036757
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Filing Dt:
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12/31/2001
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Title:
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USE OF HIGH-K DIELECTRIC MATERIALS IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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02/08/2005
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Application #:
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10053256
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Filing Dt:
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01/18/2002
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Title:
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TWO-STEP SOURCE SIDE IMPLANT FOR IMPROVING SOURCE RESISTANCE AND SHORT CHANNEL EFFECT IN DEEP SUB-0.18MUM FLASH MEMORY TECHNOLOGY
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10096741
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Filing Dt:
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03/14/2002
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Title:
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LASER THERMAL ANNEALING OF SILICON NITRIDE FOR INCREASED DENSITY AND ETCH SELECTIVITY
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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10103077
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Filing Dt:
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03/20/2002
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Title:
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MEMORY DEVICE HAVING IMPROVED PROGRAMMABILITY
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Patent #:
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Issue Dt:
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06/29/2004
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Application #:
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10113017
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Filing Dt:
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03/28/2002
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Title:
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METHOD OF DETERMINING LOCATION OF GATE OXIDE BREAKDOWN OF MOSFET BY MEASURING CURRENTS
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Patent #:
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Issue Dt:
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11/30/2004
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Application #:
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10126814
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Filing Dt:
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04/19/2002
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Title:
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METHOD FOR REDUCING SHALLOW TRENCH ISOLATION EDGE THINNING ON THIN GATE OXIDES TO IMPROVE PERIPHERAL TRANSISTOR RELIABILITY AND PERFORMANCE FOR HIGH PERFORMANCE FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10126840
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Filing Dt:
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04/19/2002
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Title:
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METHOD FOR REDUCING SHALLOW TRENCH ISOLATION EDGE THINNING ON TUNNEL OXIDES USING PARTIAL NITRIDE STRIP AND SMALL BIRD'S BEAK FORMATION FOR HIGH PERFORMANCE FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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10145952
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Filing Dt:
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05/15/2002
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Title:
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REPLACING LAYERS OF AN INTERGATE DIELECTRIC LAYER WITH HIGH-K MATERIAL FOR IMPROVED SCALABILITY
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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10150556
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Filing Dt:
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05/17/2002
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Title:
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METHOD FOR FABRICATING SELF-ALIGNED GATE OF FLASH MEMORY CELL
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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10159078
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Filing Dt:
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05/31/2002
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Title:
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SEMICONDUCTOR ISOLATION MATERIAL DEPOSITION SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10174734
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Filing Dt:
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06/18/2002
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Title:
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TEST STRUCTURE TO MEASURE INTERLAYER DIELECTRIC EFFECTS AND BREAKDOWN AND DETECT METAL DEFECTS IN FLASH MEMORIES
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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10200330
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Filing Dt:
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07/22/2002
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Title:
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ON-CHIP ERASE PULSE COUNTER FOR EFFICIENT ERASE VERIFY BIST (BUILT-IN-SELF-TEST) MODE
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Patent #:
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Issue Dt:
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03/07/2006
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Application #:
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10200518
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Filing Dt:
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07/22/2002
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Title:
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ADDRESS SEQUENCER WITHIN BIST (BUILT-IN-SELF-TEST) SYSTEM
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Patent #:
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Issue Dt:
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04/11/2006
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Application #:
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10200526
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Filing Dt:
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07/22/2002
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Title:
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DIAGNOSTIC MODE FOR TESTING FUNCTIONALITY OF BIST (BUILT-IN-SELF-TEST) BACK-END STATE MACHINE
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10200539
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Filing Dt:
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07/22/2002
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Title:
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GENERATION OF MARGINING VOLTAGE ON-CHIP DURING TESTING CAM PORTION OF FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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10/07/2003
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Application #:
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10200544
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Filing Dt:
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07/22/2002
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Title:
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ON-CHIP REPAIR OF DEFECTIVE ADDRESS OF CORE FLASH MEMORY CELLS
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10224028
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Filing Dt:
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08/19/2002
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Title:
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METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A C-V MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND A DEVICE THEREBY FORMED
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10224737
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Filing Dt:
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08/20/2002
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Title:
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METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A GATE CURRENT MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND DEVICE THEREBY FORMED
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Patent #:
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Issue Dt:
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04/26/2005
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Application #:
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10225052
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Filing Dt:
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08/20/2002
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Title:
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METHOD OF FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE BY DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING AN OVERDRIVE CURRENT MEASUREMENT TECHNIQUE AND A DEVICE THEREBY FABRICATED
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Patent #:
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Issue Dt:
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10/07/2003
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Application #:
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10274063
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Filing Dt:
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10/17/2002
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Title:
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BI-LAYER FLOATING GATE FOR IMPROVED WORK FUNCTION BETWEEN FLOATING GATE AND A HIGH-K DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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05/17/2005
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Application #:
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10342585
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Filing Dt:
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01/14/2003
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Title:
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FLASH MEMORY CELL PROGRAMMING METHOD AND SYSTEM
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Patent #:
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Issue Dt:
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03/29/2005
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Application #:
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10378885
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Filing Dt:
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03/05/2003
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Title:
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IMPLANT DAMAGE REMOVAL BY LASER THERMAL ANNEALING
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10438942
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Filing Dt:
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05/16/2003
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Title:
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LASER THERMAL ANNEALING METHODS FOR FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10646080
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Filing Dt:
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08/22/2003
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Title:
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USE OF HIGH-K DIELECTRIC MATERIAL IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES
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