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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:019028/0650   Pages: 6
Recorded: 03/19/2007
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 35
1
Patent #:
6020238
Issue Dt:
02/01/2000
Application #:
08978107
Filing Dt:
11/25/1997
Title:
METHOD OF FABRICATING A HIGH DIELECTRIC CONSTANT INTERPOLYSILICON DIELECTRIC STRUCTURE FOR A LOW VOLTAGE NON-VOLATILE MEMORY
2
Patent #:
6025228
Issue Dt:
02/15/2000
Application #:
08978398
Filing Dt:
11/25/1997
Title:
METHOD OF FABRICATING AN OXYNITRIDE-CAPPED HIGH DIELECTRIC CONSTANT INTERPOLYSILICON DIELECTRIC STRUCTURE FOR A LOW VOLTAGE NON-VOLATILE MEMORY.
3
Patent #:
6124608
Issue Dt:
09/26/2000
Application #:
08992961
Filing Dt:
12/18/1997
Title:
NON-VOLATILE TRENCH SEMICONDUCTOR DEVICE HAVING A SHALLOW DRAIN REGION
4
Patent #:
6228746
Issue Dt:
05/08/2001
Application #:
08993149
Filing Dt:
12/18/1997
Title:
METHODOLOGY FOR ACHIEVING DUAL FIELD OXIDE THICKNESSES
5
Patent #:
6080682
Issue Dt:
06/27/2000
Application #:
08993716
Filing Dt:
12/18/1997
Title:
METHODOLOGY FOR ACHIEVING DUAL GATE OXIDE THICKNESSES
6
Patent #:
6002151
Issue Dt:
12/14/1999
Application #:
08993890
Filing Dt:
12/18/1997
Title:
NON- VOLATILE TRENCH SEMICONDUCTOR DEVICE
7
Patent #:
6235632
Issue Dt:
05/22/2001
Application #:
09006495
Filing Dt:
01/13/1998
Title:
TRUNGSTEN PLUG FORMATION
8
Patent #:
6001689
Issue Dt:
12/14/1999
Application #:
09008415
Filing Dt:
01/16/1998
Title:
PROCESS FOR FABRICATING A FLASH MEMORY WITH DUAL FUNCTION CONTROL LINES
9
Patent #:
6100593
Issue Dt:
08/08/2000
Application #:
09032362
Filing Dt:
02/27/1998
Title:
MULTIPLE CHIP HYBRID PACKAGE USING BUMP TECHNOLOGY
10
Patent #:
6091138
Issue Dt:
07/18/2000
Application #:
09032398
Filing Dt:
02/27/1998
Title:
MULTI-CHIP PACKAGING USING BUMP TECHNOLOGY
11
Patent #:
6043120
Issue Dt:
03/28/2000
Application #:
09033723
Filing Dt:
03/03/1998
Title:
ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRINGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
12
Patent #:
6110833
Issue Dt:
08/29/2000
Application #:
09033836
Filing Dt:
03/03/1998
Title:
ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRI NGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
13
Patent #:
6030868
Issue Dt:
02/29/2000
Application #:
09033916
Filing Dt:
03/03/1998
Title:
ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRINGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
14
Patent #:
6146944
Issue Dt:
11/14/2000
Application #:
09039783
Filing Dt:
03/16/1998
Title:
LARGE ANGLE IMPLANTATION TO PREVENT FIELD TURN-ON UNDER SELECT GATE TRANSISTOR FIELD OXIDE REGION FOR NON-VOLATILE MEMORY DEVICES
15
Patent #:
5990515
Issue Dt:
11/23/1999
Application #:
09052062
Filing Dt:
03/30/1998
Title:
TRENCHED GATE NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD WITH CORNER DOPING AND SIDEWALL DOPING
16
Patent #:
6150285
Issue Dt:
11/21/2000
Application #:
09099057
Filing Dt:
06/17/1998
Title:
METHOD FOR SIMULTANEOUS DEPOSITION AND SPUTTERING OF TEOS
17
Patent #:
5930172
Issue Dt:
07/27/1999
Application #:
09103041
Filing Dt:
06/23/1998
Title:
PAGE BUFFER FOR A MULTI-LEVEL FLASH MEMORY WITH A LIMITED NUMBER OF LATCHES PER MEMORY CELL
18
Patent #:
5973958
Issue Dt:
10/26/1999
Application #:
09103046
Filing Dt:
06/23/1998
Title:
INTERLACED STORAGE AND SENSE TECHNIQUE FOR FLASH MULTI-LEVEL DEVICES
19
Patent #:
6369421
Issue Dt:
04/09/2002
Application #:
09106177
Filing Dt:
06/29/1998
Title:
EEPROM HAVING STACKED DIELECTRIC TO INCREASE PROGRAMMING SPEED
20
Patent #:
6091631
Issue Dt:
07/18/2000
Application #:
09108529
Filing Dt:
07/01/1998
Title:
PROGRAM/VERIFY TECHNIQUE FOR MULTI-LEVEL FLASH CELLS ENABLING DIFFERENT THRESHOLD LEVELS TO BE SIMULTANEOUSLY PROGRAMMED
21
Patent #:
6118147
Issue Dt:
09/12/2000
Application #:
09110446
Filing Dt:
07/07/1998
Title:
DOUBLE DENSITY NON-VOLATILE MEMEORY CELLS
22
Patent #:
6146795
Issue Dt:
11/14/2000
Application #:
09146032
Filing Dt:
09/02/1998
Title:
METHOD FOR MANUFACTURING MEMORY DEVICES
23
Patent #:
6369433
Issue Dt:
04/09/2002
Application #:
09182525
Filing Dt:
10/30/1998
Title:
HIGH VOLTAGE TRANSISTOR WITH LOW BODY EFFECT AND LOW LEAKAGE
24
Patent #:
6246118
Issue Dt:
06/12/2001
Application #:
09252185
Filing Dt:
02/18/1999
Title:
LOW DIELECTRIC SEMICONDUCTOR DEVICE WITH RIGID, CONDUCTIVELY LINED INTERCONNECTION SYSTEM
25
Patent #:
6584594
Issue Dt:
06/24/2003
Application #:
09314574
Filing Dt:
05/18/1999
Title:
DATA PRE-READING AND ERROR CORRECTION CIRCUIT FOR A MEMORY DEVICE
26
Patent #:
6438726
Issue Dt:
08/20/2002
Application #:
09314575
Filing Dt:
05/18/1999
Title:
METHOD OF DUAL USE OF NON-VOLATILE MEMORY FOR ERROR CORRECTION
27
Patent #:
6175522
Issue Dt:
01/16/2001
Application #:
09408846
Filing Dt:
09/30/1999
Title:
READ OPERATION SCHEME FOR A HIGH-DENSITY, LOW VOLTAGE, AND SUPERIOR RELIABILITY NAND FLASH MEMORY DEVICE
28
Patent #:
6232632
Issue Dt:
05/15/2001
Application #:
09436503
Filing Dt:
11/09/1999
Title:
DOUBLE DENSITY NON-VOLATILE MEMORY CELLS
29
Patent #:
6455888
Issue Dt:
09/24/2002
Application #:
09506298
Filing Dt:
02/17/2000
Title:
ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRINGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
30
Patent #:
6232244
Issue Dt:
05/15/2001
Application #:
09562442
Filing Dt:
05/01/2000
Title:
Methodology for achieving dual gate oxide thicknesses
31
Patent #:
6713842
Issue Dt:
03/30/2004
Application #:
09639798
Filing Dt:
08/17/2000
Title:
MASK FOR AND METHOD OF FORMING A CHARACTER ON A SUBSTRATE
32
Patent #:
6475868
Issue Dt:
11/05/2002
Application #:
09640082
Filing Dt:
08/17/2000
Title:
OXYGEN IMPLANTATION FOR REDUCTION OF JUNCTION CAPACITANCE IN MOS TRANSISTORS
33
Patent #:
6348356
Issue Dt:
02/19/2002
Application #:
09664636
Filing Dt:
09/19/2000
Title:
Method and apparatus for determining the robustness of memory cells to alpha-particle/cosmic ray induced soft errors
34
Patent #:
6506640
Issue Dt:
01/14/2003
Application #:
09667686
Filing Dt:
09/22/2000
Title:
MULTIPLE CHANNEL IMPLANTATION TO FORM RETROGRADE CHANNEL PROFILE AND TO ENGINEER THRESHOLD VOLTAGE AND SUB-SURFACE PUNCH-THROUGH
35
Patent #:
6566252
Issue Dt:
05/20/2003
Application #:
09689144
Filing Dt:
10/11/2000
Title:
METHOD FOR SIMULTANEOUS DEPOSITION AND SPUTTERING OF TEOS AND DEVICE THEREBY FORMED
Assignor
1
ADVANCED MICRO DEVICES, INC.
Exec Dt:
01/31/2007
Assignee
1
SPANSION INC.
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CALIFORNIA 94088-3453
Correspondence name and address
RAYMOND E. FRITZ
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CA 94088-3453

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