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Total properties:
35
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09189227
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Filing Dt:
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11/11/1998
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Title:
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LPCVD OXIDE AND RTA FOR TOP OXIDE OF ONO FILM TO IMPROVE RELIABILITY FOR FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09198654
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Filing Dt:
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11/24/1998
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Title:
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METHOD FOR FABRICATING A HIGH-DENSITY AND HIGH-RELIABILITY EEPROM DEVICE
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09199772
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Filing Dt:
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11/25/1998
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Title:
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METHOD FOR IMPROVING ELECTROSTATIC DISCHARGE ( ESD) ROBUSTNESS
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09205899
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Filing Dt:
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12/04/1998
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Title:
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METHOD OF FORMING ONO STACKED FILMS AND DCS TUNGSTEN SILICIDE GATE TO IMPROVE POLYCIDE GATE PERFORMANCE FOR FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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09252186
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Filing Dt:
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02/18/1999
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Title:
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LOW DIELECTRIC METAL SILICIDE LINED INTERCONNECTION SYSTEM
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09307259
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Filing Dt:
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05/06/1999
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Title:
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RAMPED OR STEPPED GATE CHANNEL ERASE FOR FLASH MEMORY APPLICATION
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09370380
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Filing Dt:
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08/09/1999
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Title:
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RAMPED GATE TECHNIQUE FOR SOFT PROGRAMMING TO TIGHTEN THE VT DISTRIBUTION
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09387710
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Filing Dt:
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08/30/1999
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Title:
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INTEGRATED CIRCUIT HAVING OPTIMIZED GATE COUPLING CAPACITANCE
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09389161
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Filing Dt:
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09/02/1999
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Title:
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1 TRANSISTOR CELL FOR EEPROM APPLICATION
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09390052
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Filing Dt:
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09/03/1999
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Title:
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FLASH MEMORY DEVICE AND FABRICATION METHOD HAVING A HIGH COUPLING RATIO
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Patent #:
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Issue Dt:
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04/11/2000
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Application #:
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09404080
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Filing Dt:
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09/23/1999
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Title:
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OPERATIONAL APPROACH FOR THE SUPPRESSION OF BI-DIRECTIONAL TUNNEL OXIDE STRESS OF A FLASH CELL
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09420220
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Filing Dt:
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10/18/1999
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Title:
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NITRIDE PLUG TO REDUCE GATE EDGE LIFTING
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09430336
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Filing Dt:
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10/29/1999
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Title:
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BIASING SCHEME TO REDUCE STRESS ON NON-SELECTED CELLS DURING READ
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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09430410
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Filing Dt:
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10/29/1999
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Title:
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SOLID-SOURCE DOPING FOR SOURCE/DRAIN TO ELIMINATE IMPLANT DAMAGE
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09476584
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Filing Dt:
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01/03/2000
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Title:
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USE OF ETCH TO BLUNT GATE CORNERS
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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09476906
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Filing Dt:
|
01/03/2000
|
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Title:
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DEPOSITED SCREEN OXIDE FOR REDUCING GATE EDGE LIFTING
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|
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Patent #:
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Issue Dt:
|
12/12/2000
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Application #:
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09490351
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Filing Dt:
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01/24/2000
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Title:
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METHOD TO PROVIDE A REDUCED CONSTANT E-FIELD DURING ERASE OF EEPROMS FOR RELIABILITY IMPROVEMENT
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09490352
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Filing Dt:
|
01/24/2000
|
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Title:
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Background correction for charge gain and loss
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09490353
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Filing Dt:
|
01/24/2000
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Title:
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Reduction of oxide stress through the use of forward biased body voltage
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09495213
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Filing Dt:
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01/31/2000
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Title:
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Nitridization of the pre-ddi screen oxide
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Patent #:
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Issue Dt:
|
05/29/2001
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Application #:
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09495214
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Filing Dt:
|
01/31/2000
|
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Title:
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Method to reduce read gate disturb for flash eeprom application
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|
|
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Patent #:
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|
Issue Dt:
|
03/06/2001
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Application #:
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09495215
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Filing Dt:
|
01/31/2000
|
|
Title:
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APDE scheme for flash memory application
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|
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Patent #:
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|
Issue Dt:
|
09/04/2001
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Application #:
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09495216
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Filing Dt:
|
01/31/2000
|
|
Title:
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Erase scheme to tighten the threshold voltage distribution of EEPROM flash memory cells
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|
|
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Patent #:
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|
Issue Dt:
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01/27/2004
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Application #:
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09504087
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Filing Dt:
|
02/15/2000
|
|
Title:
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INTEGRATED CIRCUIT HAVING INCREASED GATE COUPLING CAPACITANCE
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|
|
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Patent #:
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|
Issue Dt:
|
06/25/2002
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Application #:
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09507810
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Filing Dt:
|
02/22/2000
|
|
Title:
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METHOD FOR REMOVING SEMICONDUCTOR ARC USING ARC CMP BUFFING
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|
|
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Patent #:
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Issue Dt:
|
03/27/2001
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Application #:
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09516472
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Filing Dt:
|
03/01/2000
|
|
Title:
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FLASH MEMORY CELLS HAVING A MODULATION DOPED HETEROJUNCTION STRUCTURE
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|
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Patent #:
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|
Issue Dt:
|
02/12/2002
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Application #:
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09538168
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Filing Dt:
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03/30/2000
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|
Title:
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Planarization of a polysilicon layer surface by chemical mechanical polish to improve lithography and silicide formation
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|
|
|
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Patent #:
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|
Issue Dt:
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03/11/2003
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Application #:
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09543484
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Filing Dt:
|
04/06/2000
|
|
Title:
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USE OF GASEOUS SILICON HYDRIDES AS A REDUCING AGENT TO REMOVE RE-SPUTTERED SILICON OXIDE
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|
|
|
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Patent #:
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|
Issue Dt:
|
05/15/2001
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Application #:
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09543991
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Filing Dt:
|
04/06/2000
|
|
Title:
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New method to fabricate a high coupling flash cell with less silicide seam problem
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|
|
|
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Patent #:
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|
Issue Dt:
|
06/17/2003
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Application #:
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09619231
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Filing Dt:
|
07/19/2000
|
|
Title:
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ELIMINATION OF N+ CONTACT IMPLANT FROM FLASH TECHNOLOGIES BY REPLACEMENT WITH STANDARD DOUBLE-DIFFUSED AND N+ IMPLANTS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
09/17/2002
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Application #:
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09693649
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Filing Dt:
|
10/21/2000
|
|
Title:
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FEEDBACK METHOD TO OPTIMIZE ELECTRIC FIELD DURING CHANNEL ERASE OF FLASH MEMORY DEVICES
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|
|
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Patent #:
|
|
Issue Dt:
|
05/15/2001
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Application #:
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09693650
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Filing Dt:
|
10/21/2000
|
|
Title:
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Self-limiting multi-level programming states
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Patent #:
|
|
Issue Dt:
|
08/27/2002
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Application #:
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09704026
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Filing Dt:
|
11/01/2000
|
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Title:
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PHOTORESIST SPACER PROCESS SIMPLIFICATION TO ELIMINATE THE STANDARD POLYSILICON OR OXIDE SPACER PROCESS FOR FLASH MEMORY CIRCUITS
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|
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Patent #:
|
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Issue Dt:
|
08/21/2001
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Application #:
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09708982
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Filing Dt:
|
11/01/2000
|
|
Title:
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Elimination of N+ implant from flash technologies by replacement with standard medium-doped-drain (Mdd) implant
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|
|
|
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Patent #:
|
|
Issue Dt:
|
04/15/2003
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Application #:
|
10067765
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Filing Dt:
|
02/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2002
| | | | |
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Title:
|
PLANARIZATION OF A POLYSILICON LAYER SURFACE BY CHEMICAL MECHANICAL POLISH TO IMPROVE LITHOGRAPHY AND SILICIDE FORMATION
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|
