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Patent Assignment Details
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Reel/Frame:019028/0662   Pages: 6
Recorded: 03/19/2007
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 35
1
Patent #:
6268624
Issue Dt:
07/31/2001
Application #:
09364982
Filing Dt:
07/31/1999
Title:
METHOD FOR INHIBITING TUNNEL OXIDE GROWTH AT THE EDGES OF A FLOATING GATE DURING SEMICONDUCOR DEVICE PROCESSING
2
Patent #:
6248627
Issue Dt:
06/19/2001
Application #:
09376658
Filing Dt:
08/18/1999
Title:
METHOD FOR PROTECTING GATE EDGES FROM CHARGE GAIN/LOSS IN SEMICONDUCTOR DEVICE
3
Patent #:
6808996
Issue Dt:
10/26/2004
Application #:
09376659
Filing Dt:
08/18/1999
Title:
METHOD FOR PROTECTING GATE EDGES FROM CHARGE GAIN/LOSS IN SEMICONDUCTOR DEVICE
4
Patent #:
6369416
Issue Dt:
04/09/2002
Application #:
09404394
Filing Dt:
09/23/1999
Title:
SEMICONDUCTOR DEVICE WITH CONTACTS HAVING A SLOPED PROFILE
5
Patent #:
6342415
Issue Dt:
01/29/2002
Application #:
09404395
Filing Dt:
09/23/1999
Publication #:
US20020025618
Pub Dt:
02/28/2002
Title:
METHOD AND SYSTEM FOR PROVIDING REDUCED-SIZED CONTACTS IN A SEMICONDUCTOR DEVICE
6
Patent #:
6235584
Issue Dt:
05/22/2001
Application #:
09412544
Filing Dt:
10/05/1999
Title:
METHOD AND SYSTEM FOR REDUCING SHORT CHANNEL EFFECTS IN A MEMORY DEVICE
7
Patent #:
6197635
Issue Dt:
03/06/2001
Application #:
09417130
Filing Dt:
10/13/1999
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH REDUCED MASKING AND WITHOUT ARC LOSS IN PERIPHERAL CIRCUITRY REGION
8
Patent #:
6235587
Issue Dt:
05/22/2001
Application #:
09417131
Filing Dt:
10/13/1999
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH REDUCED ARC LOSS IN PERIPHERAL CIRCUITRY REGION
9
Patent #:
6200857
Issue Dt:
03/13/2001
Application #:
09417132
Filing Dt:
10/13/1999
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITHOUT ARC LOSS IN PERIPHERAL CIRCUIT REGION
10
Patent #:
6867097
Issue Dt:
03/15/2005
Application #:
09430366
Filing Dt:
10/28/1999
Title:
METHOD OF MAKING A MEMORY CELL WITH POLISHED INSULATOR LAYER
11
Patent #:
6551923
Issue Dt:
04/22/2003
Application #:
09430845
Filing Dt:
11/01/1999
Title:
DUAL WIDTH CONTACT FOR CHARGE GAIN REDUCTION
12
Patent #:
6441418
Issue Dt:
08/27/2002
Application #:
09430848
Filing Dt:
11/01/1999
Title:
SPACER NARROWED, DUAL WIDTH CONTACT FOR CHARGE GAIN REDUCTION
13
Patent #:
6465835
Issue Dt:
10/15/2002
Application #:
09487964
Filing Dt:
01/18/2000
Title:
CHARGE GAIN/CHARGE LOSS JUNCTION LEAKAGE PREVENTION FOR FLASH TECHNOLOGY BY USING DOUBLE ISOLATION/CAPPING LAYER BETWEEN LIGHTLY DOPED DRAIN AND GATE
14
Patent #:
6509604
Issue Dt:
01/21/2003
Application #:
09491457
Filing Dt:
01/26/2000
Title:
NOVEL NITRIDATION BARRIERS FOR NITRIDATED TUNNEL OXIDE FOR CIRCUITRY FOR FLASH TECHNOLOGY AND FOR LOCOS/STI ISOLATION
15
Patent #:
6787840
Issue Dt:
09/07/2004
Application #:
09492931
Filing Dt:
01/27/2000
Title:
NITRIDATED TUNNEL OXIDE BARRIERS FOR FLASH MEMORY TECHOLOGY CIRCUITRY
16
Patent #:
6359307
Issue Dt:
03/19/2002
Application #:
09493436
Filing Dt:
01/29/2000
Title:
METHOD FOR FORMING SELF-ALIGNED CONTACTS AND INTERCONNECTION LINES USING DUAL DAMASCENE TECHNIQUES
17
Patent #:
6348379
Issue Dt:
02/19/2002
Application #:
09502153
Filing Dt:
02/11/2000
Title:
Method of forming self-aligned contacts using consumable spacers
18
Patent #:
6486506
Issue Dt:
11/26/2002
Application #:
09532293
Filing Dt:
03/23/2000
Title:
FLASH MEMORY WITH LESS SUSCEPTIBILITY TO CHARGE GAIN AND CHARGE LOSS
19
Patent #:
6635943
Issue Dt:
10/21/2003
Application #:
09533617
Filing Dt:
03/22/2000
Title:
METHOD AND SYSTEM FOR REDUCING CHARGE GAIN AND CHARGE LOSS IN INTERLAYER DIELECTRIC FORMATION
20
Patent #:
6294460
Issue Dt:
09/25/2001
Application #:
09586254
Filing Dt:
05/31/2000
Title:
Semiconductor manufacturing method using a high extinction coefficient dielectric photomask
21
Patent #:
6380067
Issue Dt:
04/30/2002
Application #:
09588119
Filing Dt:
05/31/2000
Title:
METHOD FOR CREATING PARTIALLY UV TRANSPARENT ANTI-REFLECTIVE COATING FOR SEMICONDUCTORS
22
Patent #:
6512264
Issue Dt:
01/28/2003
Application #:
09594207
Filing Dt:
06/14/2000
Title:
FLASH MEMORY HAVING PRE-INTERPOLY DIELECTRIC TREATMENT LAYER AND METHOD OF FORMING
23
Patent #:
6306777
Issue Dt:
10/23/2001
Application #:
09595166
Filing Dt:
06/15/2000
Title:
Flash memory having a treatment layer disposed between an interpoly dielectric structure and method of forming
24
Patent #:
6798002
Issue Dt:
09/28/2004
Application #:
09607675
Filing Dt:
06/30/2000
Title:
DUAL-PURPOSE ANTI-REFLECTIVE COATING AND SPACER FOR FLASH MEMORY AND OTHER DUAL GATE TECHNOLOGIES AND METHOD OF FORMING
25
Patent #:
6448608
Issue Dt:
09/10/2002
Application #:
09631894
Filing Dt:
08/04/2000
Title:
NOVEL CAPPING LAYER
26
Patent #:
6337246
Issue Dt:
01/08/2002
Application #:
09824841
Filing Dt:
04/02/2001
Title:
Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing
27
Patent #:
6455373
Issue Dt:
09/24/2002
Application #:
09834419
Filing Dt:
04/12/2001
Title:
SEMICONDUCTOR DEVICE HAVING GATE EDGES PROTECTED FROM CHARGE GAIN/LOSS
28
Patent #:
6709927
Issue Dt:
03/23/2004
Application #:
09927134
Filing Dt:
08/10/2001
Title:
PROCESS FOR TREATING ONO DIELECTRIC FILM OF A FLOATING GATE MEMORY CELL
29
Patent #:
6620705
Issue Dt:
09/16/2003
Application #:
10006529
Filing Dt:
12/05/2001
Title:
NITRIDING PRETREATMENT OF ONO NITRIDE FOR OXIDE DEPOSITION
30
Patent #:
6858496
Issue Dt:
02/22/2005
Application #:
10010280
Filing Dt:
12/05/2001
Title:
OXIDIZING PRETREATMENT OF ONO LAYER FOR FLASH MEMORY
31
Patent #:
7015134
Issue Dt:
03/21/2006
Application #:
10079775
Filing Dt:
02/19/2002
Publication #:
US20020076931
Pub Dt:
06/20/2002
Title:
METHOD FOR REDUCING ANTI-REFLECTIVE COATING LAYER REMOVAL DURING REMOVAL OF PHOTORESIST
32
Patent #:
6548334
Issue Dt:
04/15/2003
Application #:
10179061
Filing Dt:
06/24/2002
Title:
NOVEL CAPPING LAYER
33
Patent #:
6589841
Issue Dt:
07/08/2003
Application #:
10180772
Filing Dt:
06/25/2002
Title:
CHARGE GAIN/CHARGE LOSS JUNCTION LEAKAGE PREVENTION FOR FLASH TECHNOLOGY BY USING DOUBLE ISOLATION/CAPPING LAYER BETWEEN LIGHTLY DOPED DRAIN AND GATE
34
Patent #:
6716702
Issue Dt:
04/06/2004
Application #:
10291293
Filing Dt:
11/08/2002
Publication #:
US20030071304
Pub Dt:
04/17/2003
Title:
METHOD OF FORMING FLASH MEMORY HAVING PRE-INTERPOLY DIELECTRIC TREATMENT LAYER
35
Patent #:
6605511
Issue Dt:
08/12/2003
Application #:
10295738
Filing Dt:
11/15/2002
Publication #:
US20030073288
Pub Dt:
04/17/2003
Title:
METHOD OF FABRICATING NITRIDATED TUNNEL OXIDE BARRIERS FOR FLASH MEMORY DEVICES HAVING STI AND LOCOS ISOLATION
Assignor
1
ADVANCED MICRO DEVICES, INC.
Exec Dt:
01/31/2007
Assignee
1
SPANSION INC.
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CALIFORNIA 94088-3453
Correspondence name and address
RAYMOND E. FRITZ
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CA 94088-3453

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