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Reel/Frame:051061/0681   Pages: 36
Recorded: 11/20/2019
Attorney Dkt #:5059-500029
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 31
1
Patent #:
6968413
Issue Dt:
11/22/2005
Application #:
10266132
Filing Dt:
10/07/2002
Publication #:
US20040068600
Pub Dt:
04/08/2004
Title:
METHOD AND SYSTEM FOR CONFIGURING TERMINATORS IN A SERIAL COMMUNICATION SYSTEM
2
Patent #:
7305600
Issue Dt:
12/04/2007
Application #:
10651874
Filing Dt:
08/29/2003
Publication #:
US20050047224
Pub Dt:
03/03/2005
Title:
PARTIAL GOOD INTEGRATED CIRCUIT AND METHOD OF TESTING SAME
3
Patent #:
6967885
Issue Dt:
11/22/2005
Application #:
10757846
Filing Dt:
01/15/2004
Publication #:
US20050157577
Pub Dt:
07/21/2005
Title:
CONCURRENT REFRESH MODE WITH DISTRIBUTED ROW ADDRESS COUNTERS IN AN EMBEDDED DRAM
4
Patent #:
7477713
Issue Dt:
01/13/2009
Application #:
10791175
Filing Dt:
03/02/2004
Publication #:
US20050195863
Pub Dt:
09/08/2005
Title:
METHOD FOR PROVIDING AUTOMATIC ADAPTATION TO FREQUENCY OFFSETS IN HIGH SPEED SERIAL LINKS
5
Patent #:
7391266
Issue Dt:
06/24/2008
Application #:
11531714
Filing Dt:
09/14/2006
Publication #:
US20080068084
Pub Dt:
03/20/2008
Title:
SERIAL LINK OUTPUT STAGE DIFFERENTIAL AMPLIFIER AND METHOD
6
Patent #:
7499308
Issue Dt:
03/03/2009
Application #:
11689096
Filing Dt:
03/21/2007
Publication #:
US20080273393
Pub Dt:
11/06/2008
Title:
PROGRAMMABLE HEAVY-ION SENSING DEVICE FOR ACCELERATED DRAM SOFT ERROR DETECTION
7
Patent #:
8695089
Issue Dt:
04/08/2014
Application #:
11694388
Filing Dt:
03/30/2007
Publication #:
US20080244739
Pub Dt:
10/02/2008
Title:
METHOD AND SYSTEM FOR RESILIENT PACKET TRACEBACK IN WIRELESS MESH AND SENSOR NETWORKS
8
Patent #:
7671678
Issue Dt:
03/02/2010
Application #:
12117098
Filing Dt:
05/08/2008
Publication #:
US20080238554
Pub Dt:
10/02/2008
Title:
SERIAL LINK OUTPUT STAGE DIFFERENTIAL AMPLIFIER AND METHOD
9
Patent #:
7675789
Issue Dt:
03/09/2010
Application #:
12134347
Filing Dt:
06/06/2008
Publication #:
US20080266984
Pub Dt:
10/30/2008
Title:
PROGRAMMABLE HEAVY-ION SENSING DEVICE FOR ACCELERATED DRAM SOFT ERROR DETECTION
10
Patent #:
8214699
Issue Dt:
07/03/2012
Application #:
12147670
Filing Dt:
06/27/2008
Publication #:
US20090327620
Pub Dt:
12/31/2009
Title:
CIRCUIT STRUCTURE AND METHOD FOR DIGITAL INTEGRATED CIRCUIT PERFORMANCE SCREENING
11
Patent #:
8599966
Issue Dt:
12/03/2013
Application #:
13173434
Filing Dt:
06/30/2011
Publication #:
US20130002347
Pub Dt:
01/03/2013
Title:
COUPLING SYSTEM FOR DATA RECEIVERS
12
Patent #:
8773920
Issue Dt:
07/08/2014
Application #:
13401368
Filing Dt:
02/21/2012
Publication #:
US20130215686
Pub Dt:
08/22/2013
Title:
REFERENCE GENERATOR WITH PROGRAMMABLE M AND B PARAMETERS AND METHODS OF USE
13
Patent #:
8867668
Issue Dt:
10/21/2014
Application #:
14074920
Filing Dt:
11/08/2013
Publication #:
US20140133604
Pub Dt:
05/15/2014
Title:
COUPLING SYSTEM FOR DATA RECEIVERS
14
Patent #:
10396811
Issue Dt:
08/27/2019
Application #:
16248290
Filing Dt:
01/15/2019
Title:
TEMPERATURE COMPENSATION FOR REFERENCE VOLTAGES IN AN ANALOG-TO-DIGITAL CONVERTER
15
Patent #:
11114155
Issue Dt:
09/07/2021
Application #:
16256584
Filing Dt:
01/24/2019
Publication #:
US20200243130
Pub Dt:
07/30/2020
Title:
HIGH-DENSITY HIGH-BANDWIDTH STATIC RANDOM ACCESS MEMORY (SRAM) WITH PHASE SHIFTED SEQUENTIAL READ
16
Patent #:
10447510
Issue Dt:
10/15/2019
Application #:
16266707
Filing Dt:
02/04/2019
Title:
ON-DEMAND FEED FORWARD EQUALIZER WITH DISTRIBUTED ARITHMETIC ARCHITECTURE AND METHOD
17
Patent #:
10726909
Issue Dt:
07/28/2020
Application #:
16359076
Filing Dt:
03/20/2019
Title:
MULTI-PORT MEMORY ARRAYS WITH INTEGRATED WORDLINE COUPLING MITIGATION STRUCTURES AND METHOD
18
Patent #:
10950325
Issue Dt:
03/16/2021
Application #:
16375115
Filing Dt:
04/04/2019
Publication #:
US20200321070
Pub Dt:
10/08/2020
Title:
MEMORY BUILT-IN SELF TEST ERROR CORRECTING CODE (MBIST ECC) FOR LOW VOLTAGE MEMORIES
19
Patent #:
10964357
Issue Dt:
03/30/2021
Application #:
16393050
Filing Dt:
04/24/2019
Publication #:
US20200342918
Pub Dt:
10/29/2020
Title:
SKEWED SENSE AMPLIFIER FOR SINGLE-ENDED SENSING
20
Patent #:
10964362
Issue Dt:
03/30/2021
Application #:
16393997
Filing Dt:
04/25/2019
Publication #:
US20200342921
Pub Dt:
10/29/2020
Title:
THREE-PORT MEMORY CELL AND ARRAY FOR IN-MEMORY COMPUTING
21
Patent #:
10826489
Issue Dt:
11/03/2020
Application #:
16433567
Filing Dt:
06/06/2019
Title:
SELECTION CIRCUIT
22
Patent #:
10840892
Issue Dt:
11/17/2020
Application #:
16512535
Filing Dt:
07/16/2019
Title:
FULLY DIGITAL, STATIC, TRUE SINGLE-PHASE CLOCK (TSPC) FLIP-FLOP
23
Patent #:
10839931
Issue Dt:
11/17/2020
Application #:
16520642
Filing Dt:
07/24/2019
Publication #:
US20190348137
Pub Dt:
11/14/2019
Title:
ZERO TEST TIME MEMORY USING BACKGROUND BUILT-IN SELF-TEST
24
Patent #:
10721104
Issue Dt:
07/21/2020
Application #:
16525723
Filing Dt:
07/30/2019
Publication #:
US20200186401
Pub Dt:
06/11/2020
Title:
FEED FORWARD EQUALIZER WITH POWER-OPTIMIZED DISTRIBUTED ARITHMETIC ARCHITECTURE AND METHOD
25
Patent #:
11580059
Issue Dt:
02/14/2023
Application #:
16527100
Filing Dt:
07/31/2019
Publication #:
US20210034567
Pub Dt:
02/04/2021
Title:
MULTI-PORT MEMORY ARCHITECTURE FOR A SYSTOLIC ARRAY
26
Patent #:
10978143
Issue Dt:
04/13/2021
Application #:
16550953
Filing Dt:
08/26/2019
Publication #:
US20210065784
Pub Dt:
03/04/2021
Title:
MULTI-PORT HIGH PERFORMANCE MEMORY
27
Patent #:
11101010
Issue Dt:
08/24/2021
Application #:
16568394
Filing Dt:
09/12/2019
Publication #:
US20210082532
Pub Dt:
03/18/2021
Title:
SENSING CIRCUITS FOR CHARGE TRAP TRANSISTORS
28
Patent #:
11282806
Issue Dt:
03/22/2022
Application #:
16599738
Filing Dt:
10/11/2019
Publication #:
US20210111141
Pub Dt:
04/15/2021
Title:
PARTITIONED SUBSTRATES WITH INTERCONNECT BRIDGE
29
Patent #:
11024347
Issue Dt:
06/01/2021
Application #:
16655283
Filing Dt:
10/17/2019
Publication #:
US20210118477
Pub Dt:
04/22/2021
Title:
MULTIPLE SENSE AMPLIFIER AND DATA PATH-BASED PSEUDO DUAL PORT SRAM
30
Patent #:
11171104
Issue Dt:
11/09/2021
Application #:
16662293
Filing Dt:
10/24/2019
Publication #:
US20210125952
Pub Dt:
04/29/2021
Title:
IC CHIP PACKAGE WITH DUMMY SOLDER STRUCTURE UNDER CORNER, AND RELATED METHOD
31
Patent #:
10748852
Issue Dt:
08/18/2020
Application #:
16663413
Filing Dt:
10/25/2019
Title:
MULTI-CHIP MODULE (MCM) WITH CHIP-TO-CHIP CONNECTION REDUNDANCY AND METHOD
Assignor
1
GLOBALFOUNDRIES, INC.
Exec Dt:
11/05/2019
Assignee
1
MARVELL INTERNATIONAL LTD.
CANON'S COURT, 22 VICTORIA STREET
HAMILTON, BERMUDA HM 12
Correspondence name and address
HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 828
BLOOMFIELD HILLS, MI 48303

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