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Total properties:
60
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Patent #:
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Issue Dt:
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05/19/2009
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Application #:
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10378061
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Filing Dt:
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02/28/2003
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Publication #:
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Pub Dt:
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09/02/2004
| | | | |
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Title:
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SEGMENTED VIRTUAL MACHINE
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10701388
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Filing Dt:
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11/04/2003
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Title:
|
MEMORY MANAGEMENT
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Patent #:
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Issue Dt:
|
04/10/2007
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Application #:
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10710066
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Filing Dt:
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06/16/2004
|
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Title:
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ADDRESS ERROR DETECTION BY MERGING A POLYNOMIAL-BASED CRC CODE OF ADDRESS BITS WITH TWO NIBBLES OF DATA OR DATA ECC BITS
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Patent #:
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Issue Dt:
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05/29/2007
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Application #:
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10711387
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Filing Dt:
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09/15/2004
|
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Title:
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DUPLICATE SNOOP TAGS PARTITIONED ACROSS MULTIPLE PROCESSOR/CACHE CHIPS IN A MULTI-PROCESSOR SYSTEM
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Patent #:
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Issue Dt:
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10/02/2007
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Application #:
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10816471
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Filing Dt:
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04/01/2004
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Title:
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COOPERATIVE MEMORY MANAGEMENT
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Patent #:
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Issue Dt:
|
06/22/2010
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Application #:
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10823414
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Filing Dt:
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04/12/2004
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Title:
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INFORMATION REDIRECTION
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Patent #:
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Issue Dt:
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07/15/2008
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Application #:
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10858832
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Filing Dt:
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06/01/2004
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Title:
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EXPANDED MEMORY SPACE IN ENVIRONMENTS INCLUDING VIRTUAL MACHINES
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Patent #:
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Issue Dt:
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05/30/2006
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Application #:
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10906438
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Filing Dt:
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02/19/2005
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Title:
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MULTI-CHIP PACKAGE HAVING REPAIRABLE EMBEDDED MEMORIES ON A SYSTEM CHIP WITH AN EEPROM CHIP STORING REPAIR INFORMATION
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Patent #:
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Issue Dt:
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07/24/2007
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Application #:
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10907662
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Filing Dt:
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04/11/2005
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Title:
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ERROR RECOVERY OF VARIABLE-LENGTH PACKETS WITHOUT SEQUENCE NUMBERS OR SPECIAL SYMBOLS USED FOR SYNCHRONIZING TRANSMIT RETRY-BUFFER POINTER
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Patent #:
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Issue Dt:
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10/14/2008
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Application #:
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10908586
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Filing Dt:
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05/18/2005
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Title:
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WRITE-BACK CACHE WITH DIFFERENT ECC CODINGS FOR CLEAN AND DIRTY LINES WITH REFETCHING OF UNCORRECTABLE CLEAN LINES
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Patent #:
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Issue Dt:
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11/17/2009
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Application #:
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10959407
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Filing Dt:
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10/05/2004
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Title:
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SYSTEM AND METHOD FOR ALLOCATING RESOURCES OF A CORE SPACE AMONG A PLURALITY OF CORE VIRTUAL MACHINES
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Patent #:
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Issue Dt:
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02/23/2010
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Application #:
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10959409
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Filing Dt:
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10/05/2004
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Title:
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RESOURCE MANAGEMENT
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Patent #:
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Issue Dt:
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12/23/2008
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Application #:
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11031015
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Filing Dt:
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01/07/2005
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Publication #:
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Pub Dt:
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07/13/2006
| | | | |
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Title:
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SYSTEM AND METHOD FOR CONCURRENT COMPACTING SELF PACING GARBAGE COLLECTION USING LOADED VALUE AND ACCESS BARRIERS
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Patent #:
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Issue Dt:
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05/20/2008
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Application #:
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11117657
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Filing Dt:
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04/27/2005
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Title:
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SPECULATIVE MULTIADDRESS ATOMICITY
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Patent #:
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Issue Dt:
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10/29/2013
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Application #:
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11118624
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Filing Dt:
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04/28/2005
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Title:
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SOURCE SWITCHING OF VIRTUAL MACHINES
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Patent #:
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Issue Dt:
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07/08/2008
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Application #:
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11161042
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Filing Dt:
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07/20/2005
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Title:
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ENCODING 64-BIT DATA NIBBLE ERROR CORRECT AND CYCLIC-REDUNDANCY CODE (CRC) ADDRESS ERROR DETECT FOR USE ON A 76-BIT MEMORY MODULE
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Patent #:
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Issue Dt:
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02/26/2008
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Application #:
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11162578
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Filing Dt:
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09/15/2005
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Title:
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MULTI-LEVEL POWER MONITORING, FILTERING AND THROTTLING AT LOCAL BLOCKS AND GLOBALLY
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Patent #:
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Issue Dt:
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08/28/2007
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Application #:
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11162595
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Filing Dt:
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09/15/2005
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Title:
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TESTING REPLICATED SUB-SYSTEMS IN A YIELD-ENHANCING CHIP-TEST
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Patent #:
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01/20/2009
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Application #:
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11165827
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Filing Dt:
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06/24/2005
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Title:
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SEGMENTED VIRTUAL MACHINE TRANSPORT MECHANISM
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Patent #:
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Issue Dt:
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11/23/2010
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Application #:
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11227417
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Filing Dt:
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09/14/2005
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Title:
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TRANSPARENT CONCURRENT ATOMIC EXECUTION
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Patent #:
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Issue Dt:
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11/16/2010
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Application #:
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11227418
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Filing Dt:
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09/14/2005
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Title:
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DYNAMIC CONCURRENT ATOMIC EXECUTION
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Patent #:
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Issue Dt:
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07/26/2011
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Application #:
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11227419
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Filing Dt:
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09/14/2005
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Title:
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ACCELERATED CLASS CHECK
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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11227422
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Filing Dt:
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09/14/2005
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Title:
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CONCURRENT ATOMIC EXECUTION
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Patent #:
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Issue Dt:
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07/15/2008
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Application #:
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11227423
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Filing Dt:
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09/14/2005
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Title:
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MEMORY ADDRESSING
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Patent #:
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Issue Dt:
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06/23/2009
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Application #:
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11227448
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Filing Dt:
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09/14/2005
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Title:
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ORDERING OPERATION
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Patent #:
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Issue Dt:
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09/24/2013
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Application #:
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11228034
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Filing Dt:
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09/14/2005
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Title:
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Cooperative preemption
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Patent #:
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Issue Dt:
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03/24/2015
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Application #:
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11250149
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Filing Dt:
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10/12/2005
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Title:
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Multiple cluster processor
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Patent #:
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Issue Dt:
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08/18/2009
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Application #:
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11296191
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Filing Dt:
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12/06/2005
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Title:
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ARRAY ACCESS
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Patent #:
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Issue Dt:
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03/30/2010
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Application #:
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11296195
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Filing Dt:
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12/06/2005
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Title:
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PROCESSOR INSTRUCTION USED TO DETERMINE WHETHER TO PERFORM A MEMORY-RELATED TRAP
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Patent #:
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Issue Dt:
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06/07/2016
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Application #:
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11296651
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Filing Dt:
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12/06/2005
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Title:
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10/11/2011
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11296652
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12/06/2005
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Title:
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ACCELERATED CLASS CHECK
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04/29/2008
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11307413
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02/06/2006
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Publication #:
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Pub Dt:
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08/09/2007
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Title:
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DISTRIBUTED CACHE COHERENCE AT SCALABLE REQUESTOR FILTER PIPES THAT ACCUMULATE INVALIDATION ACKNOWLEDGEMENTS FROM OTHER REQUESTOR FILTER PIPES USING ORDERING MESSAGES FROM CENTRAL SNOOP TAG
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01/27/2009
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11308039
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03/03/2006
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Title:
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SELF-CHECKING TEST GENERATOR FOR PARTIALLY-MODELED PROCESSORS BY PROPAGATING FUZZY STATES
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02/19/2008
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11308048
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03/03/2006
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Title:
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WIDE-SCAN ON-CHIP LOGIC ANALYZER WITH GLOBAL TRIGGER AND INTERLEAVED SRAM CAPTURE BUFFERS
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Patent #:
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09/16/2014
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11449154
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06/07/2006
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Publication #:
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Pub Dt:
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12/13/2007
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Title:
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CPU utilization metering on sytems that include multiple hardware threads per core
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08/14/2007
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11503388
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08/11/2006
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03/22/2007
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Title:
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MEMORY MANAGEMENT
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11/30/2010
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11716545
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03/08/2007
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01/15/2013
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11726695
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03/21/2007
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EXTERNAL DATA SOURCE REDIRECTION IN SEGMENTED VIRTUAL MACHINE
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02/03/2015
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11799448
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04/30/2007
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07/21/2009
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11894434
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08/20/2007
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12/20/2007
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COOPERATIVE MEMORY MANAGEMENT ALLOWING PROGRAM REQUEST AND RELEASE MEMORY AS NEEDED
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05/28/2013
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12082238
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04/08/2008
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GARBAGE COLLECTION WITH MEMORY QUICK RELEASE
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01/12/2010
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12082239
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04/08/2008
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01/17/2012
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06/04/2008
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09/25/2008
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SUBSYSTEM AND METHOD FOR ENCODING 64-BIT DATA NIBBLE ERROR CORRECT AND CYCLIC-REDUNDANCY CODE (CRC) ADDRESS ERROR DETECT FOR USE IN A 76-BIT MEMORY MODULE
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07/05/2011
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12151430
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05/05/2008
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11/13/2008
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MEMORY MANAGEMENT BASED ON CONCURRENT GARBAGE COLLECTION USING SAFEPOINTS
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09/25/2012
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12315854
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12/05/2008
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07/09/2009
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SEGMENTED VIRTUAL MACHINE TRANSPORT MECHANISM
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12/18/2012
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12/05/2008
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07/02/2009
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03/27/2018
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05/01/2009
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ENHANCED MANAGED RUNTIME ENVIRONMENTS THAT SUPPORT DETERMINISTIC RECORD AND REPLAY
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03/27/2018
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05/01/2009
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11/19/2013
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09/25/2009
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04/22/2010
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10/25/2011
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11/25/2009
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07/15/2010
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01/31/2012
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02/12/2010
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06/17/2010
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PROCESSOR INSTRUCTION USED TO PERFORM A MATRIX TEST TO GENERATE A MEMORY-RELATED TRAP
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10/18/2011
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10/06/2010
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04/21/2011
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TRANSPARENT CONCURRENT ATOMIC EXECUTION
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07/24/2012
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10/22/2010
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02/17/2011
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DETECTING SOFTWARE RACE CONDITIONS
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09/23/2014
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06/09/2011
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09/16/2014
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12/29/2011
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05/13/2014
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04/25/2013
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11/21/2013
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GARBAGE COLLECTION WITH MEMORY QUICK RELEASE
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05/10/2016
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08/09/2013
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03/20/2014
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05/17/2016
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08/11/2014
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ACCELERATED CLASS CHECK
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05/09/2017
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08/12/2014
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ACCELERATED CLASS CHECK
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03/14/2017
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08/15/2014
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04/02/2015
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CPU UTILIZATION METERING ON SYSTEMS THAT INCLUDE MULTIPLE HARDWARE THREADS PER CORE
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