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Total properties:
35
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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10262221
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Filing Dt:
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09/30/2002
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Title:
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ORGANIC SPIN-ON ANTI-REFLECTIVE COATING OVER INORGANIC ANTI-REFLECTIVE COATING
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10305756
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Filing Dt:
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11/26/2002
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Title:
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PROGRAM ALGORITHM INCLUDING SOFT ERASE FOR SONOS MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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10307667
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Filing Dt:
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12/02/2002
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Title:
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SYSTEM FOR PROGRAMMING A NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10307749
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Filing Dt:
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12/02/2002
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Publication #:
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Pub Dt:
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06/03/2004
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Title:
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PRE-CHARGE METHOD FOR READING A NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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10315632
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Filing Dt:
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12/10/2002
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Title:
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FLASH MEMORY DEVICE HAVING FOUR-BIT CELLS
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Patent #:
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Issue Dt:
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12/19/2006
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Application #:
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10342549
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Filing Dt:
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01/15/2003
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Title:
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DIELECTRIC MEMORY CELL STRUCTURE WITH COUNTER DOPED CHANNEL REGION
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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10350472
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Filing Dt:
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01/23/2003
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Title:
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STRUCTURE AND METHOD FOR REDUCING STANDING WAVES IN A PHOTORESIST
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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10353558
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Filing Dt:
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01/29/2003
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Title:
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METHOD FOR READING A NON-VOLATILE MEMORY CELL ADJACENT TO AN INACTIVE REGION OF A NON-VOLATILE MEMORY CELL ARRAY
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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10357879
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Filing Dt:
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02/04/2003
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Title:
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METHOD OF IMPROVING DYNAMIC REFERENCE TRACKING FOR FLASH MEMORY UNIT
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Patent #:
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Issue Dt:
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08/10/2004
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Application #:
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10358589
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Filing Dt:
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02/05/2003
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Publication #:
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Pub Dt:
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08/05/2004
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Title:
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UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BIT FLASH MEMORY DEVICES IN BEOL PROCESSING
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Patent #:
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Issue Dt:
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10/10/2006
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Application #:
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10368696
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Filing Dt:
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02/19/2003
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Title:
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PROTECTION OF CHARGE TRAPPING DIELECTRIC FLASH MEMORY DEVICES FROM UV-INDUCED CHARGING IN BEOL PROCESSING
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10382744
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Filing Dt:
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03/05/2003
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Title:
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METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10407999
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Filing Dt:
|
04/03/2003
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Title:
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MEMORY DEVICE HAVING IMPROVED PERIPHERY AND CORE ISOLATION
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|
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Patent #:
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Issue Dt:
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10/18/2005
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Application #:
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10413800
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Filing Dt:
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04/15/2003
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Publication #:
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Pub Dt:
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10/21/2004
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Title:
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METHOD OF PROGRAMMING DUAL CELL MEMORY DEVICE TO STORE MULTIPLE DATA STATES PER CELL
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Patent #:
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|
Issue Dt:
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11/23/2004
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Application #:
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10422090
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Filing Dt:
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04/24/2003
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Title:
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METHOD OF CONTROLLING PROGRAM THRESHOLD VOLTAGE DISTRIBUTION OF A DUAL CELL MEMORY DEVICE
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10422092
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Filing Dt:
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04/24/2003
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Title:
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METHOD OF DUAL CELL MEMORY DEVICE OPERATION FOR IMPROVED END-OF-LIFE READ MARGIN
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10422276
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Filing Dt:
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04/24/2003
|
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Title:
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METHOD OF PROGRAMMING AND READING A DUAL CELL MEMORY DEVICE
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|
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Patent #:
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Issue Dt:
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08/10/2004
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Application #:
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10422489
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Filing Dt:
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04/24/2003
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Title:
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METHOD OF PROGRAMMING A DUAL CELL MEMORY DEVICE
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Patent #:
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|
Issue Dt:
|
03/15/2005
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Application #:
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10430604
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Filing Dt:
|
05/06/2003
|
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Title:
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MEMORY DEVICE WITH REDUCED OPERATING VOLTAGE HAVING DIELECTRIC STACK
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|
|
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Patent #:
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|
Issue Dt:
|
03/01/2005
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Application #:
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10459102
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Filing Dt:
|
06/11/2003
|
|
Title:
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MEMORY DEVICE HAVING A THIN TOP DIELECTRIC AND METHOD OF ERASING SAME
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|
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Patent #:
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|
Issue Dt:
|
02/15/2005
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Application #:
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10463643
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Filing Dt:
|
06/17/2003
|
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Title:
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METHOD OF FABRICATING A PLANAR STRUCTURE CHARGE TRAPPING MEMORY CELL ARRAY WITH RECTANGULAR GATES AND REDUCED BIT LINE RESISTANCE
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|
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Patent #:
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|
Issue Dt:
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12/28/2004
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Application #:
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10619797
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Filing Dt:
|
07/14/2003
|
|
Title:
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PARTIALLY DE-COUPLED CORE AND PERIPHERY GATE MODULE PROCESS
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|
|
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Patent #:
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|
Issue Dt:
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07/19/2005
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Application #:
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10655936
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Filing Dt:
|
09/04/2003
|
|
Title:
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METHOD OF FABRICATING A FLOATING GATE
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|
|
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Patent #:
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|
Issue Dt:
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09/13/2005
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Application #:
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10661720
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Filing Dt:
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09/11/2003
|
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Title:
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A FLASH MEMORY CELL WITH DRAIN AND SOURCE FORMED BY DIFFUSION OF A DOPANT FROM A SILICIDE
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Patent #:
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|
Issue Dt:
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11/22/2005
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Application #:
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10677790
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Filing Dt:
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10/02/2003
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Publication #:
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Pub Dt:
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04/07/2005
| | | | |
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Title:
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MEMORY DEVICE AND METHOD USING POSITIVE GATE STRESS TO RECOVER OVERERASED CELL
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|
|
|
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Patent #:
|
|
Issue Dt:
|
11/15/2005
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Application #:
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10683649
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Filing Dt:
|
10/10/2003
|
|
Publication #:
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Pub Dt:
|
04/14/2005
| | | | |
|
Title:
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RECESS CHANNEL FLASH ARCHITECTURE FOR REDUCED SHORT CHANNEL EFFECT
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|
|
|
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Patent #:
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|
Issue Dt:
|
06/28/2005
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Application #:
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10685044
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Filing Dt:
|
10/14/2003
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|
Publication #:
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Pub Dt:
|
04/14/2005
| | | | |
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Title:
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MEMORY CELL ARRAY WITH STAGGERED LOCAL INTER-CONNECT STRUCTURE
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|
|
|
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Patent #:
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|
Issue Dt:
|
08/23/2005
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Application #:
|
10716209
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Filing Dt:
|
11/18/2003
|
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Title:
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TIGHTLY SPACED GATE FORMATION THROUGH DAMASCENE PROCESS
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|
|
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Patent #:
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|
Issue Dt:
|
05/17/2005
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Application #:
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10716230
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Filing Dt:
|
11/18/2003
|
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Title:
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DUAL CELL MEMORY DEVICE HAVING A TOP DIELECTRIC STACK
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|
|
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Patent #:
|
|
Issue Dt:
|
01/24/2006
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Application #:
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10770260
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Filing Dt:
|
02/02/2004
|
|
Title:
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FLASH MEMORY CELL WITH UV PROTECTIVE LAYER
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|
|
|
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Patent #:
|
|
Issue Dt:
|
08/09/2005
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Application #:
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10770673
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Filing Dt:
|
02/02/2004
|
|
Title:
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BITLINE HARD MASK SPACER FLOW FOR MEMORY CELL SCALING
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|
|
|
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Patent #:
|
|
Issue Dt:
|
03/28/2006
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Application #:
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10818112
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Filing Dt:
|
04/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
|
Title:
|
UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BIT FLASH MEMORY DEVICES IN BEOL PROCESSING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
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10821312
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Filing Dt:
|
04/08/2004
|
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Title:
|
NARROW WIDE SPACER
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|
|
|
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Patent #:
|
|
Issue Dt:
|
08/15/2006
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Application #:
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10861437
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Filing Dt:
|
06/03/2004
|
|
Title:
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UV-BLOCKING ETCH STOP LAYER FOR REDUCING UV-INDUCED CHARGING OF CHARGE STORAGE LAYER IN MEMORY DEVICES IN BEOL PROCESSING
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|
|
|
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Patent #:
|
|
Issue Dt:
|
02/07/2006
|
Application #:
|
10869774
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Filing Dt:
|
06/16/2004
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH CORE AND PERIPHERY REGIONS
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|
