Total properties:
821
Page
8
of
9
Pages:
1 2 3 4 5 6 7 8 9
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10663621
|
Filing Dt:
|
09/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/17/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH NANOCLUSTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10668432
|
Filing Dt:
|
09/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/24/2005
| | | | |
|
Title:
|
METHOD FOR FABRICATING A MASK USING A HARDMASK AND METHOD FOR MAKING A SEMICONDUCTOR DEVICE USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10668694
|
Filing Dt:
|
09/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/24/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND MAKING THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2005
|
Application #:
|
10668714
|
Filing Dt:
|
09/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/24/2005
| | | | |
|
Title:
|
METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING ISOLATION REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10670631
|
Filing Dt:
|
09/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
METHOD OF FORMING A SEMICONDUCTOR PACKAGE AND STRUCTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2005
|
Application #:
|
10670634
|
Filing Dt:
|
09/25/2003
|
|
Title:
|
SEMICONDUCTOR PROCESS FOR DISPOSABLE SIDEWALL SPACERS AND STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10670683
|
Filing Dt:
|
09/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
|
Title:
|
MODULE, SYSTEM AND METHOD FOR TESTING A PHASE LOCKED LOOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10670928
|
Filing Dt:
|
09/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
METHOD OF MANUFACTURING SOI TEMPLATE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
10672161
|
Filing Dt:
|
09/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
METHOD AND CIRCUITRY FOR CONTROLLING SUPPLY VOLTAGE IN A DATA PROCESSING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2006
|
Application #:
|
10672487
|
Filing Dt:
|
09/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
|
Title:
|
ANALYSIS MODULE, INTEGRATED CIRCUIT, SYSTEM AND METHOD FOR TESTING AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
10672959
|
Filing Dt:
|
09/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
ACCELERATED LIFE TEST OF MRAM CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2005
|
Application #:
|
10675005
|
Filing Dt:
|
09/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
INTEGRATED CIRCUIT POWER MANAGEMENT FOR REDUCING LEAKAGE CURRENT IN CIRCUIT ARRAYS AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10677070
|
Filing Dt:
|
10/01/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
|
Title:
|
METHOD FOR FORMING A SEMICONDUCTOR DEVICE STRUCTURE A SEMICONDUCTOR LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
10677753
|
Filing Dt:
|
10/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
|
Title:
|
METHOD FOR MAKING A CLEAR CHANNEL ASSESSMENT IN A WIRELESS NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2004
|
Application #:
|
10677844
|
Filing Dt:
|
10/02/2003
|
|
Title:
|
SEMICONDUCTOR STRUCTURE WITH DIFFERENT LATTICE CONSTANT MATERIALS AND METHOD FOR FORMING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2005
|
Application #:
|
10679134
|
Filing Dt:
|
10/02/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
MRAM AND METHODS FOR READING THE MRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
10680492
|
Filing Dt:
|
10/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/08/2004
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR RAKING IN A WIRELESS NETWORK
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10682558
|
Filing Dt:
|
10/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
Communication steering for use in a multi-master shared resource system
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10682571
|
Filing Dt:
|
10/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
Communication steering for use in a multi-master shared resource system
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2009
|
Application #:
|
10682746
|
Filing Dt:
|
10/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
CELLULAR MODEM PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10683493
|
Filing Dt:
|
10/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
ARCHITECTURE FOR AN AM/FM DIGITAL INTERMEDIATE FREQUENCY RADIO
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
10683778
|
Filing Dt:
|
10/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
DATA PROCESSING SYSTEM HAVING A SERIAL DATA CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10684112
|
Filing Dt:
|
10/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND METHOD OF OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
10685561
|
Filing Dt:
|
10/14/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR DIRECT ACCESS TO A NON-MEMORY MAPPED DEVICE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
10687271
|
Filing Dt:
|
10/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
|
Title:
|
MULTI-LAYER DIELECTRIC CONTAINING DIFFUSION BARRIER MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10688228
|
Filing Dt:
|
10/14/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/29/2004
| | | | |
|
Title:
|
OPTICAL SENSOR PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2006
|
Application #:
|
10688589
|
Filing Dt:
|
10/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
|
Title:
|
ATTENUATED PHASE SHIFT MASK FOR EXTREME ULTRAVIOLET LITHOGRAPHY AND METHOD THEREFORE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10689240
|
Filing Dt:
|
10/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
|
Title:
|
AMPLIFIER CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10690060
|
Filing Dt:
|
10/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
|
Title:
|
METHOD OF FORMING A LOW K DIELECTRIC IN A SEMICONDUCTOR MANUFACTURING PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10691984
|
Filing Dt:
|
10/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10694077
|
Filing Dt:
|
10/27/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
|
Title:
|
Silicide formation for a semiconductor device
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10694146
|
Filing Dt:
|
10/27/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
|
Title:
|
ELECTROMAGNETIC NOISE SHIELDING IN SEMICONDUCTOR PACKAGES USING CAGED INTERCONNECT STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2005
|
Application #:
|
10695163
|
Filing Dt:
|
10/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
|
Title:
|
CONFINED SPACERS FOR DOUBLE GATE TRANSISTOR SEMICONDUCTOR FABRICATION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10696079
|
Filing Dt:
|
10/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
METHOD FOR FORMING MULTIPLE GATE OXIDE THICKNESS UTILIZING ASHING AND CLEANING
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10696346
|
Filing Dt:
|
10/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
Method of forming an NMOS transistor and structure thereof
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
10700883
|
Filing Dt:
|
11/04/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
METHOD OF IMPLEMENTING POLISHING UNIFORMITY AND MODIFYING LAYOUT DATA
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10702909
|
Filing Dt:
|
11/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
Compositions and methods for the electroless deposition of NiFe on a work piece
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10703657
|
Filing Dt:
|
11/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
|
Title:
|
DOMINO COMPARATOR CAPABLE FOR USE IN A MEMORY ARRAY
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10703796
|
Filing Dt:
|
11/07/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/20/2004
| | | | |
|
Title:
|
Semiconductor device and method of formation
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
10703924
|
Filing Dt:
|
11/07/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
|
Title:
|
MEMORY CONTROLLER USEABLE IN A DATA PROCESSING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10705317
|
Filing Dt:
|
11/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
|
Title:
|
TRANSISTOR HAVING THREE ELECTRICALLY ISOLATED ELECTRODES AND METHOD OF FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2004
|
Application #:
|
10705504
|
Filing Dt:
|
11/10/2003
|
|
Title:
|
INTEGRATED CIRCUIT HAVING MULTIPLE MEMORY TYPES AND METHOD OF FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10716655
|
Filing Dt:
|
11/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH MAGNETICALLY PERMEABLE HEAT SINK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10716955
|
Filing Dt:
|
11/19/2003
|
|
Title:
|
METHOD FOR FORMING A MICROWAVE FIELD EFFECT TRANSISTOR WITH HIGH OPERATING VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10716956
|
Filing Dt:
|
11/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
|
Title:
|
MULTI-BIT NON-VOLATILE INTEGRATED CIRCUIT MEMORY AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10718891
|
Filing Dt:
|
11/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
|
Title:
|
Multistage dynamic domino circuit with internally generated delay reset clock
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
10718892
|
Filing Dt:
|
11/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH SILICIDED SOURCE/DRAINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2007
|
Application #:
|
10721196
|
Filing Dt:
|
11/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
|
Title:
|
NETWORK MESSAGE PROCESSING USING INVERSE PATTERN MATCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2009
|
Application #:
|
10721201
|
Filing Dt:
|
11/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
|
Title:
|
NETWORK MESSAGE FILTERING USING HASHING AND PATTERN MATCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
10721950
|
Filing Dt:
|
11/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
|
Title:
|
COMMUNICATION RECEIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
10728398
|
Filing Dt:
|
12/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
APPARATUS AND METHOD FOR TIME ORDERING EVENTS IN A SYSTEM HAVING MULTIPLE TIME DOMAINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10728621
|
Filing Dt:
|
12/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
METHOD AND CIRCUIT FOR MULTIPLYING SIGNALS WITH A TRANSISTOR HAVING MORE THAN ONE INDEPENDENT GATE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10728622
|
Filing Dt:
|
12/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
DERIVATION OF CIRCUIT BLOCK CONSTRAINTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2006
|
Application #:
|
10729531
|
Filing Dt:
|
12/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
INDUCTIVE DEVICE INCLUDING BOND WIRES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
10730174
|
Filing Dt:
|
12/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
HARDWARE FOR PERFORMING AN ARITHMETIC FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2009
|
Application #:
|
10730230
|
Filing Dt:
|
12/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
METHOD OF FORMING A SEAL FOR A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10730239
|
Filing Dt:
|
12/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
MRAM DEVICE INTEGRATED WITH OTHER TYPES OF CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
10730387
|
Filing Dt:
|
12/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR CONTROLLING THE BANDWIDTH FREQUENCY OF AN ANALOG FILTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2009
|
Application #:
|
10730449
|
Filing Dt:
|
12/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR DYNAMICALLY INSERTING GAIN IN AN ADAPTIVE FILTER SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
10731069
|
Filing Dt:
|
12/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
ADAPTIVE TRANSMIT POWER CONTROL SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10731831
|
Filing Dt:
|
12/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
LAND GRID ARRAY PACKAGED DEVICE AND METHOD OF FORMING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2008
|
Application #:
|
10731850
|
Filing Dt:
|
12/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS TO IMPLEMENT DC OFFSET CORRECTION IN A SIGMA DELTA CONVERTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2005
|
Application #:
|
10734435
|
Filing Dt:
|
12/12/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR FORMING AN SOI BODY-CONTACTED TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10736393
|
Filing Dt:
|
12/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR ALLOCATING ENTRIES IN A BRANCH TARGET BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
10736395
|
Filing Dt:
|
12/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
|
Title:
|
METHOD FOR REDUCING CORROSION OF METAL SURFACES DURING SEMICONDUCTOR PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
10736852
|
Filing Dt:
|
12/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/30/2005
| | | | |
|
Title:
|
MRAM HAVING ERROR CORRECTION CODE CIRCUITRY AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10736853
|
Filing Dt:
|
12/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
|
Title:
|
METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING A LOW K DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10737114
|
Filing Dt:
|
12/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
|
Title:
|
REDUCING POWER CONSUMPTION DURING MRAM WRITES USING MULTIPLE CURRENT LEVELS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10737115
|
Filing Dt:
|
12/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
|
Title:
|
METHOD FOR ELIMINATION OF EXCESSIVE FIELD OXIDE RECESS FOR THIN SI SOI
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2005
|
Application #:
|
10737116
|
Filing Dt:
|
12/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
INTEGRATED CIRCUIT DEVICE AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
10738433
|
Filing Dt:
|
12/17/2003
|
|
Title:
|
GLITCH REMOVAL CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
10738815
|
Filing Dt:
|
12/17/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
SLOTTED PLANAR POWER CONDUCTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/2009
|
Application #:
|
10739505
|
Filing Dt:
|
12/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR DEMODULATING A RECEIVED SIGNAL WITHIN A CODED SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2006
|
Application #:
|
10739605
|
Filing Dt:
|
12/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
STACKED SEMICONDUCTOR DEVICE ASSEMBLY AND METHOD FOR FORMING
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10739684
|
Filing Dt:
|
12/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
Blocking layer for silicide uniformity in a semiconductor transistor
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10740157
|
Filing Dt:
|
12/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR REDUCING INTERRUPT LATENCY BY DYNAMIC BUFFER SIZING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
10740303
|
Filing Dt:
|
12/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
WARPAGE CONTROL OF ARRAY PACKAGING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2005
|
Application #:
|
10740338
|
Filing Dt:
|
12/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
SYNTHETIC ANTIFERROMAGNET STRUCTURES FOR USE IN MTJS IN MRAM TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10741055
|
Filing Dt:
|
12/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
|
Title:
|
CIRCUIT AND METHOD FOR SUPPLYING AN ELECTRICAL A.C. LOAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
10741065
|
Filing Dt:
|
12/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/08/2004
| | | | |
|
Title:
|
MULTI-STRAND SUBSTRATE FOR BALL-GRID ARRAY ASSEMBLIES AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
10744619
|
Filing Dt:
|
12/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
BTSC ENCODER AND INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
10746014
|
Filing Dt:
|
12/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
APPARATUS FOR PULSE TESTING A MRAM DEVICE AND METHOD THEREFORE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
10747748
|
Filing Dt:
|
12/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/07/2005
| | | | |
|
Title:
|
LEVEL SHIFTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2005
|
Application #:
|
10752159
|
Filing Dt:
|
01/06/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/07/2005
| | | | |
|
Title:
|
METHOD OF PACKAGING AN OPTICAL SENSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10752866
|
Filing Dt:
|
01/07/2004
|
|
Title:
|
FLIPCHIP QFN PACKAGE AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
10761158
|
Filing Dt:
|
01/20/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/21/2005
| | | | |
|
Title:
|
DIGITAL RATE CONVERTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2005
|
Application #:
|
10764110
|
Filing Dt:
|
01/23/2004
|
|
Title:
|
REAL-TIME DEBUG SUPPORT FOR A DMA DEVICE AND METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
10765804
|
Filing Dt:
|
01/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
|
Title:
|
METHOD FOR FORMING A MEMORY STRUCTURE USING A MODIFIED SURFACE TOPOGRAPHY AND STRUCTURE THEREOF
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10765810
|
Filing Dt:
|
01/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
|
Title:
|
Integrated circuit with conductive grid for power distribution
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10766205
|
Filing Dt:
|
01/28/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
|
Title:
|
METHOD FOR ETCHING A QUARTZ LAYER IN A PHOTORESISTLESS SEMICONDUCTOR MASK
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10767994
|
Filing Dt:
|
02/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10767996
|
Filing Dt:
|
02/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10767998
|
Filing Dt:
|
02/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10768108
|
Filing Dt:
|
02/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR DEVICE, COMMUNICATING DEVICE, INTEGRATED CIRCUIT, AND PROCESS FOR FABRICATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10769228
|
Filing Dt:
|
01/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/23/2004
| | | | |
|
Title:
|
MULTI-BIT NON-VOLATILE MEMORY DEVICE AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10770149
|
Filing Dt:
|
02/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
|
Title:
|
VOLTAGE REGULATOR WITH IMPROVED LOAD REGULATION USING ADAPTIVE BIASING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
10771855
|
Filing Dt:
|
02/04/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
|
Title:
|
METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH LOCAL SEMICONDUCTOR-ON-INSULATOR (SOI)
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10774130
|
Filing Dt:
|
02/06/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/11/2005
| | | | |
|
Title:
|
Bidirectional level shifter
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10774977
|
Filing Dt:
|
02/09/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/11/2005
| | | | |
|
Title:
|
DIE ENCAPSULATION USING A POROUS CARRIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
10779004
|
Filing Dt:
|
02/13/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/19/2004
| | | | |
|
Title:
|
NON-VOLATILE MEMORY DEVICE WITH IMPROVED DATA RETENTION AND METHOD THEREFOR
|
|
