Total properties:
35
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10282459
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Filing Dt:
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10/29/2002
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Title:
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BUFFER DRIVER CIRCUIT FOR PRODUCING A FAST, STABLE, AND ACCURATE REFERENCE VOLTAGE
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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10288871
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Filing Dt:
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11/05/2002
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Title:
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METHOD OF ALTERNATING GROUNDED/FLOATING POLY LINES TO MONITOR SHORTS
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10292121
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Filing Dt:
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11/12/2002
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Title:
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FABRICATION OF SHALLOW TRENCH ISOLATION STRUCTURES WITH ROUNDED CORNER AND SELF-ALIGNED GATE
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10302672
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Filing Dt:
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11/22/2002
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Publication #:
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Pub Dt:
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05/27/2004
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Title:
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CASCODE AMPLIFIER CIRCUIT FOR PRODUCING A FAST, STABLE AND ACCURATE BIT LINE VOLTAGE
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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10306080
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Filing Dt:
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11/26/2002
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Title:
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MEMORY CIRCUIT FOR SUPPRESSING BIT LINE CURRENT LEAKAGE
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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10313444
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Filing Dt:
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12/05/2002
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Title:
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CIRCUIT FOR ACCURATE MEMORY READ OPERATIONS
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Patent #:
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Issue Dt:
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05/18/2004
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Application #:
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10313454
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Filing Dt:
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12/05/2002
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Title:
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STRUCTURE AND METHOD FOR REDUCING CHARGE LOSS IN A MEMORY CELL
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10313676
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Filing Dt:
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12/05/2002
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Title:
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EFFICIENT METHOD TO DETECT PROCESS INDUCED DEFECTS IN THE GATE STACK OF FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10315458
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Filing Dt:
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12/09/2002
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Title:
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DISCONTINUOUS NITRIDE STRUCTURE FOR NON-VOLATILE TRANSISTORS
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10320910
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Filing Dt:
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12/17/2002
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Title:
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DIFFERENTIALLY MIS-ALIGNED CONTACTS IN FLASH ARRAYS TO CALIBRATE FAILURE MODES
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10342032
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Filing Dt:
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01/14/2003
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Title:
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FLASH MEMORY DEVICES WITH OXYNITRIDE DIELECTRIC AS THE CHARGE STORAGE MEDIA
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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10348732
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Filing Dt:
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01/21/2003
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Title:
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MEMORY CIRCUIT ARRANGEMENT FOR PROGRAMMING A MEMORY CELL
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10352658
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Filing Dt:
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01/28/2003
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Title:
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NOVEL NON-VOLATILE MEMORY CELL AND METHOD OF PROGRAMMING FOR IMPROVED DATA RETENTION
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10361378
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Filing Dt:
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02/10/2003
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Title:
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SELECTION CIRCUIT FOR ACCURATE MEMORY READ OPERATIONS
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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10361455
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Filing Dt:
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02/10/2003
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Title:
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METHOD FOR FABRICATING DEVICES IN CORE AND PERIPHERY SEMICONDUCTOR REGIONS USING DUAL SPACERS
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10364569
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Filing Dt:
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02/10/2003
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Title:
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STRUCTURE AND METHOD FOR SUPPRESSING OXIDE ENCROACHMENT IN A FLOATING GATE MEMORY CELL
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10382731
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Filing Dt:
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03/05/2003
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Title:
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MEMORY ARRAY HAVING SHALLOW BIT LINE WITH SILICIDE CONTACT PORTION AND METHOD OF FORMATION
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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10384856
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Filing Dt:
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03/10/2003
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Title:
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METHOD AND SYSTEM FOR APPLYING TESTING VOLTAGE SIGNAL
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10384936
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Filing Dt:
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03/10/2003
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Title:
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METHOD AND SYSTEM FOR DETECTING DEFECTIVE MATERIAL SURROUNDING FLASH MEMORY CELLS
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10387617
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Filing Dt:
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03/13/2003
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Title:
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CIRCUIT FOR FAST AND ACCURATE MEMORY READ OPERATIONS
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Patent #:
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Issue Dt:
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11/08/2005
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Application #:
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10459576
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Filing Dt:
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06/12/2003
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Publication #:
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Pub Dt:
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12/16/2004
| | | | |
Title:
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NON-VOLATILE MEMORY DEVICE
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Patent #:
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Issue Dt:
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04/04/2006
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Application #:
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10617450
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Filing Dt:
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07/11/2003
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Publication #:
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Pub Dt:
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01/13/2005
| | | | |
Title:
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UNDOPED OXIDE LINER/BPSG FOR IMPROVED DATA RETENTION
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10617451
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Filing Dt:
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07/11/2003
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Publication #:
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Pub Dt:
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01/13/2005
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Title:
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PECVD SILICON-RICH OXIDE LAYER FOR REDUCED UV CHARGING
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10618156
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Filing Dt:
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07/11/2003
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Title:
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MEMORY STRUCTURE HAVING TUNABLE INTERLAYER DIELECTRIC AND METHOD FOR FABRICATING SAME
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Patent #:
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|
Issue Dt:
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06/13/2006
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Application #:
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10635089
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Filing Dt:
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08/06/2003
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Title:
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MEMORY DEVICE AND METHOD OF SIMULTANEOUS FABRICATION OF CORE AND PERIPHERY OF SAME
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Patent #:
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Issue Dt:
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01/17/2006
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Application #:
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10635781
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Filing Dt:
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08/06/2003
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Title:
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MEMORY DEVICE HAVING SILICIDED BITLINES AND METHOD OF FORMING THE SAME
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Patent #:
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Issue Dt:
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05/24/2005
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Application #:
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10636162
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Filing Dt:
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08/07/2003
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Title:
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TEST STRUCTURE FOR DETERMINING ELECTROMIGRATION AND INTERLAYER DIELECTRIC FAILURE
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Patent #:
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Issue Dt:
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11/08/2005
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Application #:
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10683631
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Filing Dt:
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10/10/2003
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Title:
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RECESSED CHANNEL
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Patent #:
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|
Issue Dt:
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06/07/2005
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Application #:
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10684890
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Filing Dt:
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10/14/2003
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Title:
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NON VOLATILE CHARGE TRAPPING DIELECTRIC MEMORY CELL STRUCTURE WITH GATE HOLE INJECTION ERASE
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Patent #:
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|
Issue Dt:
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03/22/2005
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Application #:
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10701780
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Filing Dt:
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11/05/2003
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Title:
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METHOD AND STRUCTURE FOR PROTECTING NROM DEVICES FROM INDUCED CHARGE DAMAGE DURING DEVICE FABRICATION
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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10726508
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Filing Dt:
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12/04/2003
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Publication #:
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Pub Dt:
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06/09/2005
| | | | |
Title:
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FLASH MEMORY DEVICE
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|
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Patent #:
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|
Issue Dt:
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10/25/2005
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Application #:
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10770010
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Filing Dt:
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02/03/2004
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Title:
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NON -VOLATILE MEMORY DEVICE
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Patent #:
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|
Issue Dt:
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03/28/2006
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Application #:
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10770245
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Filing Dt:
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02/02/2004
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Title:
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DISPOSABLE HARD MASK FOR MEMORY BITLINE SCALING
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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10819162
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Filing Dt:
|
04/07/2004
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Title:
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FLASH MEMORY DEVICE AND METHOD OF FORMING THE SAME WITH IMPROVED GATE BREAKDOWN AND ENDURANCE
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Patent #:
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Issue Dt:
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04/26/2005
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Application #:
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10844116
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Filing Dt:
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05/12/2004
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Title:
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CASCODE AMPLIFIER CIRCUIT FOR GENERATING AND MAINTAINING A FAST, STABLE AND ACCURATE BIT LINE VOLTAGE
|
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