Total properties:
41
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Patent #:
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Issue Dt:
|
06/16/2015
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Application #:
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14151935
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Filing Dt:
|
01/10/2014
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Title:
|
LATERAL SILICON-ON-INSULATOR BIPOLAR JUNCTION TRANSISTOR PROCESS AND STRUCTURE
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Patent #:
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Issue Dt:
|
01/05/2016
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Application #:
|
14179121
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Filing Dt:
|
02/12/2014
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Publication #:
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Pub Dt:
|
08/13/2015
| | | | |
Title:
|
MULTI-COMPOSITION GATE DIELECTRIC FIELD EFFECT TRANSISTORS
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|
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Patent #:
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Issue Dt:
|
04/12/2016
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Application #:
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14185440
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Filing Dt:
|
02/20/2014
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Publication #:
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Pub Dt:
|
08/20/2015
| | | | |
Title:
|
MASK THAT PROVIDES IMPROVED FOCUS CONTROL USING ORTHOGONAL EDGES
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Patent #:
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|
Issue Dt:
|
07/05/2016
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Application #:
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14272691
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Filing Dt:
|
05/08/2014
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Publication #:
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Pub Dt:
|
11/12/2015
| | | | |
Title:
|
Sublithographic Kelvin Structure Patterned With DSA
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|
|
Patent #:
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|
Issue Dt:
|
10/04/2016
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Application #:
|
14323164
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Filing Dt:
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07/03/2014
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Publication #:
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Pub Dt:
|
01/07/2016
| | | | |
Title:
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PHOTODETECTOR AND METHOD OF FORMING THE PHOTODETECTOR ON STACKED TRENCH ISOLATION REGIONS
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|
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Patent #:
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Issue Dt:
|
05/02/2017
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Application #:
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14569005
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Filing Dt:
|
12/12/2014
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Publication #:
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Pub Dt:
|
06/16/2016
| | | | |
Title:
|
COMPARATIVE ESD POWER CLAMP
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Patent #:
|
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Issue Dt:
|
12/27/2016
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Application #:
|
14578768
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Filing Dt:
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12/22/2014
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Publication #:
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Pub Dt:
|
06/23/2016
| | | | |
Title:
|
III-V MOSFETS With Halo-Doped Bottom Barrier Layer
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
14608257
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Filing Dt:
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01/29/2015
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Publication #:
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Pub Dt:
|
05/28/2015
| | | | |
Title:
|
HALO REGION FORMATION BY EPITAXIAL GROWTH
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|
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Patent #:
|
|
Issue Dt:
|
07/12/2016
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Application #:
|
14614489
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Filing Dt:
|
02/05/2015
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Title:
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METHOD OF FORMING A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR STRUCTURE WITH N-TYPE AND P-TYPE FIELD EFFECT TRANSISTORS HAVING SYMMETRIC SOURCE/DRAIN JUNCTIONS AND OPTIONAL DUAL SILICIDES
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|
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Patent #:
|
|
Issue Dt:
|
01/31/2017
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Application #:
|
14659749
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Filing Dt:
|
03/17/2015
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Publication #:
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Pub Dt:
|
09/22/2016
| | | | |
Title:
|
SILICIDED NANOWIRES FOR NANOBRIDGE WEAK LINKS
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|
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Patent #:
|
|
Issue Dt:
|
09/05/2017
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Application #:
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14665242
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Filing Dt:
|
03/23/2015
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Publication #:
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|
Pub Dt:
|
12/03/2015
| | | | |
Title:
|
METHOD OF CHECKING THE LAYOUT INTEGRITY
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|
|
Patent #:
|
|
Issue Dt:
|
07/19/2016
|
Application #:
|
14677460
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Filing Dt:
|
04/02/2015
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
LATERAL SILICON-ON-INSULATOR BIPOLAR JUNCTION TRANSISTOR PROCESS AND STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2017
|
Application #:
|
14685944
|
Filing Dt:
|
04/14/2015
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Publication #:
|
|
Pub Dt:
|
10/20/2016
| | | | |
Title:
|
REPLACEMENT CHANNEL TFET
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2017
|
Application #:
|
14691270
|
Filing Dt:
|
04/20/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
FORMATION OF LARGE SCALE SINGLE CRYSTALLINE GRAPHENE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2016
|
Application #:
|
14694243
|
Filing Dt:
|
04/23/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
METHOD OF MANUFACTURING A FINFET DEVICE USING A SACRIFICIAL EPITAXY REGION FOR IMPROVED FIN MERGE AND FINFET DEVICE FORMED BY SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14696015
|
Filing Dt:
|
04/24/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
ENABLING ENHANCED RELIABILITY AND MOBILITY FOR REPLACEMENT GATE PLANAR AND FINFET STRUCTURES
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|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
14697670
|
Filing Dt:
|
04/28/2015
|
Publication #:
|
|
Pub Dt:
|
08/27/2015
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING FINFET AND DIODE HAVING REDUCED DEFECTS IN DEPLETION REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2016
|
Application #:
|
14698206
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Filing Dt:
|
04/28/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2016
|
Application #:
|
14699557
|
Filing Dt:
|
04/29/2015
|
Publication #:
|
|
Pub Dt:
|
10/08/2015
| | | | |
Title:
|
COLORIMETRIC RADIATION DOSIMETRY BASED ON FUNCTIONAL POLYMER AND NANOPARTICLE HYBRID
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|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
14699920
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Filing Dt:
|
04/29/2015
|
Publication #:
|
|
Pub Dt:
|
08/20/2015
| | | | |
Title:
|
PHYSICAL UNCLONABLE FUNCTION GENERATION AND MANAGEMENT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14708350
|
Filing Dt:
|
05/11/2015
|
Publication #:
|
|
Pub Dt:
|
08/27/2015
| | | | |
Title:
|
JOINING A CHIP TO A SUBSTRATE WITH SOLDER ALLOYS HAVING DIFFERENT REFLOW TEMPERATURES
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|
|
Patent #:
|
|
Issue Dt:
|
07/25/2017
|
Application #:
|
14733398
|
Filing Dt:
|
06/08/2015
|
Publication #:
|
|
Pub Dt:
|
12/08/2016
| | | | |
Title:
|
ELECTRONIC DEVICE INCLUDING MOAT POWER METALLIZATION IN TRENCH
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14734698
|
Filing Dt:
|
06/09/2015
|
Publication #:
|
|
Pub Dt:
|
12/17/2015
| | | | |
Title:
|
METHOD AND PROTECTION APPARATUS FOR PROTECTING A THERMAL SENSITIVE COMPONENT IN A THERMAL PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2016
|
Application #:
|
14753628
|
Filing Dt:
|
06/29/2015
|
Title:
|
ELECTROSTATIC DISCHARGE AND PASSIVE STRUCTURES INTEGRATED IN A VERITCAL GATE FIN-TYPE FIELD EFFECT DIODE
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|
|
Patent #:
|
|
Issue Dt:
|
09/12/2017
|
Application #:
|
14753768
|
Filing Dt:
|
06/29/2015
|
Publication #:
|
|
Pub Dt:
|
12/29/2016
| | | | |
Title:
|
WAFER RIGIDITY WITH REINFORCEMENT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2017
|
Application #:
|
14754958
|
Filing Dt:
|
06/30/2015
|
Publication #:
|
|
Pub Dt:
|
01/05/2017
| | | | |
Title:
|
INTEGRATED CIRCUIT STRUCTURE WITH METHODS OF ELECTRICALLY CONNECTING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2018
|
Application #:
|
14755440
|
Filing Dt:
|
06/30/2015
|
Publication #:
|
|
Pub Dt:
|
01/05/2017
| | | | |
Title:
|
METHOD TO REDUCE RESISTANCE FOR A COPPER (CU) INTERCONNECT LANDING ON MULTILAYERED METAL CONTACTS, AND SEMICONDUCTOR STRUCTURES FORMED THEREFROM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2017
|
Application #:
|
14755621
|
Filing Dt:
|
06/30/2015
|
Publication #:
|
|
Pub Dt:
|
01/05/2017
| | | | |
Title:
|
NETWORK CLOCK SYNCHRONIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2019
|
Application #:
|
14755733
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Filing Dt:
|
06/30/2015
|
Publication #:
|
|
Pub Dt:
|
01/05/2017
| | | | |
Title:
|
ORGANIC PROBE SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2018
|
Application #:
|
14788296
|
Filing Dt:
|
06/30/2015
|
Publication #:
|
|
Pub Dt:
|
01/05/2017
| | | | |
Title:
|
METHOD OF SIMULTANEOUS LITHOGRAPHY AND ETCH CORRECTION FLOW
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2017
|
Application #:
|
14794997
|
Filing Dt:
|
07/09/2015
|
Publication #:
|
|
Pub Dt:
|
01/12/2017
| | | | |
Title:
|
INCREASED CONTACT AREA FOR FINFETS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
14796401
|
Filing Dt:
|
07/10/2015
|
Publication #:
|
|
Pub Dt:
|
11/05/2015
| | | | |
Title:
|
Read and Write Requests to Partially Cached Files
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|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
14797982
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Filing Dt:
|
07/13/2015
|
Publication #:
|
|
Pub Dt:
|
11/05/2015
| | | | |
Title:
|
SELF-ALIGNED LINER FORMED ON METAL SEMICONDUCTOR ALLOY CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2016
|
Application #:
|
14811236
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Filing Dt:
|
07/28/2015
|
Publication #:
|
|
Pub Dt:
|
11/19/2015
| | | | |
Title:
|
Sublithographic Kelvin Structure Patterned With DSA
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2017
|
Application #:
|
14832108
|
Filing Dt:
|
08/21/2015
|
Publication #:
|
|
Pub Dt:
|
02/23/2017
| | | | |
Title:
|
FINFET PCM ACCESS TRANSISTOR HAVING GATE-WRAPPED SOURCE AND DRAIN REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2016
|
Application #:
|
14881766
|
Filing Dt:
|
10/13/2015
|
Publication #:
|
|
Pub Dt:
|
02/04/2016
| | | | |
Title:
|
MULTI-COMPOSITION GATE DIELECTRIC FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2017
|
Application #:
|
14887572
|
Filing Dt:
|
10/20/2015
|
Publication #:
|
|
Pub Dt:
|
04/20/2017
| | | | |
Title:
|
EXPITAXIALLY REGROWN HETEROSTRUCTURE NANOWIRE LATERAL TUNNEL FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2017
|
Application #:
|
14953702
|
Filing Dt:
|
11/30/2015
|
Publication #:
|
|
Pub Dt:
|
02/23/2017
| | | | |
Title:
|
FINFET PCM ACCESS TRANSISTOR HAVING GATE-WRAPPED SOURCE AND DRAIN REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2017
|
Application #:
|
14967946
|
Filing Dt:
|
12/14/2015
|
Title:
|
METHOD AND STRUCTURE FOR III-V NANOWIRE TUNNEL FETS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2018
|
Application #:
|
14970725
|
Filing Dt:
|
12/16/2015
|
Publication #:
|
|
Pub Dt:
|
06/22/2017
| | | | |
Title:
|
STRUCTURE AND METHOD FOR FULLY DEPLETED SILICON ON INSULATOR STRUCTURE FOR THRESHOLD VOLTAGE MODIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2016
|
Application #:
|
14992209
|
Filing Dt:
|
01/11/2016
|
Title:
|
Methods of Forming Multi-Vt III-V TFET Devices
|
|