skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:064805/0735   Pages: 11
Recorded: 09/05/2023
Attorney Dkt #:392739-00007
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE SPELLING OF THE ASSIGNEE'S NAME ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0161. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.
Total properties: 56
1
Patent #:
8901439
Issue Dt:
12/02/2014
Application #:
11465744
Filing Dt:
08/18/2006
Publication #:
US20080041964
Pub Dt:
02/21/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WINDOW OPENING
2
Patent #:
8852986
Issue Dt:
10/07/2014
Application #:
11749717
Filing Dt:
05/16/2007
Publication #:
US20080284066
Pub Dt:
11/20/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING RESILIENT MEMBER MOLD SYSTEM TECHNOLOGY
3
Patent #:
8847413
Issue Dt:
09/30/2014
Application #:
12014578
Filing Dt:
01/15/2008
Publication #:
US20080171405
Pub Dt:
07/17/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADS HAVING MULTIPLE SIDES EXPOSED
4
Patent #:
8841782
Issue Dt:
09/23/2014
Application #:
12192042
Filing Dt:
08/14/2008
Publication #:
US20100038804
Pub Dt:
02/18/2010
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLD GATE
5
Patent #:
8823160
Issue Dt:
09/02/2014
Application #:
12197209
Filing Dt:
08/22/2008
Publication #:
US20100044878
Pub Dt:
02/25/2010
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING CAVITY
6
Patent #:
8900921
Issue Dt:
12/02/2014
Application #:
12332835
Filing Dt:
12/11/2008
Publication #:
US20100148316
Pub Dt:
06/17/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING TOPSIDE AND BOTTOM-SIDE INTERCONNECT STRUCTURES AROUND CORE DIE WITH TSV
7
Patent #:
8895358
Issue Dt:
11/25/2014
Application #:
12557763
Filing Dt:
09/11/2009
Publication #:
US20110062575
Pub Dt:
03/17/2011
Title:
Semiconductor Device and Method of Forming Cavity in PCB Containing Encapsulant or Dummy Die Having CTE Similar to CTE of Large Array WLCSP
8
Patent #:
8883559
Issue Dt:
11/11/2014
Application #:
12567033
Filing Dt:
09/25/2009
Publication #:
US20110074014
Pub Dt:
03/31/2011
Title:
Semiconductor Device and Method of Forming Adhesive Material to Secure Semiconductor Die to Carrier in WLCSP
9
Patent #:
8823466
Issue Dt:
09/02/2014
Application #:
12606351
Filing Dt:
10/27/2009
Publication #:
US20100045398
Pub Dt:
02/25/2010
Title:
MINIATURIZED WIDE-BAND BALUNS FOR RF APPLICATIONS
10
Patent #:
8916452
Issue Dt:
12/23/2014
Application #:
12612938
Filing Dt:
11/05/2009
Publication #:
US20100127360
Pub Dt:
05/27/2010
Title:
Semiconductor Device and Method of Forming WLCSP Using Wafer Sections Containing Multiple Die
11
Patent #:
8895440
Issue Dt:
11/25/2014
Application #:
12852433
Filing Dt:
08/06/2010
Publication #:
US20120032340
Pub Dt:
02/09/2012
Title:
Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV
12
Patent #:
8936971
Issue Dt:
01/20/2015
Application #:
12884102
Filing Dt:
09/16/2010
Publication #:
US20120068363
Pub Dt:
03/22/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DIE PADDLES AND METHOD OF MANUFACTURE THEREOF
13
Patent #:
8916416
Issue Dt:
12/23/2014
Application #:
12889588
Filing Dt:
09/24/2010
Publication #:
US20130127039
Pub Dt:
05/23/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF LASER-MARKING LAMINATE LAYER FORMED OVER EWLB WITH TAPE APPLIED TO OPPOSITE SURFACE
14
Patent #:
8861221
Issue Dt:
10/14/2014
Application #:
12890371
Filing Dt:
09/24/2010
Publication #:
US20120075821
Pub Dt:
03/29/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A SHIELD AND METHOD OF MANUFACTURE THEREOF
15
Patent #:
8866248
Issue Dt:
10/21/2014
Application #:
12941683
Filing Dt:
11/08/2010
Publication #:
US20110049662
Pub Dt:
03/03/2011
Title:
SEMICONDUCTOR DEVICE WITH OPTICAL SENSOR AND METHOD OF FORMING INTERCONNECT STRUCTURE ON FRONT AND BACKSIDE OF THE DEVICE
16
Patent #:
8877567
Issue Dt:
11/04/2014
Application #:
12949396
Filing Dt:
11/18/2010
Publication #:
US20120126395
Pub Dt:
05/24/2012
Title:
Semiconductor Device and Method of Forming Uniform Height Insulating Layer Over Interposer Frame as Standoff for Semiconductor Die
17
Patent #:
8853001
Issue Dt:
10/07/2014
Application #:
12959709
Filing Dt:
12/03/2010
Publication #:
US20120241984
Pub Dt:
09/27/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PAD LAYOUT FOR FLIPCHIP SEMICONDUCTOR DIE
18
Patent #:
8841779
Issue Dt:
09/23/2014
Application #:
12961027
Filing Dt:
12/06/2010
Publication #:
US20120241946
Pub Dt:
09/27/2012
Title:
Semiconductor Device and Method of Forming High Routing Density Bol Bonl and Bonp interconnect sites on substrate
19
Patent #:
8835301
Issue Dt:
09/16/2014
Application #:
13037181
Filing Dt:
02/28/2011
Publication #:
US20120217640
Pub Dt:
08/30/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BUMP STRUCTURE WITH INSULATING BUFFER LAYER TO REDUCE STRESS ON SEMICONDUCTOR WAFER
20
Patent #:
8906740
Issue Dt:
12/09/2014
Application #:
13085475
Filing Dt:
04/12/2011
Publication #:
US20110186994
Pub Dt:
08/04/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF
21
Patent #:
8883561
Issue Dt:
11/11/2014
Application #:
13098440
Filing Dt:
04/30/2011
Publication #:
US20120273960
Pub Dt:
11/01/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING TSV SEMICONDUCTOR DIE WITHIN ENCAPSULANT WITH TMV FOR VERTICAL INTERCONNECT IN POP
22
Patent #:
8878361
Issue Dt:
11/04/2014
Application #:
13195973
Filing Dt:
08/02/2011
Publication #:
US20110285002
Pub Dt:
11/24/2011
Title:
LEADLESS PACKAGE SYSTEM HAVING EXTERNAL CONTACTS
23
Patent #:
8912648
Issue Dt:
12/16/2014
Application #:
13231789
Filing Dt:
09/13/2011
Publication #:
US20120001325
Pub Dt:
01/05/2012
Title:
Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP
24
Patent #:
8921983
Issue Dt:
12/30/2014
Application #:
13235413
Filing Dt:
09/18/2011
Publication #:
US20120001326
Pub Dt:
01/05/2012
Title:
Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads
25
Patent #:
8912046
Issue Dt:
12/16/2014
Application #:
13284654
Filing Dt:
10/28/2011
Publication #:
US20120104585
Pub Dt:
05/03/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME AND METHOD OF MANUFACTURE THEREOF
26
Patent #:
8890328
Issue Dt:
11/18/2014
Application #:
13312852
Filing Dt:
12/06/2011
Publication #:
US20120074567
Pub Dt:
03/29/2012
Title:
Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Non-Linear Portions of Conductive Layers
27
Patent #:
8859342
Issue Dt:
10/14/2014
Application #:
13325395
Filing Dt:
12/14/2011
Publication #:
US20130154079
Pub Dt:
06/20/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUBSTRATE MOLD GATE AND METHOD OF MANUFACTURE THEREOF
28
Patent #:
8872320
Issue Dt:
10/28/2014
Application #:
13356485
Filing Dt:
01/23/2012
Publication #:
US20120119361
Pub Dt:
05/17/2012
Title:
Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure
29
Patent #:
8853855
Issue Dt:
10/07/2014
Application #:
13422649
Filing Dt:
03/16/2012
Publication #:
US20130241053
Pub Dt:
09/19/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND MOLDED CAVITIES AND METHOD OF MANUFACTURE THEREOF
30
Patent #:
8901755
Issue Dt:
12/02/2014
Application #:
13425349
Filing Dt:
03/20/2012
Publication #:
US20130249104
Pub Dt:
09/26/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE LAYER OVER METAL SUBSTRATE FOR ELECTRICAL INTERCONNECT OF SEMICONDUCTOR DIE
31
Patent #:
8936969
Issue Dt:
01/20/2015
Application #:
13426416
Filing Dt:
03/21/2012
Publication #:
US20130249079
Pub Dt:
09/26/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF SINGULATING SEMICONDUCTOR WAFER ALONG MODIFIED REGION WITHIN NON-ACTIVE REGION FORMED BY IRRADIATING ENERGY THROUGH MOUNTING TAPE
32
Patent #:
8900929
Issue Dt:
12/02/2014
Application #:
13426561
Filing Dt:
03/21/2012
Publication #:
US20130249080
Pub Dt:
09/26/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING OPENINGS AND TRENCHES IN INSULATING LAYER BY FIRST LDA AND SECOND LDA FOR RDL FORMATION
33
Patent #:
8921127
Issue Dt:
12/30/2014
Application #:
13426576
Filing Dt:
03/21/2012
Publication #:
US20130248859
Pub Dt:
09/26/2013
Title:
Semiconductor Device and Method of Simultaneous Testing of Multiple Interconnects for Electro-Migration
34
Patent #:
8841173
Issue Dt:
09/23/2014
Application #:
13427598
Filing Dt:
03/22/2012
Publication #:
US20130099365
Pub Dt:
04/25/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME LEAD ARRAY ROUTING AND METHOD OF MANUFACTURE THEREOF
35
Patent #:
8901734
Issue Dt:
12/02/2014
Application #:
13438402
Filing Dt:
04/03/2012
Publication #:
US20120187559
Pub Dt:
07/26/2012
Title:
Semiconductor Device and Method of Forming Column Interconnect Structure to Reduce Wafer Stress
36
Patent #:
8896115
Issue Dt:
11/25/2014
Application #:
13438463
Filing Dt:
04/03/2012
Publication #:
US20120187531
Pub Dt:
07/26/2012
Title:
Semiconductor Device and Method of Forming Shielding Layer Around Back Surface and Sides of Semiconductor Wafer Containing IPD Structure
37
Patent #:
8907476
Issue Dt:
12/09/2014
Application #:
13446664
Filing Dt:
04/13/2012
Publication #:
US20120199965
Pub Dt:
08/09/2012
Title:
Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation
38
Patent #:
8866294
Issue Dt:
10/21/2014
Application #:
13536177
Filing Dt:
06/28/2012
Publication #:
US20120261818
Pub Dt:
10/18/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING BUMPS FORMED ON SEMICONDUCTOR DIE INTO PENETRABLE ADHESIVE LAYER TO REDUCE DIE SHIFTING DURING ENCAPSULATION
39
Patent #:
8846454
Issue Dt:
09/30/2014
Application #:
13555531
Filing Dt:
07/23/2012
Publication #:
US20120286422
Pub Dt:
11/15/2012
Title:
Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die having Pre-Applied Protective Layer
40
Patent #:
8884418
Issue Dt:
11/11/2014
Application #:
13606451
Filing Dt:
09/07/2012
Publication #:
US20140284788
Pub Dt:
09/25/2014
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PIP WITH INNER KNOWN GOOD DIE INTERCONNECTED WITH CONDUCTIVE BUMPS
41
Patent #:
8836114
Issue Dt:
09/16/2014
Application #:
13679792
Filing Dt:
11/16/2012
Publication #:
US20130075919
Pub Dt:
03/28/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING FO-WLCSP HAVING CONDUCTIVE LAYERS AND CONDUCTIVE VIAS SEPARATED BY POLYMER LAYERS
42
Patent #:
8896109
Issue Dt:
11/25/2014
Application #:
13684055
Filing Dt:
11/21/2012
Publication #:
US20130075903
Pub Dt:
03/28/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DIFFERENT HEIGHT CONDUCTIVE PILLARS TO ELECTRICALLY INTERCONNECT STACKED LATERALLY OFFSET SEMICONDUCTOR DIE
43
Patent #:
8907498
Issue Dt:
12/09/2014
Application #:
13691440
Filing Dt:
11/30/2012
Publication #:
US20130087897
Pub Dt:
04/11/2013
Title:
Semiconductor Device and Method of Forming a Shielding Layer Between Stacked Semiconductor Die
44
Patent #:
8932907
Issue Dt:
01/13/2015
Application #:
13714061
Filing Dt:
12/13/2012
Publication #:
US20130099378
Pub Dt:
04/25/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER FRAME ELECTRICALLY CONNECTED TO EMBEDDED SEMICONDUCTOR DIE
45
Patent #:
8921161
Issue Dt:
12/30/2014
Application #:
13732150
Filing Dt:
12/31/2012
Publication #:
US20130119559
Pub Dt:
05/16/2013
Title:
Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected through Conductive Vias Formed in Encapsulant Around Die
46
Patent #:
8878359
Issue Dt:
11/04/2014
Application #:
13766493
Filing Dt:
02/13/2013
Publication #:
US20130147019
Pub Dt:
06/13/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER AROUND SEMICONDUCTOR DIE
47
Patent #:
8866275
Issue Dt:
10/21/2014
Application #:
13766646
Filing Dt:
02/13/2013
Publication #:
US20130154076
Pub Dt:
06/20/2013
Title:
LEADFRAME INTERPOSER OVER SEMICONDUCTOR DIE AND TSV SUBSTRATE FOR VERTICAL ELECTRICAL INTERCONNECT
48
Patent #:
8836097
Issue Dt:
09/16/2014
Application #:
13769302
Filing Dt:
02/16/2013
Publication #:
US20130200527
Pub Dt:
08/08/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PRE-MOLDED SUBSTRATE TO REDUCE WARPAGE DURING DIE MOLDING
49
Patent #:
8912650
Issue Dt:
12/16/2014
Application #:
13846742
Filing Dt:
03/18/2013
Publication #:
US20130228919
Pub Dt:
09/05/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE COATING OVER INTERCONNECT STRUCTURE TO INHIBIT SURFACE OXIDATION
50
Patent #:
8896133
Issue Dt:
11/25/2014
Application #:
13870928
Filing Dt:
04/25/2013
Publication #:
US20130234324
Pub Dt:
09/12/2013
Title:
Semiconductor Device and Method of Forming Vertically Offset Conductive Pillars Over First Substrate Aligned to Vertically Offset BOT Interconnect Sites Formed Over Second Substrate
51
Patent #:
8932908
Issue Dt:
01/13/2015
Application #:
13896635
Filing Dt:
05/17/2013
Publication #:
US20130249090
Pub Dt:
09/26/2013
Title:
Semiconductor Device and Method of Forming Partially-Etched Conductive Layer Recessed Within Substrate for Bonding to Semiconductor Die
52
Patent #:
8884339
Issue Dt:
11/11/2014
Application #:
13906844
Filing Dt:
05/31/2013
Publication #:
US20130264705
Pub Dt:
10/10/2013
Title:
SEMICONDUCTOR DEVICE WITH BUMP FORMED ON SUBSTRATE TO PREVENT ELK ILD DELAMINATION DURING REFLOW PROCESS
53
Patent #:
8937371
Issue Dt:
01/20/2015
Application #:
13935312
Filing Dt:
07/03/2013
Publication #:
US20130292804
Pub Dt:
11/07/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SHIELDING LAYER OVER A SEMICONDUCTOR DIE DISPOSED IN A CAVITY OF AN INTERCONNECT STRUCTURE AND GROUNDED THROUGH THE DIE TSV
54
Patent #:
8823182
Issue Dt:
09/02/2014
Application #:
13935963
Filing Dt:
07/05/2013
Publication #:
US20130292850
Pub Dt:
11/07/2013
Title:
Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant
55
Patent #:
8890315
Issue Dt:
11/18/2014
Application #:
14021056
Filing Dt:
09/09/2013
Publication #:
US20140008791
Pub Dt:
01/09/2014
Title:
Semiconductor Device and Method of Forming Interconnect Structure Over Seed Layer on Contact Pad of Semiconductor Die Without Undercutting Seed Layer Beneath Interconnect Structure
56
Patent #:
8884430
Issue Dt:
11/11/2014
Application #:
14258300
Filing Dt:
04/22/2014
Publication #:
US20140225257
Pub Dt:
08/14/2014
Title:
Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
Assignor
1
STATS CHIPPAC LTD.
Exec Dt:
03/29/2016
Assignee
1
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 23
SINGAPORE, SINGAPORE
Correspondence name and address
DARIA DELIZIO
1919 PENNSYLVANIA AVE., SUITE 800
WASHINGTON, DC 20006

Search Results as of: 05/23/2024 06:45 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT