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|
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Patent #:
|
|
Issue Dt:
|
10/04/2011
|
Application #:
|
12763390
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Filing Dt:
|
04/20/2010
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|
Publication #:
|
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Pub Dt:
|
08/12/2010
| | | | |
|
Title:
|
GROOVING BUMPED WAFER PRE-UNDERFILL SYSTEM
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Patent #:
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|
Issue Dt:
|
02/05/2013
|
Application #:
|
12764805
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Filing Dt:
|
04/21/2010
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Publication #:
|
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Pub Dt:
|
10/27/2011
| | | | |
|
Title:
|
SEMICONDUCTOR METHOD OF FORMING BUMP ON SUBSTRATE TO PREVENT ELK ILD DELAMINATION DURING REFLOW PROCESS
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Patent #:
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|
Issue Dt:
|
11/29/2016
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Application #:
|
12766607
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Filing Dt:
|
04/23/2010
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|
Publication #:
|
|
Pub Dt:
|
10/27/2011
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Openings in Thermally-Conductive Frame of FO-WLCSP to Dissipate Heat and Reduce Package Height
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|
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|
Patent #:
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|
Issue Dt:
|
03/22/2011
|
Application #:
|
12767670
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Filing Dt:
|
04/26/2010
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|
Publication #:
|
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Pub Dt:
|
08/12/2010
| | | | |
|
Title:
|
METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE WITH FINE PITCH LEAD FINGERS
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Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
12767693
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Filing Dt:
|
04/26/2010
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|
Publication #:
|
|
Pub Dt:
|
08/12/2010
| | | | |
|
Title:
|
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING PACKAGE STACKED OVER DIE-UP FLIP CHIP BALL GRID ARRAY PACKAGE AND HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES
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Patent #:
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|
Issue Dt:
|
03/19/2013
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Application #:
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12768177
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Filing Dt:
|
04/27/2010
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|
Publication #:
|
|
Pub Dt:
|
10/27/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADJACENT CHANNEL AND DAM MATERIAL AROUND DIE ATTACH AREA OF SUBSTRATE TO CONTROL OUTWARD FLOW OF UNDERFILL MATERIAL
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Patent #:
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|
Issue Dt:
|
09/03/2013
|
Application #:
|
12771833
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Filing Dt:
|
04/30/2010
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|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Protective Coating Material Over Semiconductor Wafer to Reduce Lamination Tape Residue
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|
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|
Patent #:
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|
Issue Dt:
|
11/01/2011
|
Application #:
|
12772128
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Filing Dt:
|
04/30/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/16/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM AND METHOD FOR MAKING THEREOF
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|
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|
Patent #:
|
|
Issue Dt:
|
06/26/2012
|
Application #:
|
12772142
|
Filing Dt:
|
04/30/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
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|
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|
Patent #:
|
|
Issue Dt:
|
08/30/2016
|
Application #:
|
12773669
|
Filing Dt:
|
05/04/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Channels in Back Surface of FO-WLCSP for Heat Dissipation
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|
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|
Patent #:
|
|
Issue Dt:
|
05/12/2015
|
Application #:
|
12775170
|
Filing Dt:
|
05/06/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/02/2010
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming an Interconnect Structure for 3-D Devices Using Encapsulant for Structural Support
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2011
|
Application #:
|
12775188
|
Filing Dt:
|
05/06/2010
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR 3-D DEVICES USING ENCAPSULANT FOR STRUCTURAL SUPPORT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
12775324
|
Filing Dt:
|
05/06/2010
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH VIAS WITH REFLOWED CONDUCTIVE MATERIAL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
12775338
|
Filing Dt:
|
05/06/2010
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH VIAS WITH REFLOWED CONDUCTIVE MATERIAL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12777023
|
Filing Dt:
|
05/10/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/02/2010
| | | | |
|
Title:
|
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
12777415
|
Filing Dt:
|
05/11/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH REINFORCED ENCAPSULANT HAVING EMBEDDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12777615
|
Filing Dt:
|
05/11/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COIN BONDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
|
Application #:
|
12779781
|
Filing Dt:
|
05/13/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING BUMPS FORMED ON SEMICONDUCTOR DIE INTO PENETRABLE ADHESIVE LAYER TO REDUCE DIE SHIFTING DURING ENCAPSULATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
12780268
|
Filing Dt:
|
05/14/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE AND MOUNTING SEMICONDUCTOR DIE IN RECESSED ENCAPSULANT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2012
|
Application #:
|
12780295
|
Filing Dt:
|
05/14/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DISCONTINUOUS ESD PROTECTION LAYERS BETWEEN SEMICONDUCTOR DIE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
01/22/2013
|
Application #:
|
12781751
|
Filing Dt:
|
05/17/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED MULTI-DIE LEADFRAME FOR ELECTRICAL INTERCONNECT OF STACKED SEMICONDUCTOR DIE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2015
|
Application #:
|
12781754
|
Filing Dt:
|
05/17/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
|
Title:
|
METHOD OF FORMING PERFORATED OPENING IN BOTTOM SUBSTRATE OF FLIPCHIP POP ASSEMBLY TO REDUCE BLEEDING OF UNDERFILL MATERIAL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12781772
|
Filing Dt:
|
05/17/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/09/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT HEAT SPREADER STACKING SYSTEM
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12782164
|
Filing Dt:
|
05/18/2010
|
|
Publication #:
|
|
Pub Dt:
|
10/13/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH LEAD OVERLAP AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2011
|
Application #:
|
12782992
|
Filing Dt:
|
05/19/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/09/2010
| | | | |
|
Title:
|
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2011
|
Application #:
|
12783039
|
Filing Dt:
|
05/19/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/09/2010
| | | | |
|
Title:
|
WIRE BOND INTERCONNECTION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
12784434
|
Filing Dt:
|
05/20/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/23/2010
| | | | |
|
Title:
|
METHOD FOR MAKING A STACKED PACKAGE SEMICONDUCTOR MODULE HAVING PACKAGES STACKED IN A CAVITY IN THE MODULE SUBSTRATE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12785951
|
Filing Dt:
|
05/24/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE CONNECTION AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/15/2017
|
Application #:
|
12786008
|
Filing Dt:
|
05/24/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Ultra Thin Multi-Die Face-to-Face WLCSP
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
12787216
|
Filing Dt:
|
05/25/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EMBEDDED DIE SUPERSTRUCTURE AND METHOD OF MANUFACTURE THEREOF
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|
|
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|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
12787973
|
Filing Dt:
|
05/26/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS AND HEAT SINK OVER SEMICONDUCTOR DIE USING LEADFRAME
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|
|
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|
Patent #:
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|
Issue Dt:
|
11/22/2011
|
Application #:
|
12788785
|
Filing Dt:
|
05/27/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/16/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF STACKING SAME SIZE SEMICONDUCTOR DIE ELECTRICALLY CONNECTED THROUGH CONDUCTIVE VIA FORMED AROUND PERIPHERY OF THE DIE
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|
Patent #:
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|
Issue Dt:
|
06/04/2013
|
Application #:
|
12789077
|
Filing Dt:
|
05/27/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTIPLE ROW LEADS AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
12789203
|
Filing Dt:
|
05/27/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE CONNECTION AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
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|
Issue Dt:
|
07/10/2012
|
Application #:
|
12789456
|
Filing Dt:
|
05/28/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/23/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HONEYCOMB MOLDING
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|
|
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|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
12791867
|
Filing Dt:
|
06/02/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/01/2016
|
Application #:
|
12792031
|
Filing Dt:
|
06/02/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming EMI Shielding Layer with Conductive Material Around Semiconductor Die
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12792066
|
Filing Dt:
|
06/02/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED EMI SHIELDING FRAME WITH CAVITIES CONTAINING PENETRABLE MATERIAL OVER SEMICONDUCTOR DIE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
10/18/2011
|
Application #:
|
12792629
|
Filing Dt:
|
06/02/2010
|
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUNDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/19/2016
|
Application #:
|
12794598
|
Filing Dt:
|
06/04/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Sacrificial Adhesive Over Contact Pads of Semiconductor Die
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12794612
|
Filing Dt:
|
06/04/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THERMALLY CONDUCTIVE LAYER BETWEEN SEMICONDUCTOR DIE AND BUILD-UP INTERCONNECT STRUCTURE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2012
|
Application #:
|
12796668
|
Filing Dt:
|
06/08/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTIPART CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2012
|
Application #:
|
12797922
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Filing Dt:
|
06/10/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DEVICE UNITS AND METHOD FOR MANUFACTURING THEREOF
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|
|
|
Patent #:
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|
Issue Dt:
|
08/06/2013
|
Application #:
|
12813315
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Filing Dt:
|
06/10/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
|
Title:
|
SYSTEM-IN-PACKAGE HAVING INTEGRATED PASSIVE DEVICES AND METHOD THEREFOR
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2015
|
Application #:
|
12813335
|
Filing Dt:
|
06/10/2010
|
|
Publication #:
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|
Pub Dt:
|
09/30/2010
| | | | |
|
Title:
|
Filp Chip Interconnection Structure with Bump on Partial Pad and Method Thereof
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|
|
|
|
Patent #:
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|
Issue Dt:
|
05/22/2012
|
Application #:
|
12816190
|
Filing Dt:
|
06/15/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/15/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER AROUND BACK SURFACE AND SIDES OF SEMICONDUCTOR WAFER CONTAINING IPD STRUCTURE
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|
Patent #:
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|
Issue Dt:
|
01/08/2013
|
Application #:
|
12816225
|
Filing Dt:
|
06/15/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/15/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RF FEM WITH LC FILTER AND IPD FILTER OVER SUBSTRATE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/25/2012
|
Application #:
|
12818462
|
Filing Dt:
|
06/18/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND UNDERFILL AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
12818750
|
Filing Dt:
|
06/18/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12819162
|
Filing Dt:
|
06/18/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIP CHIP MOUNTING AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
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|
Issue Dt:
|
06/19/2012
|
Application #:
|
12820491
|
Filing Dt:
|
06/22/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT SYSTEM WITH RECESSED THROUGH SILICON VIA PADS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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12821404
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Filing Dt:
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06/23/2010
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Publication #:
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Pub Dt:
|
12/29/2011
| | | | |
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Title:
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SEMICONDUCTOR PACKAGING SYSTEM WITH MULTIPART CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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08/23/2011
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Application #:
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12822080
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Filing Dt:
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06/23/2010
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Publication #:
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Pub Dt:
|
10/14/2010
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE FOR ENCAPSULATED DIE HAVING PRE-APPLIED PROTECTIVE LAYER
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Patent #:
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Issue Dt:
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09/17/2013
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Application #:
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12822405
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Filing Dt:
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06/24/2010
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Publication #:
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Pub Dt:
|
12/29/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRENCHES AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
04/11/2017
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Application #:
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12822458
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Filing Dt:
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06/24/2010
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Publication #:
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Pub Dt:
|
12/29/2011
| | | | |
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Title:
|
Semiconductor Device and Method of Forming Anisotropic Conductive Film Between Semiconductor Die and Build-Up Interconnect Structure
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Patent #:
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Issue Dt:
|
08/05/2014
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Application #:
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12822488
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Filing Dt:
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06/24/2010
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Publication #:
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Pub Dt:
|
12/29/2011
| | | | |
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Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RDL ALONG SLOPED SIDE SURFACE OF SEMICONDUCTOR DIE FOR Z-DIRECTION INTERCONNECT
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Patent #:
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Issue Dt:
|
04/02/2013
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Application #:
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12822504
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Filing Dt:
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06/24/2010
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Publication #:
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Pub Dt:
|
12/29/2011
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECT STRUCTURE ON LEADFRAME
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Patent #:
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Issue Dt:
|
03/05/2013
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Application #:
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12822659
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Filing Dt:
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06/24/2010
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Publication #:
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Pub Dt:
|
12/29/2011
| | | | |
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Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STAND-OFF AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
04/03/2012
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Application #:
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12822954
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Filing Dt:
|
06/24/2010
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|
Publication #:
|
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Pub Dt:
|
10/21/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADED PACKAGE AND METHOD FOR MANUFACTURING THEREOF
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Patent #:
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Issue Dt:
|
01/21/2014
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Application #:
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12823079
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Filing Dt:
|
06/24/2010
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Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRAL INNER LEAD AND PADDLE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
11/13/2012
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Application #:
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12826365
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Filing Dt:
|
06/29/2010
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Publication #:
|
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Pub Dt:
|
10/21/2010
| | | | |
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Title:
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METHOD OF FORMING AN INDUCTOR ON A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
|
02/07/2012
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Application #:
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12826368
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Filing Dt:
|
06/29/2010
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Publication #:
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Pub Dt:
|
10/21/2010
| | | | |
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Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING HIGH-FREQUENCY CIRCUIT STRUCTURE AND METHOD THEREOF
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Patent #:
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Issue Dt:
|
05/15/2012
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Application #:
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12827864
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Filing Dt:
|
06/30/2010
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Publication #:
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Pub Dt:
|
10/21/2010
| | | | |
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Title:
|
QUAD FLAT PACK IN QUAD FLAT PACK INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
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Patent #:
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Issue Dt:
|
12/13/2011
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Application #:
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12830390
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Filing Dt:
|
07/05/2010
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|
Publication #:
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Pub Dt:
|
10/28/2010
| | | | |
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Title:
|
SEMICONDUCTOR DEVICE HAVING ELECTRICAL DEVICES MOUNTED TO IPD STRUCTURE AND METHOD OF SHIELDING ELECTROMAGNETIC INTERFERENCE
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Patent #:
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Issue Dt:
|
10/15/2013
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Application #:
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12831047
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Filing Dt:
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07/06/2010
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Publication #:
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Pub Dt:
|
10/28/2010
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING ELECTROSTATIC DISCHARGE PROTECTION FOR INTEGRATED PASSIVE DEVICES
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Patent #:
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Issue Dt:
|
03/27/2012
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Application #:
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12831822
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Filing Dt:
|
07/07/2010
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Publication #:
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Pub Dt:
|
10/28/2010
| | | | |
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Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKING AND ANTI-FLASH STRUCTURE
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Patent #:
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Issue Dt:
|
04/24/2012
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Application #:
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12832821
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Filing Dt:
|
07/08/2010
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|
Publication #:
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Pub Dt:
|
10/28/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLARS IN RECESSED REGION OF PERIPHERAL AREA AROUND THE DEVICE FOR ELECTRICAL INTERCONNECTION TO OTHER DEVICES
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Patent #:
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Issue Dt:
|
04/02/2013
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Application #:
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12834176
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Filing Dt:
|
07/12/2010
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Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HONEYCOMB MOLDING
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Patent #:
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Issue Dt:
|
02/04/2014
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Application #:
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12837562
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Filing Dt:
|
07/16/2010
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|
Publication #:
|
|
Pub Dt:
|
01/19/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Protective Layer Over Exposed Surfaces of Semiconductor Die
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|
Patent #:
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Issue Dt:
|
02/04/2014
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Application #:
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12837562
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Filing Dt:
|
07/16/2010
|
|
Publication #:
|
|
Pub Dt:
|
01/19/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Protective Layer Over Exposed Surfaces of Semiconductor Die
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|
Patent #:
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Issue Dt:
|
11/25/2014
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Application #:
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12852433
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Filing Dt:
|
08/06/2010
|
|
Publication #:
|
|
Pub Dt:
|
02/09/2012
| | | | |
|
Title:
|
Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV
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Patent #:
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Issue Dt:
|
11/27/2012
|
Application #:
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12853865
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Filing Dt:
|
08/10/2010
|
|
Publication #:
|
|
Pub Dt:
|
02/16/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT IN FO-WLCSP USING LEADFRAME DISPOSED BETWEEN SEMICONDUCTOR DIE
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|
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Patent #:
|
|
Issue Dt:
|
06/05/2012
|
Application #:
|
12853898
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Filing Dt:
|
08/10/2010
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|
Publication #:
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Pub Dt:
|
02/16/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING B-STAGE CONDUCTIVE POLYMER OVER CONTACT PADS OF SEMICONDUCTOR DIE IN FO-WLCSP
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Patent #:
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Issue Dt:
|
11/06/2012
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Application #:
|
12854306
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Filing Dt:
|
08/11/2010
|
|
Publication #:
|
|
Pub Dt:
|
02/16/2012
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED LEAD AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
08/06/2013
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Application #:
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12856288
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Filing Dt:
|
08/13/2010
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|
Publication #:
|
|
Pub Dt:
|
04/07/2011
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHAPED LEAD AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
01/01/2013
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Application #:
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12857362
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Filing Dt:
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08/16/2010
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Publication #:
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|
Pub Dt:
|
02/16/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING FO-WLCSP HAVING CONDUCTIVE LAYERS AND CONDUCTIVE VIAS SEPARATED BY POLYMER LAYERS
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Patent #:
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Issue Dt:
|
12/13/2011
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Application #:
|
12857395
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Filing Dt:
|
08/16/2010
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|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER-LEVEL MULTI-ROW ETCHED LEADFRAME WITH BASE LEADS AND EMBEDDED SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
|
07/23/2013
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Application #:
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12858163
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Filing Dt:
|
08/17/2010
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|
Publication #:
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|
Pub Dt:
|
02/23/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET CONDUCTIVE PILLARS OVER FIRST SUBSTRATE ALIGNED TO VERTICALLY OFFSET BOT INTERCONNECT SITES FORMED OVER SECOND SUBSTRATE
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Patent #:
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Issue Dt:
|
11/26/2013
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Application #:
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12858593
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Filing Dt:
|
08/18/2010
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Publication #:
|
|
Pub Dt:
|
12/09/2010
| | | | |
|
Title:
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Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die
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Patent #:
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Issue Dt:
|
03/19/2013
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Application #:
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12858602
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Filing Dt:
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08/18/2010
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Publication #:
|
|
Pub Dt:
|
12/09/2010
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH HOLE VIAS IN DIE EXTENSION REGION AROUND PERIPHERY OF DIE
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Patent #:
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Issue Dt:
|
08/28/2012
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Application #:
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12858615
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Filing Dt:
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08/18/2010
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Publication #:
|
|
Pub Dt:
|
12/09/2010
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH HOLE VIAS IN DIE EXTENSION REGION AROUND PERIPHERY OF DIE
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Patent #:
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|
Issue Dt:
|
08/14/2012
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Application #:
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12859049
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Filing Dt:
|
08/18/2010
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|
Publication #:
|
|
Pub Dt:
|
04/07/2011
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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|
Issue Dt:
|
10/16/2012
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Application #:
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12868334
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Filing Dt:
|
08/25/2010
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Publication #:
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|
Pub Dt:
|
03/01/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING FO-WLCSP WITH DISCRETE SEMICONDUCTOR COMPONENTS MOUNTED UNDER AND OVER SEMICONDUCTOR DIE
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
12870681
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Filing Dt:
|
08/27/2010
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|
Publication #:
|
|
Pub Dt:
|
03/01/2012
| | | | |
|
Title:
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Semiconductor Device and Method of Forming Leadframe as Vertical Interconnect Structure Between Stacked Semiconductor Die
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Patent #:
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|
Issue Dt:
|
01/17/2012
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Application #:
|
12870696
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Filing Dt:
|
08/27/2010
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|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED INTERCONNECT LAYER FOR STACKED SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
|
01/10/2012
|
Application #:
|
12871031
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Filing Dt:
|
08/30/2010
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|
Publication #:
|
|
Pub Dt:
|
12/23/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH SIDE-BY-SIDE AND OFFSET STACKING AND METHOD FOR MANUFACTURING THEREOF
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Patent #:
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Issue Dt:
|
05/07/2013
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Application #:
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12871401
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Filing Dt:
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08/30/2010
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Publication #:
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|
Pub Dt:
|
12/23/2010
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-Up Interconnect Structure
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|
Patent #:
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Issue Dt:
|
08/27/2013
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Application #:
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12874787
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Filing Dt:
|
09/02/2010
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Publication #:
|
|
Pub Dt:
|
03/08/2012
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING TSV SEMICONDUCTOR WAFER WITH EMBEDDED SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
|
05/07/2013
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Application #:
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12874827
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Filing Dt:
|
09/02/2010
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Publication #:
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|
Pub Dt:
|
03/08/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE LEADS FROM BASE SUBSTRATE AS STANDOFF FOR STACKING SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
|
07/16/2013
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Application #:
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12875496
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Filing Dt:
|
09/03/2010
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|
Publication #:
|
|
Pub Dt:
|
12/23/2010
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER AND METHOD FOR MANUFACTURING THEREOF
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Patent #:
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|
Issue Dt:
|
02/26/2013
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Application #:
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12875981
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Filing Dt:
|
09/03/2010
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|
Publication #:
|
|
Pub Dt:
|
03/08/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER FRAME OVER SEMICONDUCTOR DIE TO PROVIDE VERTICAL INTERCONNECT
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Patent #:
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Issue Dt:
|
04/02/2013
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Application #:
|
12875998
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Filing Dt:
|
09/03/2010
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|
Publication #:
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|
Pub Dt:
|
03/08/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PRE-MOLDED SUBSTRATE TO REDUCE WARPAGE DURING DIE MOUNTING
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Patent #:
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Issue Dt:
|
01/15/2013
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Application #:
|
12876013
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Filing Dt:
|
09/03/2010
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|
Publication #:
|
|
Pub Dt:
|
03/08/2012
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING DIFFERENT HEIGHT CONDUCTIVE PILLARS TO ELECTRICALLY INTERCONNECT STACKED LATERALLY OFFSET SEMICONDUCTOR DIE
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|
Patent #:
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|
Issue Dt:
|
12/20/2011
|
Application #:
|
12876425
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Filing Dt:
|
09/07/2010
|
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WLP WITH SEMICONDUCTOR DIE EMBEDDED WITHIN PENETRABLE ENCAPSULANT BETWEEN TSV INTERPOSERS
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Patent #:
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Issue Dt:
|
11/06/2012
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Application #:
|
12878661
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Filing Dt:
|
09/09/2010
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|
Publication #:
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|
Pub Dt:
|
03/15/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE SUBSTRATE WITH CAVITIES FORMED THROUGH ETCH-RESISTANT CONDUCTIVE LAYER FOR BUMP LOCKING
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Patent #:
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Issue Dt:
|
05/07/2013
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Application #:
|
12880255
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Filing Dt:
|
09/13/2010
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|
Publication #:
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|
Pub Dt:
|
03/15/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BOND-ON-LEAD INTERCONNECTION FOR MOUNTING SEMICONDUCTOR DIE IN FO-WLCSP
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Patent #:
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|
Issue Dt:
|
09/20/2011
|
Application #:
|
12880415
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Filing Dt:
|
09/13/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2010
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM USING HEAT SLUG
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|
Patent #:
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|
Issue Dt:
|
11/06/2012
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Application #:
|
12881983
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Filing Dt:
|
09/14/2010
|
|
Publication #:
|
|
Pub Dt:
|
03/15/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
12882067
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Filing Dt:
|
09/14/2010
|
|
Publication #:
|
|
Pub Dt:
|
03/15/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
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|
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|
Patent #:
|
|
Issue Dt:
|
06/05/2012
|
Application #:
|
12882083
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Filing Dt:
|
09/14/2010
|
|
Publication #:
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|
Pub Dt:
|
03/15/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MOLD UNDERFILL USING DISPENSING NEEDLE HAVING SAME WIDTH AS SEMICONDUCTOR DIE
|
|
