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Patent Assignment Details
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Reel/Frame:036288/0748   Pages: 247
Recorded: 08/06/2015
Attorney Dkt #:70341.00400
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1836
Page 12 of 19
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
1
Patent #:
8409922
Issue Dt:
04/02/2013
Application #:
12882110
Filing Dt:
09/14/2010
Publication #:
US20120061814
Pub Dt:
03/15/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING LEADFRAME INTERPOSER OVER SEMICONDUCTOR DIE AND TSV SUBSTRATE FOR VERTICAL ELECTRICAL INTERCONNECT
2
Patent #:
9281300
Issue Dt:
03/08/2016
Application #:
12882728
Filing Dt:
09/15/2010
Publication #:
US20110001240
Pub Dt:
01/06/2011
Title:
Chip Scale Module Package in BGA Semiconductor Package
3
Patent #:
NONE
Issue Dt:
Application #:
12882748
Filing Dt:
09/15/2010
Publication #:
US20110024890
Pub Dt:
02/03/2011
Title:
Stackable Package By Using Internal Stacking Modules
4
Patent #:
8227903
Issue Dt:
07/24/2012
Application #:
12882856
Filing Dt:
09/15/2010
Publication #:
US20120061859
Pub Dt:
03/15/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULANT CONTAINMENT AND METHOD OF MANUFACTURE THEREOF
5
Patent #:
8404524
Issue Dt:
03/26/2013
Application #:
12884073
Filing Dt:
09/16/2010
Publication #:
US20120068318
Pub Dt:
03/22/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADDLE MOLDING AND METHOD OF MANUFACTURE THEREOF
6
Patent #:
8936971
Issue Dt:
01/20/2015
Application #:
12884102
Filing Dt:
09/16/2010
Publication #:
US20120068363
Pub Dt:
03/22/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DIE PADDLES AND METHOD OF MANUFACTURE THEREOF
7
Patent #:
8466567
Issue Dt:
06/18/2013
Application #:
12884134
Filing Dt:
09/16/2010
Publication #:
US20120068319
Pub Dt:
03/22/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
8
Patent #:
8460968
Issue Dt:
06/11/2013
Application #:
12885137
Filing Dt:
09/17/2010
Publication #:
US20120068332
Pub Dt:
03/22/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POST AND METHOD OF MANUFACTURE THEREOF
9
Patent #:
8399305
Issue Dt:
03/19/2013
Application #:
12885831
Filing Dt:
09/20/2010
Publication #:
US20120068353
Pub Dt:
03/22/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DAM MATERIAL WITH OPENINGS AROUND SEMICONDUCTOR DIE FOR MOLD UNDERFILL USING DISPENSER AND VACUUM ASSIST
10
Patent #:
8421212
Issue Dt:
04/16/2013
Application #:
12887681
Filing Dt:
09/22/2010
Publication #:
US20120068328
Pub Dt:
03/22/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ACTIVE SURFACE HEAT REMOVAL AND METHOD OF MANUFACTURE THEREOF
11
Patent #:
8349735
Issue Dt:
01/08/2013
Application #:
12887811
Filing Dt:
09/22/2010
Publication #:
US20120068313
Pub Dt:
03/22/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE TSV WITH INSULATING ANNULAR RING
12
Patent #:
8916416
Issue Dt:
12/23/2014
Application #:
12889588
Filing Dt:
09/24/2010
Publication #:
US20130127039
Pub Dt:
05/23/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF LASER-MARKING LAMINATE LAYER FORMED OVER EWLB WITH TAPE APPLIED TO OPPOSITE SURFACE
13
Patent #:
8803300
Issue Dt:
08/12/2014
Application #:
12889911
Filing Dt:
09/24/2010
Publication #:
US20110079888
Pub Dt:
04/07/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PROTECTIVE COATING AND METHOD OF MANUFACTURE THEREOF
14
Patent #:
8766426
Issue Dt:
07/01/2014
Application #:
12890161
Filing Dt:
09/24/2010
Publication #:
US20120074560
Pub Dt:
03/29/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL AND METHOD OF MANUFACTURE THEREOF
15
Patent #:
8455991
Issue Dt:
06/04/2013
Application #:
12890338
Filing Dt:
09/24/2010
Publication #:
US20120074588
Pub Dt:
03/29/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL AND METHOD OF MANUFACTURE THEREOF
16
Patent #:
8861221
Issue Dt:
10/14/2014
Application #:
12890371
Filing Dt:
09/24/2010
Publication #:
US20120075821
Pub Dt:
03/29/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A SHIELD AND METHOD OF MANUFACTURE THEREOF
17
Patent #:
8519518
Issue Dt:
08/27/2013
Application #:
12890409
Filing Dt:
09/24/2010
Publication #:
US20120074547
Pub Dt:
03/29/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
18
Patent #:
8669649
Issue Dt:
03/11/2014
Application #:
12890491
Filing Dt:
09/24/2010
Publication #:
US20120074548
Pub Dt:
03/29/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERLOCK AND METHOD OF MANUFACTURE THEREOF
19
Patent #:
8642446
Issue Dt:
02/04/2014
Application #:
12891232
Filing Dt:
09/27/2010
Publication #:
US20120074534
Pub Dt:
03/29/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE STRUCTURE AROUND SEMICONDUCTOR DIE FOR LOCALIZED PLANARIZATION OF INSULATING LAYER
20
Patent #:
8021924
Issue Dt:
09/20/2011
Application #:
12892907
Filing Dt:
09/28/2010
Publication #:
US20110018084
Pub Dt:
01/27/2011
Title:
ENCAPSULANT CAVITY INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF FABRICATION THEREOF
21
Patent #:
8120187
Issue Dt:
02/21/2012
Application #:
12892941
Filing Dt:
09/29/2010
Publication #:
US20110012270
Pub Dt:
01/20/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING AND METHOD OF MANUFACTURE THEREOF
22
Patent #:
8247268
Issue Dt:
08/21/2012
Application #:
12896430
Filing Dt:
10/01/2010
Publication #:
US20110111591
Pub Dt:
05/12/2011
Title:
SEMICONDUCTOR WAFER HAVING THROUGH-HOLE VIAS ON SAW STREETS WITH BACKSIDE REDISTRIBUTION LAYER
23
Patent #:
8097943
Issue Dt:
01/17/2012
Application #:
12905797
Filing Dt:
10/15/2010
Publication #:
US20110024903
Pub Dt:
02/03/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER LEVEL GROUND PLANE AND POWER RING
24
Patent #:
8263439
Issue Dt:
09/11/2012
Application #:
12905825
Filing Dt:
10/15/2010
Publication #:
US20110024916
Pub Dt:
02/03/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INTERPOSER PACKAGE WITH THROUGH SILICON VIAS
25
Patent #:
8174098
Issue Dt:
05/08/2012
Application #:
12911042
Filing Dt:
10/25/2010
Publication #:
US20110037168
Pub Dt:
02/17/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING A THERMAL DISSIPATION PATH THROUGH RDL AND CONDUCTIVE VIA
26
Patent #:
8704366
Issue Dt:
04/22/2014
Application #:
12911592
Filing Dt:
10/25/2010
Publication #:
US20110037172
Pub Dt:
02/17/2011
Title:
Ultra Thin Bumped Wafer With Under-Film
27
Patent #:
8222717
Issue Dt:
07/17/2012
Application #:
12912467
Filing Dt:
10/26/2010
Title:
EMBEDDED SEMICONDUCTOR DIE PACKAGE AND METHOD OF MAKING THE SAME USING METAL FRAME CARRIER
28
Patent #:
8368188
Issue Dt:
02/05/2013
Application #:
12912728
Filing Dt:
10/26/2010
Publication #:
US20110037152
Pub Dt:
02/17/2011
Title:
DROP-MOLD CONFORMABLE MATERIAL AS AN ENCAPSULATION FOR AN INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
29
Patent #:
8378502
Issue Dt:
02/19/2013
Application #:
12912730
Filing Dt:
10/26/2010
Publication #:
US20110037136
Pub Dt:
02/17/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH IMAGE SENSOR SYSTEM
30
Patent #:
9337116
Issue Dt:
05/10/2016
Application #:
12914878
Filing Dt:
10/28/2010
Publication #:
US20120104623
Pub Dt:
05/03/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED INTERPOSER FOR STACKING AND ELECTRICALLY CONNECTING SEMICONDUCTOR DIE
31
Patent #:
8263435
Issue Dt:
09/11/2012
Application #:
12914895
Filing Dt:
10/28/2010
Publication #:
US20120104624
Pub Dt:
05/03/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF STACKING SEMICONDUCTOR DIE IN MOLD LASER PACKAGE INTERCONNECTED BY BUMPS AND CONDUCTIVE VIAS
32
Patent #:
8329554
Issue Dt:
12/11/2012
Application #:
12916758
Filing Dt:
11/01/2010
Publication #:
US20110045637
Pub Dt:
02/24/2011
Title:
ULTRA THIN BUMPED WAFER WITH UNDER-FILM
33
Patent #:
8546193
Issue Dt:
10/01/2013
Application #:
12917629
Filing Dt:
11/02/2010
Publication #:
US20120104590
Pub Dt:
05/03/2012
Title:
Semiconductor Device and Method of Forming Penetrable Film Encapsulant Around Semiconductor Die and Interconnect Structure
34
Patent #:
8866248
Issue Dt:
10/21/2014
Application #:
12941683
Filing Dt:
11/08/2010
Publication #:
US20110049662
Pub Dt:
03/03/2011
Title:
SEMICONDUCTOR DEVICE WITH OPTICAL SENSOR AND METHOD OF FORMING INTERCONNECT STRUCTURE ON FRONT AND BACKSIDE OF THE DEVICE
35
Patent #:
8258612
Issue Dt:
09/04/2012
Application #:
12942084
Filing Dt:
11/09/2010
Publication #:
US20110049687
Pub Dt:
03/03/2011
Title:
ENCAPSULANT INTERPOSER SYSTEM WITH INTEGRATED PASSIVE DEVICES AND MANUFACTURING METHOD THEREFOR
36
Patent #:
8802500
Issue Dt:
08/12/2014
Application #:
12944351
Filing Dt:
11/11/2010
Publication #:
US20110108969
Pub Dt:
05/12/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
37
Patent #:
NONE
Issue Dt:
Application #:
12946841
Filing Dt:
11/15/2010
Publication #:
US20120119345
Pub Dt:
05/17/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DEVICE MOUNT AND METHOD OF MANUFACTURE THEREOF
38
Patent #:
10388626
Issue Dt:
08/20/2019
Application #:
12947414
Filing Dt:
11/16/2010
Publication #:
US20120241945
Pub Dt:
09/27/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING FLIPCHIP INTERCONNECT STRUCTURE
39
Patent #:
8384227
Issue Dt:
02/26/2013
Application #:
12947442
Filing Dt:
11/16/2010
Publication #:
US20120119388
Pub Dt:
05/17/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER FRAME ELECTRICALLY CONNECTED TO EMBEDDED SEMICONDUCTOR DIE
40
Patent #:
8421203
Issue Dt:
04/16/2013
Application #:
12948756
Filing Dt:
11/17/2010
Publication #:
US20120119393
Pub Dt:
05/17/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FOLDABLE SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
41
Patent #:
8877567
Issue Dt:
11/04/2014
Application #:
12949396
Filing Dt:
11/18/2010
Publication #:
US20120126395
Pub Dt:
05/24/2012
Title:
Semiconductor Device and Method of Forming Uniform Height Insulating Layer Over Interposer Frame as Standoff for Semiconductor Die
42
Patent #:
8093100
Issue Dt:
01/10/2012
Application #:
12949835
Filing Dt:
11/19/2010
Publication #:
US20110062591
Pub Dt:
03/17/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING THROUGH SILICON VIA WITH DIRECT INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
43
Patent #:
8193604
Issue Dt:
06/05/2012
Application #:
12950591
Filing Dt:
11/19/2010
Publication #:
US20110068468
Pub Dt:
03/24/2011
Title:
SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CORE STRUCTURE AND METHOD OF FORMING THE SAME
44
Patent #:
8372695
Issue Dt:
02/12/2013
Application #:
12950631
Filing Dt:
11/19/2010
Publication #:
US20120126428
Pub Dt:
05/24/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
45
Patent #:
8288202
Issue Dt:
10/16/2012
Application #:
12951399
Filing Dt:
11/22/2010
Publication #:
US20120126416
Pub Dt:
05/24/2012
Title:
METHOD OF FORMING PARTIALLY-ETCHED CONDUCTIVE LAYER RECESSED WITHIN SUBSTRATE FOR BONDING TO SEMICONDUCTOR DIE
46
Patent #:
8476772
Issue Dt:
07/02/2013
Application #:
12953812
Filing Dt:
11/24/2010
Publication #:
US20120126429
Pub Dt:
05/24/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE SUBSTRATE WITH RECESSES FOR CAPTURING BUMPED SEMICONDUCTOR DIE
47
Patent #:
8502358
Issue Dt:
08/06/2013
Application #:
12957339
Filing Dt:
11/30/2010
Publication #:
US20120133033
Pub Dt:
05/31/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-ROW LEADS AND METHOD OF MANUFACTURE THEREOF
48
Patent #:
8508026
Issue Dt:
08/13/2013
Application #:
12957361
Filing Dt:
11/30/2010
Publication #:
US20120133036
Pub Dt:
05/31/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONNECTION SUPPORTS AND METHOD OF MANUFACTURE THEREOF
49
Patent #:
8853001
Issue Dt:
10/07/2014
Application #:
12959709
Filing Dt:
12/03/2010
Publication #:
US20120241984
Pub Dt:
09/27/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PAD LAYOUT FOR FLIPCHIP SEMICONDUCTOR DIE
50
Patent #:
8574959
Issue Dt:
11/05/2013
Application #:
12960178
Filing Dt:
12/03/2010
Publication #:
US20130277826
Pub Dt:
10/24/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BUMP-ON-LEAD INTERCONNECTION
51
Patent #:
8841779
Issue Dt:
09/23/2014
Application #:
12961027
Filing Dt:
12/06/2010
Publication #:
US20120241946
Pub Dt:
09/27/2012
Title:
Semiconductor Device and Method of Forming High Routing Density Bol Bonl and Bonp interconnect sites on substrate
52
Patent #:
9258904
Issue Dt:
02/09/2016
Application #:
12961107
Filing Dt:
12/06/2010
Publication #:
US20120208326
Pub Dt:
08/16/2012
Title:
Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings
53
Patent #:
8349721
Issue Dt:
01/08/2013
Application #:
12961202
Filing Dt:
12/06/2010
Publication #:
US20110074026
Pub Dt:
03/31/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER ON CONDUCTIVE TRACES FOR ELECTRICAL ISOLATION IN FINE PITCH BONDING
54
Patent #:
9171769
Issue Dt:
10/27/2015
Application #:
12961260
Filing Dt:
12/06/2010
Publication #:
US20120139120
Pub Dt:
06/07/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING OPENINGS THROUGH ENCAPSULANT TO REDUCE WARPAGE AND STRESS ON SEMICONDUCTOR PACKAGE
55
Patent #:
8723324
Issue Dt:
05/13/2014
Application #:
12961489
Filing Dt:
12/06/2010
Publication #:
US20120139104
Pub Dt:
06/07/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF
56
Patent #:
8193037
Issue Dt:
06/05/2012
Application #:
12961490
Filing Dt:
12/06/2010
Publication #:
US20120139121
Pub Dt:
06/07/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF
57
Patent #:
8415205
Issue Dt:
04/09/2013
Application #:
12961494
Filing Dt:
12/06/2010
Publication #:
US20110169151
Pub Dt:
07/14/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD INTERLOCKING MECHANISMS AND METHOD OF MANUFACTURE THEREOF
58
Patent #:
8659172
Issue Dt:
02/25/2014
Application #:
12963919
Filing Dt:
12/09/2010
Publication #:
US20120211882
Pub Dt:
08/23/2012
Title:
Semiconductor Device and Method of Confining Conductive Bump Material with Solder Mask Patch
59
Patent #:
8350384
Issue Dt:
01/08/2013
Application #:
12963934
Filing Dt:
12/09/2010
Publication #:
US20110121464
Pub Dt:
05/26/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING ELECTRICAL INTERCONNECT WITH STRESS RELIEF VOID
60
Patent #:
8994048
Issue Dt:
03/31/2015
Application #:
12964117
Filing Dt:
12/09/2010
Publication #:
US20120146177
Pub Dt:
06/14/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RECESSES IN SUBSTRATE FOR SAME SIZE OR DIFFERENT SIZED DIE WITH VERTICAL INTEGRATION
61
Patent #:
8546957
Issue Dt:
10/01/2013
Application #:
12964577
Filing Dt:
12/09/2010
Publication #:
US20120146246
Pub Dt:
06/14/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DIELECTRIC SUPPORT AND METHOD OF MANUFACTURE THEREOF
62
Patent #:
8502387
Issue Dt:
08/06/2013
Application #:
12964617
Filing Dt:
12/09/2010
Publication #:
US20120146235
Pub Dt:
06/14/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTION AND METHOD OF MANUFACTURE THEREOF
63
Patent #:
8067832
Issue Dt:
11/29/2011
Application #:
12964638
Filing Dt:
12/09/2010
Publication #:
US20110079899
Pub Dt:
04/07/2011
Title:
EMBEDDED INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF MANUFACTURE THEREOF
64
Patent #:
8368199
Issue Dt:
02/05/2013
Application #:
12964644
Filing Dt:
12/09/2010
Publication #:
US20110079891
Pub Dt:
04/07/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES AND METHOD FOR MANUFACTURING THEREOF
65
Patent #:
8445990
Issue Dt:
05/21/2013
Application #:
12964810
Filing Dt:
12/10/2010
Publication #:
US20120146181
Pub Dt:
06/14/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INDUCTOR WITHIN INTERCONNECT LAYER VERTICALLY SEPARATED FROM SEMICONDUCTOR DIE
66
Patent #:
9601434
Issue Dt:
03/21/2017
Application #:
12964823
Filing Dt:
12/10/2010
Publication #:
US20120146236
Pub Dt:
06/14/2012
Title:
Semiconductor Device and Method of Forming Openings Through Insulating Layer Over Encapsulant for Enhanced Adhesion of Interconnect Structure
67
Patent #:
9093392
Issue Dt:
07/28/2015
Application #:
12965018
Filing Dt:
12/10/2010
Publication #:
US20120146229
Pub Dt:
06/14/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTION AND METHOD OF MANUFACTURE THEREOF
68
Patent #:
8143108
Issue Dt:
03/27/2012
Application #:
12965584
Filing Dt:
12/10/2010
Publication #:
US20110074028
Pub Dt:
03/31/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF DISSIPATING HEAT FROM THIN PACKAGE-ON-PACKAGE MOUNTED TO SUBSTRATE
69
Patent #:
8709932
Issue Dt:
04/29/2014
Application #:
12966071
Filing Dt:
12/13/2010
Publication #:
US20120146230
Pub Dt:
06/14/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
70
Patent #:
8779565
Issue Dt:
07/15/2014
Application #:
12967223
Filing Dt:
12/14/2010
Publication #:
US20120146192
Pub Dt:
06/14/2012
Title:
INTEGRATED CIRCUIT MOUNTING SYSTEM WITH PADDLE INTERLOCK AND METHOD OF MANUFACTURE THEREOF
71
Patent #:
8299596
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Assignors
1
STATS CHIPPAC, INC.
Exec Dt:
08/06/2015
2
STATS CHIPPAC LTD.
Exec Dt:
08/06/2015
Assignee
1
CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
39TH FLOOR, CITIBANK TOWER, CITIBANK PLAZA, 3 GARDEN ROAD
ATTENTION: AGENCY AND TRUST
CENTRAL, HONG KONG
Correspondence name and address
LAWRENCE KASS
28 LIBERTY STREET
C/O LAWRENCE KASS
NEW YORK, NY 10005

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