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10/04/2016
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13172680
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06/29/2011
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10/20/2011
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Semiconductor Device and Method of Wafer Level Package Integration
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01/15/2013
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13174033
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06/30/2011
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10/20/2011
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Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant
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04/15/2014
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13175694
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07/01/2011
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10/27/2011
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FLIP CHIP INTERCONNECTION STRUCTURE
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03/06/2012
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13178331
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07/07/2011
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11/03/2011
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09/10/2013
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13178347
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07/07/2011
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10/27/2011
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONTOURED ENCAPSULATION AND METHOD FOR MANUFACTURING THEREOF
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08/06/2013
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13181290
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07/12/2011
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01/26/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING RDL WIDER THAN CONTACT PAD ALONG FIRST AXIS AND NARROWER THAN CONTACT PAD ALONG SECOND AXIS
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12/01/2015
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13181412
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07/12/2011
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01/26/2012
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Semiconductor Device and Method of Forming RDL over Contact Pad with High Alignment Tolerance or Reduced Interconnect Pitch
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02/24/2015
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13181838
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07/13/2011
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11/03/2011
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Semiconductor Package with Penetrable Encapsulant Joining Semiconductor Die and Method Thereof
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12/29/2015
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13184253
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07/15/2011
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03/29/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING TSV INTERPOSER WITH SEMICONDUCTOR DIE AND BUILD-UP INTERCONNECT STRUCTURE ON OPPOSING SURFACES OF THE INTERPOSER
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08/06/2013
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13185384
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07/18/2011
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03/01/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADHESIVE MATERIAL OVER SEMICONDUCTOR DIE AND CARRIER TO REDUCE DIE SHIFTING DURING ENCAPSULATION
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04/22/2014
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13187252
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07/20/2011
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11/10/2011
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Title:
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08/12/2014
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07/21/2011
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01/26/2012
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Title:
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06/02/2015
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13190339
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07/25/2011
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11/17/2011
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING SEMICONDUCTOR DIE TO HEAT SPREADER ON TEMPORARY CARRIER AND FORMING POLYMER LAYER AND CONDUCTIVE LAYER OVER THE DIE
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06/02/2015
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13190339
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07/25/2011
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11/17/2011
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING SEMICONDUCTOR DIE TO HEAT SPREADER ON TEMPORARY CARRIER AND FORMING POLYMER LAYER AND CONDUCTIVE LAYER OVER THE DIE
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07/14/2015
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13191318
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07/26/2011
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11/17/2011
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING A VERTICAL INTERCONNECT STRUCTURE FOR 3-D FO-WLCSP
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02/11/2014
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13191386
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07/26/2011
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11/17/2011
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SEMICONDUCTOR PACKAGE AND METHOD OF MOUNTING SEMICONDUCTOR DIE TO OPPOSITE SIDES OF TSV SUBSTRATE
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08/27/2013
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07/29/2011
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11/24/2011
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SEMICONDUCTOR SYSTEM WITH FINE PITCH LEAD FINGERS AND METHOD OF MANUFACTURING THEREOF
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04/29/2014
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13195465
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08/01/2011
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11/24/2011
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LEADLESS INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
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04/26/2016
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13195636
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08/01/2011
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02/07/2013
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Semiconductor Device and Method of Forming POP With Stacked Semiconductor Die and Bumps Formed Directly on the Lower Die
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11/04/2014
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13195973
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08/02/2011
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11/24/2011
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01/21/2014
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08/02/2011
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11/24/2011
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LAMINATE BASE
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03/11/2014
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08/03/2011
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02/09/2012
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DIE PADDLE AND METHOD OF MANUFACTURE THEREOF
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03/05/2013
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13197122
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08/03/2011
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11/24/2011
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISOLATED PADS AND METHOD OF MANUFACTURE THEREOF
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06/24/2014
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13197215
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08/03/2011
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11/24/2011
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE
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11/17/2015
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08/11/2011
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02/14/2013
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Semiconductor Device and Method of Forming a Stackable Semiconductor Package with Vertically-Oriented Discrete Electrical Devices as Interconnect Structures
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01/08/2013
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13209620
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08/15/2011
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12/08/2011
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER AFTER ENCAPSULATION AND GROUNDED THROUGH INTERCONNECT STRUCTURE
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NONE
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13209837
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08/15/2011
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12/08/2011
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INCREASED CONNECTIVITY AND METHOD OF MANUFACTURE THEREOF
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04/19/2016
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13211303
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08/16/2011
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12/08/2011
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MAGNETIC FILM AND METHOD OF MANUFACTURE THEREOF
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02/05/2013
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08/17/2011
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12/08/2011
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SHIELDED STACKED INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
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07/24/2012
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13212986
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08/18/2011
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12/08/2011
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APPARATUS FOR THERMALLY ENHANCED SEMICONDUCTOR PACKAGE
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04/09/2013
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13215131
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08/22/2011
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12/08/2011
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NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE GROUND SITES
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NONE
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13218388
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08/25/2011
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02/28/2013
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Semiconductor Device and Method of Forming TIM Within Recesses of MUF Material
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03/18/2014
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13218653
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08/26/2011
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12/22/2011
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SEMICONDUCTOR DEVICE AND METHOD OF SELF-CONFINEMENT OF CONDUCTIVE BUMP MATERIAL DURING REFLOW WITHOUT SOLDER MASK
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03/05/2013
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13219374
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08/26/2011
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12/22/2011
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SEMICONDUCTOR DEVICE AND METHOD OF INTEGRATING BALUN AND RF COUPLER ON A COMMON SUBSTRATE
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02/05/2013
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13223478
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09/01/2011
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12/22/2011
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Semiconductor Device and Method of Forming Dam Material Around Periphery of Die to Reduce Warpage
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10/22/2013
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13224718
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09/02/2011
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03/07/2013
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED THERMAL HEAT SHIELD AND METHOD OF MANUFACTURE THEREOF
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07/23/2013
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09/02/2011
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03/07/2013
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STIFFENER AND METHOD OF MANUFACTURE THEREOF
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08/20/2019
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09/06/2011
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03/07/2013
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Semiconductor device and method of forming FO-WLCSP with recessed interconnect area in peripheral region of semiconductor die
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12/25/2018
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09/07/2011
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03/07/2013
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Semiconductor Device and Method of Forming a Low Profile Dual-Purpose Shield and Heat-Dissipation Structure
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08/06/2013
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09/08/2011
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01/26/2012
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SEMICONDUCTOR DEVICE AND METHOD OF CONFORMING CONDUCTIVE VIAS BETWEEN INSULATING LAYERS IN SAW STREETS
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08/06/2013
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09/08/2011
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01/26/2012
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SEMICONDUCTOR DEVICE WITH CONDUCTIVE VIAS BETWEEN SAW STREETS
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12/16/2014
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09/13/2011
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01/05/2012
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Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP
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12/16/2014
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13231789
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09/13/2011
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01/05/2012
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Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP
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03/31/2015
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13231839
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09/13/2011
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03/29/2012
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Semiconductor Device and Method of Bonding Different Size Semiconductor Die at the Wafer Level
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03/05/2013
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13233402
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09/15/2011
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01/05/2012
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METHOD FOR MANUFACTURE OF INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PROTECTED CONDUCTIVE LAYERS FOR PADS
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01/05/2016
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09/16/2011
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03/21/2013
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Semiconductor Device and Method of Forming Conductive Protrusions Over Conductive Pillars or Bond Pads as Fixed Offset Vertical Interconnect Structure
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11/03/2015
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09/16/2011
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03/21/2013
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08/26/2014
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09/16/2011
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03/21/2013
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08/20/2013
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09/16/2011
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03/21/2013
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE UNDERLAYER AND METHOD OF MANUFACTURE THEREOF
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12/10/2013
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09/16/2011
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03/21/2013
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE MOLD AND METHOD OF MANUFACTURE THEREOF
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12/30/2014
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13235413
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09/18/2011
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01/05/2012
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Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads
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12/30/2014
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13235413
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Filing Dt:
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09/18/2011
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Publication #:
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Pub Dt:
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01/05/2012
| | | | |
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Title:
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Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads
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Patent #:
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Issue Dt:
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11/13/2012
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Application #:
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13235755
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Filing Dt:
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09/19/2011
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Publication #:
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Pub Dt:
|
01/12/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A COMPONENT IN AN ENCAPSULANT CAVITY AND METHOD OF FABRICATION THEREOF
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Patent #:
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Issue Dt:
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03/01/2016
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Application #:
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13236952
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Filing Dt:
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09/20/2011
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Publication #:
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Pub Dt:
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03/21/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR PACKAGE USING PANEL FORM CARRIER
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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13237828
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Filing Dt:
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09/20/2011
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Publication #:
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Pub Dt:
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01/12/2012
| | | | |
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Title:
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SOLDER BUMP WITH INNER CORE PILLAR IN SEMICONDUCTOR PACKAGE
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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13237828
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Filing Dt:
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09/20/2011
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Publication #:
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Pub Dt:
|
01/12/2012
| | | | |
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Title:
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SOLDER BUMP WITH INNER CORE PILLAR IN SEMICONDUCTOR PACKAGE
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Patent #:
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Issue Dt:
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04/15/2014
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Application #:
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13237918
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Filing Dt:
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09/20/2011
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Publication #:
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Pub Dt:
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03/21/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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11/01/2016
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Application #:
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13239080
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Filing Dt:
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09/21/2011
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Publication #:
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Pub Dt:
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03/21/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTION AND SUPPORT STRUCTURE FOR CONDUCTIVE INTERCONNECT STRUCTURE
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Patent #:
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Issue Dt:
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12/24/2013
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Application #:
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13239373
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Filing Dt:
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09/21/2011
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Publication #:
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Pub Dt:
|
03/21/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT SYSTEM WITH TEST PADS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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07/09/2013
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Application #:
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13241141
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Filing Dt:
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09/22/2011
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Publication #:
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Pub Dt:
|
03/28/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL CONNECTION AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
09/11/2012
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Application #:
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13241153
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Filing Dt:
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09/22/2011
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Publication #:
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Pub Dt:
|
01/26/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF DUAL-MOLDING DIE FORMED ON OPPOSITE SIDES OF BUILD-UP INTERCONNECT STRUCTURE
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Patent #:
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Issue Dt:
|
01/12/2016
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Application #:
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13242306
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Filing Dt:
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09/23/2011
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Publication #:
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Pub Dt:
|
03/28/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A SUBSTRATE EMBEDDED DUMMY-DIE PADDLE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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08/26/2014
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Application #:
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13242656
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Filing Dt:
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09/23/2011
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Publication #:
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Pub Dt:
|
08/22/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED UNDER-FILL AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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08/26/2014
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Application #:
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13242656
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Filing Dt:
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09/23/2011
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Publication #:
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Pub Dt:
|
08/22/2013
| | | | |
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Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED UNDER-FILL AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
06/13/2017
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Application #:
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13243214
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Filing Dt:
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09/23/2011
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Publication #:
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Pub Dt:
|
03/28/2013
| | | | |
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Title:
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Semiconductor Device and Method of Forming Interconnect Substrate for FO-WLCSP
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Patent #:
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Issue Dt:
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12/27/2016
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Application #:
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13243474
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Filing Dt:
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09/23/2011
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Publication #:
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Pub Dt:
|
03/28/2013
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CHIP STACKING AND METHOD OF MANUFACTURE THEREOF
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Patent #:
|
NONE
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Issue Dt:
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|
Application #:
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13243555
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Filing Dt:
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09/23/2011
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Publication #:
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Pub Dt:
|
03/28/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
07/05/2016
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Application #:
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13243558
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Filing Dt:
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09/23/2011
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Publication #:
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Pub Dt:
|
03/28/2013
| | | | |
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Title:
|
Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP
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Patent #:
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Issue Dt:
|
04/15/2014
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Application #:
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13243699
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Filing Dt:
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09/23/2011
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Publication #:
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Pub Dt:
|
03/28/2013
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK DEVICE
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Patent #:
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Issue Dt:
|
05/06/2014
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Application #:
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13243886
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Filing Dt:
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09/23/2011
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Publication #:
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|
Pub Dt:
|
03/28/2013
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
04/22/2014
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Application #:
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13244262
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Filing Dt:
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09/23/2011
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Publication #:
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Pub Dt:
|
03/28/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXTERNAL WIRE CONNECTION AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
02/24/2015
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Application #:
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13244273
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Filing Dt:
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09/23/2011
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Publication #:
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Pub Dt:
|
03/28/2013
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SHIELD AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
02/25/2014
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Application #:
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13245099
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Filing Dt:
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09/26/2011
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Publication #:
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Pub Dt:
|
01/19/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT STRUCTURE WITH TSV USING ENCAPSULANT FOR STRUCTURAL SUPPORT
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Patent #:
|
NONE
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Issue Dt:
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|
Application #:
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13245181
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Filing Dt:
|
09/26/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
|
Title:
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SEMICONDUCTOR PACKAGING STRUCTURE AND METHOD OF FORMING METALLURGICAL INTERCONNECTION DIRECTLY BETWEEN A DUP AND METALLIZATION ON A SUBTRATE
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Patent #:
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Issue Dt:
|
05/19/2015
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Application #:
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13247890
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Filing Dt:
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09/28/2011
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Publication #:
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Pub Dt:
|
01/26/2012
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE AND METHOD OF MANUFACTURING THEREOF
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Patent #:
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Issue Dt:
|
04/14/2015
|
Application #:
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13248312
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Filing Dt:
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09/29/2011
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Publication #:
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|
Pub Dt:
|
09/06/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure
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Patent #:
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Issue Dt:
|
04/12/2016
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Application #:
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13268048
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Filing Dt:
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10/07/2011
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Publication #:
|
|
Pub Dt:
|
05/09/2013
| | | | |
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Title:
|
Semiconductor Device and Method of Forming a Metallurgical Interconnection Between a Chip and a Substrate in a Flip Chip Package
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Patent #:
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Issue Dt:
|
10/22/2013
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Application #:
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13268091
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Filing Dt:
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10/07/2011
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Publication #:
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Pub Dt:
|
02/02/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON DIFFERENT HEIGHT TRACES
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Patent #:
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Issue Dt:
|
03/27/2012
|
Application #:
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13269258
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Filing Dt:
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10/07/2011
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Publication #:
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Pub Dt:
|
02/02/2012
| | | | |
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Title:
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METHOD FOR MANUFACTURING BALL GRID ARRAY PACKAGE STACKING SYSTEM
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Patent #:
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Issue Dt:
|
06/25/2013
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Application #:
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13269442
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Filing Dt:
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10/07/2011
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Publication #:
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Pub Dt:
|
02/02/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
06/11/2013
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Application #:
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13272034
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Filing Dt:
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10/12/2011
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Publication #:
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Pub Dt:
|
02/02/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUNDED INTERCONNECT
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Patent #:
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Issue Dt:
|
01/27/2015
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Application #:
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13273537
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Filing Dt:
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10/14/2011
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Publication #:
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Pub Dt:
|
02/09/2012
| | | | |
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Title:
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Through Hole Vias at Saw Streets Including Protrusions or Recesses for Interconnection
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Patent #:
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Issue Dt:
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06/09/2015
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Application #:
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13284003
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Filing Dt:
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10/28/2011
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Publication #:
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Pub Dt:
|
03/08/2012
| | | | |
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Title:
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Semiconductor Device and Method of Forming WLP With Semiconductor Die Embedded Within Penetrable Encapsulant Between TSV Interposers
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Patent #:
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Issue Dt:
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06/09/2015
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Application #:
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13284003
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Filing Dt:
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10/28/2011
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Publication #:
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Pub Dt:
|
03/08/2012
| | | | |
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Title:
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Semiconductor Device and Method of Forming WLP With Semiconductor Die Embedded Within Penetrable Encapsulant Between TSV Interposers
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Patent #:
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Issue Dt:
|
12/16/2014
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Application #:
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13284654
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Filing Dt:
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10/28/2011
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Publication #:
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Pub Dt:
|
05/03/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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03/31/2015
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Application #:
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13284811
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Filing Dt:
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10/28/2011
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Publication #:
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Pub Dt:
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02/16/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER-LEVEL MULTI-ROW ETCHED LEADFRAME WITH BASE LEADS AND EMBEDDED SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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06/09/2015
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Application #:
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13287006
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Filing Dt:
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11/01/2011
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Publication #:
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Pub Dt:
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05/02/2013
| | | | |
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Title:
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SEMICONDUCTOR DIE AND METHOD OF FORMING SLOPED SURFACE IN PHOTORESIST LAYER TO ENHANCE FLOW OF UNDERFILL MATERIAL BETWEEN SEMICONDUCTOR DIE AND SUBSTRATE
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Patent #:
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Issue Dt:
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03/08/2016
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Application #:
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13287035
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Filing Dt:
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11/01/2011
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Publication #:
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Pub Dt:
|
05/02/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THERMAL INTERFACE MATERIAL AND HEAT SPREADER OVER SEMICONDUCTOR DIE
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13289811
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Filing Dt:
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11/04/2011
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Publication #:
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Pub Dt:
|
05/09/2013
| | | | |
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Title:
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Semiconductor Device and Method of Forming Sloped Surface in Patterning Layer to Separate Bumps of Semiconductor Die from Patterning Layer
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Patent #:
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Issue Dt:
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08/20/2013
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Application #:
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13295843
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Filing Dt:
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11/14/2011
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Publication #:
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Pub Dt:
|
04/11/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING RECONSTITUTED WAFER WITH LARGER CARRIER TO ACHIEVE MORE EWLB PACKAGES PER WAFER WITH ENCAPSULANT DEPOSITED UNDER TEMPERATURE AND PRESSURE
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Patent #:
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|
Issue Dt:
|
12/01/2015
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Application #:
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13298267
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Filing Dt:
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11/16/2011
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|
Publication #:
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|
Pub Dt:
|
05/17/2012
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONNECTION STRUCTURE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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|
Issue Dt:
|
12/25/2012
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Application #:
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13300088
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Filing Dt:
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11/18/2011
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|
Publication #:
|
|
Pub Dt:
|
03/15/2012
| | | | |
|
Title:
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METHOD OF MANUFACTURE OF INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT
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Patent #:
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|
Issue Dt:
|
02/10/2015
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Application #:
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13303019
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Filing Dt:
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11/22/2011
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Publication #:
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|
Pub Dt:
|
05/23/2013
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE WITH CONDUCTIVE LAYER OVER SUBSTRATE WITH VENTS TO CHANNEL BUMP MATERIAL AND REDUCE INTERCONNECT VOIDS
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Patent #:
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Issue Dt:
|
02/10/2015
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Application #:
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13303019
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Filing Dt:
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11/22/2011
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Publication #:
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Pub Dt:
|
05/23/2013
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE WITH CONDUCTIVE LAYER OVER SUBSTRATE WITH VENTS TO CHANNEL BUMP MATERIAL AND REDUCE INTERCONNECT VOIDS
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Patent #:
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Issue Dt:
|
06/24/2014
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Application #:
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13306768
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Filing Dt:
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11/29/2011
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Publication #:
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Pub Dt:
|
10/24/2013
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPOSITE BUMP-ON-LEAD INTERCONNECTION
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Patent #:
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Issue Dt:
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09/22/2015
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Application #:
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13307849
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Filing Dt:
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11/30/2011
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Publication #:
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Pub Dt:
|
05/30/2013
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING RDL UNDER BUMP FOR ELECTRICAL CONNECTION TO ENCLOSED BUMP
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Patent #:
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Issue Dt:
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01/07/2014
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Application #:
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13311266
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Filing Dt:
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12/05/2011
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Publication #:
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Pub Dt:
|
06/28/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTEGRATED PASSIVE DEVICE OVER SEMICONDUCTOR DIE WITH CONDUCTIVE BRIDGE AND FAN-OUT REDISTRIBUTION LAYER
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Patent #:
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Issue Dt:
|
02/24/2015
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Application #:
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13312730
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Filing Dt:
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12/06/2011
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Publication #:
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Pub Dt:
|
06/06/2013
| | | | |
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Title:
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Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration
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Patent #:
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Issue Dt:
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02/24/2015
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Application #:
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13312730
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Filing Dt:
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12/06/2011
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|
Publication #:
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|
Pub Dt:
|
06/06/2013
| | | | |
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Title:
|
Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration
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Patent #:
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Issue Dt:
|
11/18/2014
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Application #:
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13312852
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Filing Dt:
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12/06/2011
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|
Publication #:
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|
Pub Dt:
|
03/29/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Non-Linear Portions of Conductive Layers
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