|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
13431816
|
Filing Dt:
|
03/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
|
Title:
|
METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
13438155
|
Filing Dt:
|
04/03/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
|
Title:
|
THERMALLY ENHANCED SEMICONDUCTOR PACKAGE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13438402
|
Filing Dt:
|
04/03/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Column Interconnect Structure to Reduce Wafer Stress
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13438463
|
Filing Dt:
|
04/03/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Shielding Layer Around Back Surface and Sides of Semiconductor Wafer Containing IPD Structure
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2018
|
Application #:
|
13438696
|
Filing Dt:
|
04/03/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming a Fan-Out Structure with Integrated Passive Device and Discrete Component
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2016
|
Application #:
|
13438713
|
Filing Dt:
|
04/03/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING B-STAGE CONDUCTIVE POLYMER OVER CONTACT PADS OF SEMICONDUCTOR DIE IN FO-WLCSP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2014
|
Application #:
|
13441550
|
Filing Dt:
|
04/06/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
|
Title:
|
ELECTRONIC SYSTEM WITH EXPANSION FEATURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13441691
|
Filing Dt:
|
04/06/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING STUD BUMPS OVER EMBEDDED DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13443067
|
Filing Dt:
|
04/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
|
Title:
|
DUAL MOLDED MULTI-CHIP PACKAGE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
13446664
|
Filing Dt:
|
04/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13446741
|
Filing Dt:
|
04/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
|
Title:
|
EMBEDDED SEMICONDUCTOR DIE PACKAGE AND METHOD OF MAKING THE SAME USING METAL FRAME CARRIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2016
|
Application #:
|
13446863
|
Filing Dt:
|
04/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
|
Title:
|
Semiconductor Device Having a Vertical Interconnect Structure Using Stud Bumps
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2015
|
Application #:
|
13456145
|
Filing Dt:
|
04/25/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH POST-PASSIVATION INTERCONNECTION AND INTEGRATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13458289
|
Filing Dt:
|
04/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MOLD UNDERFILL USING DISPENSING NEEDLE HAVING SAME WIDTH AS SEMICONDUCTOR DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2015
|
Application #:
|
13463148
|
Filing Dt:
|
05/03/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE WITH MOLDED CAVITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13464979
|
Filing Dt:
|
05/05/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
|
Title:
|
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2016
|
Application #:
|
13466945
|
Filing Dt:
|
05/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/14/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Depositing Underfill Material With Uniform Flow Rate
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2017
|
Application #:
|
13468981
|
Filing Dt:
|
05/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLAR HAVING AN EXPANDED BASE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2017
|
Application #:
|
13469754
|
Filing Dt:
|
05/11/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF SINGULATING THIN SEMICONDUCTOR WAFER ON CARRIER ALONG MODIFIED REGION WITHIN NON-ACTIVE REGION FORMED BY IRRADIATING ENERGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2016
|
Application #:
|
13471314
|
Filing Dt:
|
05/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/14/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Controlling Warpage in Semiconductor Package
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2017
|
Application #:
|
13476410
|
Filing Dt:
|
05/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/06/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Semiconductor Die and Substrate
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13476899
|
Filing Dt:
|
05/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/13/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13477630
|
Filing Dt:
|
05/22/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/13/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKABLE DEVICES AND A METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13477982
|
Filing Dt:
|
05/22/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
Semiconductor Method and Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2015
|
Application #:
|
13478008
|
Filing Dt:
|
05/22/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTION AND SUPPORT STRUCTURE FOR CONDUCTIVE INTERCONNECT STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2016
|
Application #:
|
13488029
|
Filing Dt:
|
06/04/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/05/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF BACKGRINDING AND SINGULATION OF SEMICONDUCTOR WAFER WHILE REDUCING KERF SHIFTING AND PROTECTING WAFER SURFACES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2016
|
Application #:
|
13488812
|
Filing Dt:
|
06/05/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/05/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2016
|
Application #:
|
13489143
|
Filing Dt:
|
06/05/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/05/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Reflow Soldering for Conductive Column Structure in Flip Chip Package
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2014
|
Application #:
|
13490908
|
Filing Dt:
|
06/07/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/12/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE PREVENTING MECHANISM AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13492646
|
Filing Dt:
|
06/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
APPARATUS FOR THERMALLY ENHANCED SEMICONDUCTOR PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13492668
|
Filing Dt:
|
06/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING THERMALLY CONDUCTIVE LAYER IN INTERCONNECT STRUCTURE FOR HEAT DISSIPATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2015
|
Application #:
|
13492687
|
Filing Dt:
|
06/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THERMALLY CONDUCTIVE LAYER BETWEEN SEMICONDUCTOR DIE AND BUILD-UP INTERCONNECT STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
13492765
|
Filing Dt:
|
06/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
LEADFRAME-BASED MOLD ARRAY PACKAGE HEAT SPREADER AND FABRICATION METHOD THEREFOR
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13494721
|
Filing Dt:
|
06/12/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/12/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ASSIST AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
13495663
|
Filing Dt:
|
06/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13517897
|
Filing Dt:
|
06/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13523261
|
Filing Dt:
|
06/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TIEBAR-LESS DESIGN AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
13526802
|
Filing Dt:
|
06/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLANARITY CONTROL AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13526877
|
Filing Dt:
|
06/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING WARPAGE PREVENTION STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13528051
|
Filing Dt:
|
06/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL STRUCTURES AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2017
|
Application #:
|
13529794
|
Filing Dt:
|
06/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
|
Title:
|
Solder Joint Flip Chip Interconnection Having Relief Structure
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2016
|
Application #:
|
13529918
|
Filing Dt:
|
06/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming an Embedded SOP Fan-Out Package
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13531941
|
Filing Dt:
|
06/25/2012
|
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHIELDING SPACER AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13536120
|
Filing Dt:
|
06/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/18/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
13536177
|
Filing Dt:
|
06/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/18/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING BUMPS FORMED ON SEMICONDUCTOR DIE INTO PENETRABLE ADHESIVE LAYER TO REDUCE DIE SHIFTING DURING ENCAPSULATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2014
|
Application #:
|
13536268
|
Filing Dt:
|
06/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/18/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WAFERSCALE SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13536321
|
Filing Dt:
|
06/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/18/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REMOVABLE BACKING ELEMENT HAVING PLATED TERMINAL LEADS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13536382
|
Filing Dt:
|
06/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING MOLD FLASH PREVENTION TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13542120
|
Filing Dt:
|
07/05/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/09/2014
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH GRID-ARRAY MECHANISM AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2016
|
Application #:
|
13543088
|
Filing Dt:
|
07/06/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming IPD in Fan-Out Wafer Level Chip Scale Package
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2015
|
Application #:
|
13543618
|
Filing Dt:
|
07/06/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
|
Title:
|
Semiconductor Wafer Having Through-Hole Vias on Saw Streets with Backside Redistribution Layer
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13543637
|
Filing Dt:
|
07/06/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Wafer Level Multi-Row Etched Lead Package
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2017
|
Application #:
|
13545887
|
Filing Dt:
|
07/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Semiconductor Die with Active Region Responsive to External Stimulus
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
13546726
|
Filing Dt:
|
07/11/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER LEVEL DIE INTEGRATION
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13553711
|
Filing Dt:
|
07/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
|
Title:
|
Semiconductor Die and Method of Forming through Organic Vias having Varying Width in Peripheral Region of the Die
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13553739
|
Filing Dt:
|
07/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE THROUGH ORGANIC VIAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2016
|
Application #:
|
13555353
|
Filing Dt:
|
07/23/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH OPTICAL SENSOR AND METHOD OF FORMING INTERCONNECT STRUCTURE ON FRONT AND BACKSIDE OF THE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13555531
|
Filing Dt:
|
07/23/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die having Pre-Applied Protective Layer
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13556064
|
Filing Dt:
|
07/23/2012
|
|
Title:
|
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
13556106
|
Filing Dt:
|
07/23/2012
|
|
Title:
|
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
13558586
|
Filing Dt:
|
07/26/2012
|
|
Title:
|
Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13558953
|
Filing Dt:
|
07/26/2012
|
|
Title:
|
SOLDER JOINT FLIP CHIP INTERCONNECTION HAVING RELIEF STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13559430
|
Filing Dt:
|
07/26/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
13560008
|
Filing Dt:
|
07/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor Die
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2015
|
Application #:
|
13563598
|
Filing Dt:
|
07/31/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERNAL STACKING MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13566287
|
Filing Dt:
|
08/03/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING DIE WITH TSV IN CAVITY OF SUBSTRATE FOR ELECTRICAL INTERCONNECT OF FI-POP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13566287
|
Filing Dt:
|
08/03/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING DIE WITH TSV IN CAVITY OF SUBSTRATE FOR ELECTRICAL INTERCONNECT OF FI-POP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
13566872
|
Filing Dt:
|
08/03/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF STACKING SEMICONDUCTOR DIE IN MOLD LASER PACKAGE INTERCONNECTED BY BUMPS AND CONDUCTIVE VIAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
13569088
|
Filing Dt:
|
08/07/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Holes in Substrate to Interconnect Top Shield and Ground Shield
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2016
|
Application #:
|
13569105
|
Filing Dt:
|
08/07/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming an IPD over a High-Resistivity Encapsulant Separated from other IPDS and Baseband Circuit
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13570979
|
Filing Dt:
|
08/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming WLCSP Structure using Protruded MLP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13570979
|
Filing Dt:
|
08/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming WLCSP Structure using Protruded MLP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13571020
|
Filing Dt:
|
08/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER OVER SEMICONDUCTOR DIE MOUNTED TO TSV INTERPOSER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2015
|
Application #:
|
13571068
|
Filing Dt:
|
08/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming RF Balun having Reduced Capacitive Coupling and High CMRR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2015
|
Application #:
|
13572517
|
Filing Dt:
|
08/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
Semicinductor Device with Cross-Talk Isolation Using M-CAP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2015
|
Application #:
|
13572517
|
Filing Dt:
|
08/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
Semicinductor Device with Cross-Talk Isolation Using M-CAP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13586178
|
Filing Dt:
|
08/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ARRAY CONTACTS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2017
|
Application #:
|
13596446
|
Filing Dt:
|
08/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
FLIP CHIP INTERCONNECT SOLDER MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2017
|
Application #:
|
13596860
|
Filing Dt:
|
08/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
Flip Chip Interconnect Solder Mask
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13597086
|
Filing Dt:
|
08/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND UNDERFILL AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
13604539
|
Filing Dt:
|
09/05/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming a Conductive Via-in-Via Structure
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13606451
|
Filing Dt:
|
09/07/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/25/2014
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PIP WITH INNER KNOWN GOOD DIE INTERCONNECTED WITH CONDUCTIVE BUMPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
13606631
|
Filing Dt:
|
09/07/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PARTIALLY-ETCHED CONDUCTIVE LAYER RECESSED WITHIN SUBSTRATE FOR BONDING TO SEMICONDUCTOR DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2016
|
Application #:
|
13607204
|
Filing Dt:
|
09/07/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming FO-WLCSP with Discrete Semiconductor Components Mounted Under and Over Semiconductor Die
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13609003
|
Filing Dt:
|
09/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13609050
|
Filing Dt:
|
09/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
|
Title:
|
Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor Die
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13615308
|
Filing Dt:
|
09/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/17/2013
| | | | |
|
Title:
|
Semiconductor Device and Method for Forming Passive Circuit Elements With Through Silicon Vias to Backside Interconnect Structures
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2016
|
Application #:
|
13621804
|
Filing Dt:
|
09/17/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/17/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH SOLDER BUMP FORMED ON HIGH TOPOGRAPHY PLATED CU PADS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2015
|
Application #:
|
13621810
|
Filing Dt:
|
09/17/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/17/2013
| | | | |
|
Title:
|
SOLDER BUMP WITH INNER CORE PILLAR IN SEMICONDUCTOR PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
13622280
|
Filing Dt:
|
09/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/17/2013
| | | | |
|
Title:
|
Method of Forming an Inductor on a Semiconductor Wafer
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
13622297
|
Filing Dt:
|
09/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/17/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE SUBSTRATE WITH CAVITIES FORMED THROUGH ETCH-RESISTANT CONDUCTIVE LAYER FOR BUMP LOCKING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2016
|
Application #:
|
13630912
|
Filing Dt:
|
09/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
04/03/2014
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SUPPORTING LAYER OVER SEMICONDUCTOR DIE IN THIN FAN-OUT WAFER LEVEL CHIP SCALE PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2017
|
Application #:
|
13645385
|
Filing Dt:
|
10/04/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/31/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT IN FO-WLCSP USING LEADFRAME DISPOSED BETWEEN SEMICONDUCTOR DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2015
|
Application #:
|
13645397
|
Filing Dt:
|
10/04/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/31/2013
| | | | |
|
Title:
|
FLIP CHIP INTERCONNECTION HAVING NARROW INTERCONNECTION SITES ON THE SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13649834
|
Filing Dt:
|
10/11/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
|
Title:
|
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2016
|
Application #:
|
13653242
|
Filing Dt:
|
10/16/2012
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Conductive Ink Layer as Interconnect Structure Between Semiconductor Packages
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
13664626
|
Filing Dt:
|
10/31/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING REPASSIVATION LAYER WITH REDUCED OPENING TO CONTACT PAD OF SEMICONDUCTOR DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2017
|
Application #:
|
13678134
|
Filing Dt:
|
11/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RF FEM WITH LC FILTER AND IPD FILTER OVER SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
13679615
|
Filing Dt:
|
11/16/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
|
Title:
|
PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13679792
|
Filing Dt:
|
11/16/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING FO-WLCSP HAVING CONDUCTIVE LAYERS AND CONDUCTIVE VIAS SEPARATED BY POLYMER LAYERS
|
|
